RU2325689C2 - Portable data storage unit with multiple memory units - Google Patents

Abstract

FIELD: mechanics.

SUBSTANCE: said portable data storage unit incorporates data interface for transmitting data to the device and back (USB-interface), interface controller (USB-controller), main control centre and two or more flash-memory AND-NOT units. Interface controller is implemented so as to provide for possibility to transmit data received via the interface to the main control centre, which controls memory units operation by sending thereto identical control data via corresponding signal lines. Main control centre is able to send data to flash-memory AND-NOT units simultaneously, via corresponding 8-bit buses. When data shall be stored, it is divided into groups, which are sent to corresponding memory units, and both memory units recieve commands to save data simultaneously. When data shall be extracted, both units receive commands to record data to the main control centre simultaneously.

EFFECT: enhanced data transmission rate.

14 cl, 5 dwg

Description

Technical field

The present invention relates to portable data storage devices and methods for using these devices to store and retrieve data recorded on them.

State of the art

In the past few years, there has been great interest in creating storage devices that contain flash memory and which can be connected to the computer's serial bus. The main document in this area is WO01 / 61692, which describes a device that subsequently entered the market under the trademark "Thumbdrive". In one of the embodiments of the invention described in this document, the universal serial bus (USB) plug, integral with the device case, is directly connected to a USB socket on a computer, so that the computer is capable of transferring data to and from flash memory -Memory of a portable storage device under control of a universal serial bus controller (USB controller). Various improvements have been proposed for this device. For example, WO 03/003282 describes a device that can be equipped with a fingerprint sensor, and in which access to data stored in this device is permitted only when the fingerprint sensor authenticates the user by comparing a scanned fingerprint user with pre-stored data. A description of both of these documents is incorporated herein by reference.

Figure 1 shows a possible structure of such a portable storage device. The portable storage device is located in the housing labeled 1. It includes a USB controller 2, which controls a USB interface 3 (i.e., a USB plug), which connects directly to serial bus 4 (i.e., a USB outlet) the host computer 5. Data transmitted to the USB interface 3 from the host computer 5 passes through the USB controller 2 to the host control unit 7. Data packets are multiples of 512 bytes. The main control unit 7 passes these data packets through an 8-bit bus 8 to the NAND 9 flash memory. The main control node 7 controls the NAND 9 flash memory using control signals that are transmitted along one or more lines, schematically indicated 6. Typically, these lines 6 include one line that carries a “command latch on” (CLE) signal, indicating that any command (for example, a REQUEST enable signal or an READ enable command) is being written or will soon be written to flash memory 9 using bus 8; a line that carries an address latch enable signal (ALE) indicating that the bus is currently transmitting or will soon begin transmitting to the flash memory 9 via bus 8 physical address data indicating a cell in the memory 9; and a line that sends a CONNECTION enable signal, which must have a specific meaning for the flash memory in order to power it. The NAND 9 flash memory is configured to store 512-byte sections of data in the corresponding “windows”, each of which also contains a sector (for example, 10 bytes) that stores data that checks for correct storage (that is, this sector works similarly control bit). When data is transferred from the device, it passes in packets of 512 bytes from the NAND flash memory 9 through an 8-bit bus 8 to the main control node 7. The main control node 7 sends 512-byte packets to the USB controller 2, which sends them from the device 1 via the USB interface 3 to the main computer 5.

Figure 2 shows a second possible form of a known storage device. Elements having the same values as in FIG. 1 are denoted by the same reference numbers. In contrast to the device of FIG. 1, the device of FIG. 2 includes a second NAND flash device 19, which is connected to the same bus 8. The main control node controls the second memory 19 using a set of control lines 16. In practice some pins of the main control unit 7 sending control signals can be connected simultaneously to one of the lines 6 and to one of the lines 16, so this pin simultaneously sends the same control signals to both memory 9, 19, but at least least, the CONNECTION signal is not sent tsya in both memories together. More specifically, when the main control node must write data to memory, it turns on only one of memories 9, 19, sending it a CONNECTION signal. While the connection signal is being sent to this memory, the main control unit first sends the command latch on (CLE) signal to this memory via one of the suitable lines 6, and at the same time sends the RECORD command (chip operation code) to bus 8. Later, while the connection signal is still transmitted of this memory, the main control unit sends an address latch (ALE) signal through one of the suitable lines 6 and simultaneously sends the address data via bus 8. Then, while the CONNECTION signal is still transmitted to this memory, the main control unit Ia 8 uses the bus to send that memory data to be stored on it. Only the memory 9, 19, which is connected by the CONNECTION signal, saves the data in the cell indicated by the address data, even if both microcircuits receive data for storage, and can also receive command latch (CLE) and address latch (ALE) signals.

Similarly, when the memory management device needs to read data, it only connects one of the memories 9, 19, using one of the corresponding lines 6 or lines 16, in order to send a CONNECTION signal. While the CONNECTION signal is transmitted, the main control node uses one of lines 6 or lines 16 to send a command latch (CLE) signal to this memory and at the same time uses bus 8 to send an READ enable command to this memory (i.e., the READ operation code ), using bus 8. Then, while the CONNECTION signal is transmitted, the main control unit uses one of the suitable lines 6 or lines 16 to send this memory of the address latch (ALE) signal and simultaneously sends address memory to this memory using bus 8. Flash memory b 19 in response, writes data to bus 8.

The term “read command” is used herein to refer to data sent by the main control unit (GUU) to the storage device at the same time as the CONNECTION signal, which causes the storage device to transmit data. Thus, as described above, the “read command” is the first command latch control signal (CLE) sent to the control line, and at the same time, the enable read command is sent to the bus; and then the address latch control signal (ALE) is sent to the control line, and simultaneous address data is sent to the bus.

The term “write command” is used in this document to refer to data sent by the main control unit (GUU) to the storage device at the same time as the CONNECTION signal, which configures the storage device to receive and store data. Thus, as described above, the “write command” is the first command latch control signal (CLE) sent to the control line, and at the same time, the enable write command is sent to the bus; and then the address latch control signal (ALE) is sent to the control line, and simultaneous address data is sent to the bus.

The available versions of devices 1 on the market, described above, use the universal 1.1 USB serial bus standard, in which the data transfer rate is limited to 15 megabytes / s (i.e. 1.2 megabytes / s), but the industry is switching to using the USB standard 2.0, in which the data transfer rate is 480 megabits / s (i.e. 40 megabytes / s). These latest devices use the read and write methods described above.

SUMMARY OF THE INVENTION

The present invention aims to provide a new and useful portable data storage device, and in particular, a device having a higher data rate than the known devices described above.

The present inventors realized that when a faster data transfer standard is adopted than the universal 1.1 USB serial bus standard, then a critical data restriction (i.e. bandwidth limitation) can move from the USB interface to other places in the storage device data. In particular, an 8-bit bus connection to the NAND flash memory node may become a critical limitation.

One way to solve this problem would be to design the memory as a set of 2 chips, in which data is written simultaneously to two flash memory devices AND NOT via a 16-bit bus. However, this decision is complex.

In general terms, the present invention proposes that the main control node transfers data simultaneously to two or more AND memory devices and via parallel buses that are allowed to work at the same time.

In typical embodiments, one or more (preferably all) of the pins of the main control node that sends control signals are paired with two conductive paths leading to two storage devices, respectively.

This means that each of the storage devices will receive the same amount of data. For example, if two storage devices are available, each will receive half the data that has been transferred for storage.

More specifically, the first embodiment of the present invention provides a portable storage device including:

data interface for transferring data to and from the device,

interface controller

main control node

at least two AND-NOT flash memory devices connected via respective buses to the main control unit for transferring data to and from it,

wherein the interface controller is configured to forward data received through the interface to the main control node,

moreover, the main control node is configured to:

dividing the data received from the interface controller into data groups;

transferring different groups of data to each of the NAND flash memory devices, simultaneously using the corresponding data buses; and

controlling flash memory devices AND-NOT, using control signals that are sent to both flash memory devices AND-NOT, the memory management device transmitting at least CONNECTION signals to both flash memory devices AND-NOT and at the same time transmitting data groups using the specified buses.

Preferably, all control signals sent to the AND memory devices are NOT identical. Undoubtedly, they preferably come from the same pins of the main control node, and each of these pins is connected to the corresponding inputs of the control signals of both flash memory devices AND.

The interface is preferably a universal serial bus (USB) interface, even more preferably, a USB 2.0 or higher interface. However, the present invention is not limited in this regard, and the interface can be any other type of interface, such as a Firewire high speed serial local bus interface (e.g., Firewire connector).

Brief Description of the Drawings

Here, preferred features of the present invention will be described, solely for the sake of explanation, referring to the following drawings, of which:

figure 1 shows a first configuration of a known portable storage device;

figure 2 shows a second configuration of a known portable data storage device;

figure 3 shows the configuration of a portable storage device, which is an embodiment of the present invention;

and

4 and 5 are process flow diagrams of the embodiment of FIG. 3.

Detailed Description of Embodiments

Figure 3 shows the structure of a portable storage device, which is an embodiment of the present invention. Elements of this embodiment corresponding to known devices in FIGS. 1 and 2 are denoted by the same corresponding reference numbers.

Like the known devices of FIGS. 1 and 2, the data storage device of FIG. 3 includes a housing 1 comprising a USB interface 3 for connecting to the USB interface 4 of the host computer 5. Usually, the USB interface 3 is a USB plug, directly connected to USB interface 4, which is a USB outlet. However, in other possible embodiments of the invention, it is possible to use a cable between interfaces 3, 4. In addition, the USB interfaces 3, 4 of the embodiment of FIG. 3 can be replaced by other data interfaces, such as high-speed serial local bus interfaces (Firewire interfaces) .

The USB interface 3 is controlled by the USB controller 2. It is preferred that the USB controller 2 and interfaces 3, 4 operate in accordance with a universal serial bus (USB) standard having a data transfer rate of at least 480 megabits / s, such as USB2.0 standard. Preferably, this portable storage device receives power from the host computer via interfaces 3, 4.

The USB controller 2 transfers the data received from the interface 3 to the main control unit 7 (GUU), which is usually made in the form of a group of single integrated circuits having electrical contacts, referred to here as pins. The main control unit 7 (GUU) outputs data through 16 output pin contacts. Eight of these output pin contacts are connected to the first 8-bit bus 8, and the other eight output pin contacts are connected to the second 8-bit bus 18. Buses 8, 18 are connected to two 8-bit flash memory devices AND-NOT 9, respectively 19.

The main control unit 7 (GU) controls the storage devices 9, 19 by means of control lines 6 connected to the input pin contacts of the control signal of the memory device NAND 9, and control lines 16 connected to the input pin contacts of the control signal of the memory device NAND 19 The main control unit (GUU) has a number of pins 11 that transmit control signals (such as the control signal of the address latch ALE, the control signal CONNECTION and the control signal of the command latch CLE), The first of these pins is connected to the corresponding pin 6 and lines to respective lines of pins 16. Thus, the main control unit (SUM) transmits the same control signals simultaneously to two memories 9, 19.

USB controller 2 usually transmits any data received through interface 3 to the main control unit 7 (GUU) in 512 byte packets. The main control unit 7 (GUU) divides this data into groups of data packets of 256 bytes in size. First of all, the pins 11 of the control signals of the main control unit 7 (GUU) simultaneously transmit the control signal of the command latch CLE and the control signal CONNECTION to both memory, and at the same time use both buses 8, 18 to transmit the RECORD commands (i.e., the RECORD operation code) to both memory 9, 19. Then the main control unit 7 (GUU) transmits the control signal CONNECTION and the control signal of the address latch ALE simultaneously to two memory 9, 19, and (usually simultaneously), using buses 8, 18, transfers to two memory 9, 19 corresponding physical addresses in storage devices 9, 19 on which this data is to be recorded. Following this, and while the main control unit 7 (GU) is still transmitting the CONNECTION control signal to both memories 9, 19, the main control unit 7 (GU) uses buses 8, 18 to transmit portions of data packets that should be written to this address to the corresponding memory 9, 19.

Preferably, each word in the packet that the main control unit 7 (GUU) receives from the USB controller 2 is divided into two bytes, which are simultaneously transmitted to two respective storage devices 9, 19 via the corresponding buses 8, 18. These two bytes, preferably are stored on the respective storage devices 9, 19 at the corresponding addresses. This is because both memory devices are preferably sent the same address data from the main control unit 7 (GUU) via the buses 8, 18 while the address latch signal ALE has configured the memory 9, 19 to recognize these address data. Note, however, that these physical addresses can be different, for example, they can be part of the same “row” in storage devices (in flash terminology, “row” (or “block”) is a set of “pages” that in standard flash memory devices, it must be deleted entirely; thus, the physical address in this memory is standardly encoded as a number representing a row, followed by a number indicating a “branch”, i.e. a specific page inside that row), but on the same position of the "branch" inside series. " The advantage of this scheme is simplicity. However, in other embodiments, 512 bytes may be shared in other ways.

When it is necessary to extract data from a portable storage device (for example, in response to a control input signal to a portable storage device via interface 3), the main control unit 7 (GU) uses a corresponding line from control signal lines 6 and a corresponding line from control signal lines 16 to send CONNECTION control signals to both memories, and at the same time use the corresponding line from control signal lines 6 and the corresponding line from control signal lines 16 to send directs the command latch signal CLE in both memory and simultaneously uses the bus 8 to send a READ command resolution (i.e. READ opcode) to both memory. Then, while the CONNECTION code is still being sent to both memories, the main control unit 7 (GU) uses a suitable line from the control signal lines 6 and a suitable line from the control signal lines 16 to send the control signal of the address latch ALE to both memory 9, 19, and at the same time uses bus 8 to send address data to both memories. In response, and while still in the process of receiving the CONNECTION control signals, the memory 9, 19 transmit the corresponding data to the corresponding buses 8, 18. Thus, the main control unit (GU) receives 16 bits of data in each cycle. It transfers this data via USB controller 2 to USB interface 3, which transfers it further to interface 4.

Figure 4 shows the process of storing data in the device of figure 3. At step 1, the interfaces 3, 4 receive a data packet, which is transmitted from them to the interface controller, and then to the main control node 7. In step 2, the main control node 7 divides the data packets received from the interface controller word by word into groups of data packets, each of which contains a single byte of data to be stored. In step 3, the main control unit 7 transmits the CONNECTION control signal and simultaneously the RECORD instruction (i.e., first the CLE command latch control signal and simultaneously the write enable command; then the ALE address latch control signal and simultaneously the address data) to both memory devices 9, 19. At step 4, while the CONNECTION control signal is still being sent, the main control node transmits different groups of data packets simultaneously to each of the NAND flash memory devices 9, 19 simultaneously through different corresponding e buses 8, 18, and in step 5, the corresponding flash memory devices 9, 19 store groups of data packets.

Figure 5 shows the process of extracting data from the portable data storage device in figure 3. In step 11, the main control unit 7 (in response to an instruction received from outside this device) transmits a CONNECTION control signal and a read order at the same time (i.e., first the CLE command latch control signal and the read enable command at the same time; then the ALE address latch control signal and simultaneously address data) simultaneously to flash devices 9, 19. At step 12, while the CONNECTION control signal is still being transmitted, flash devices in response to read instructions simultaneously transmit data to the chapters the second control node 7 via the corresponding buses 8, 18. At step 13, the main control node 7 combines the corresponding data bytes received from the flash memory devices 9, 19 into words from which data packets are formed and transmits these data packets to the interface controller 2. At step 14, the interface controller sends these data packets via interface 3 from this device.

Note that step 3 and step 11, in turn, are performed in the following 6 sub-steps:

a) memory chips 9, 19 are connected (both memory chips are supported on throughout the recording);

b) a command command latch (control signal) is sent to both microcircuits;

c) an operation code command is sent via the data bus 8, and the operation code will be interpreted by memory chips 9, 19 as a command;

d) the command command latch for both chips is prohibited;

d) the address latch command is turned on;

f) an address operation code is sent via the data bus, and the operation code will be interpreted by memory chips 9.19 as an address;

g) the address latch command is prohibited.

It is necessary to understand that the processes in figures 4 and 5, as a rule, occur on the fly, on a word by word basis. In other words, FIGS. 4 and 5 show single word processing. Thus, for example, while the indicated device performs step 2 with respect to one word, the interface 3 can carry out step 1 with respect to the subsequent word.

Alternatively, although less preferably, in other embodiments of the invention, the steps of FIGS. 4 and 5 may be implemented with respect to complete data packets. Thus, in the case of FIG. 4, the complete data packet can be received by the main control unit (GUU) and stored in the data cache before the main control unit (GUU) begins to split it and send these groups to the storage devices 9, 19.

The inventors have found that this embodiment is capable of writing data to memory at a speed of 15 megabytes / s and reading data at a speed of 20 megabytes / s. It is both simpler and faster than an alternative, in which the main control unit (GUU) records data in turn to two storage devices.

Note that the above description may, in practice, be complicated by the requirements of AND-NOT flash memory devices. For example, as mentioned above, the windows of a traditional AND-NOT flash memory device can be a two-dimensional array of windows, and only entire rows of memory can be deleted at a time. Thus, when it is desirable to remove several, but not all cells in the row (in order to free them for recording other data in their place) of the storage device 9 in the known devices in FIGS. 1 and 2, the main control unit 7 (GUU) must take measures, to ensure the safety of data in cells that should not be erased. There are several strategies for this. One possibility is that the main control unit 7 (GUU) instructs the storage device 9 to create a copy of the data on the bus 8 that needs to be stored, and so that the main control unit 7 (GUU) saves them in the cache. Then this row on the storage device 9 may be erased, and this data is written back from the cache to the storage device. Another possibility is that the main control unit 7 (GU) instructs the storage device 9 to copy this data from the row that should be erased into another row of the storage device 9.

Both of these possibilities also have analogues in the embodiment of FIG. 3. In particular, the main control unit 7 (GUU) will typically be configured to erase the respective complete rows of both storage devices 9, 19 at the same time, and will be configured to interact with storage devices 9, 19 to ensure that any data in these rows that are not subject to deletion, were saved somewhere before the deletion will be made. Since, as mentioned above, it is preferable that each individual byte received by the main control unit 7 (GUU) from the USB controller 9 is divided between two storage devices 9, 19, and both parts are stored in the respective memory addresses on two storage devices 9, 19, in general, it turns out that the data in the corresponding rows of the corresponding devices to be stored will be in identical positions within the specific rows of the corresponding storage devices 9, 19. Therefore, the main control unit (GU) can save data by transmitting identical control signals to two storage devices 9, 19.

The first opportunity for these control signals is to instruct the storage devices 9, 19 to transfer any data in those rows that should not be deleted to the buses 8, 18, so that the main control unit 7 (GU) could receive this data and save it inside random access memory (RAM) (for example, internal RAM of the main control unit 7 (GUU), which acts as a data cache). Then it can transmit the control signals necessary for the storage devices 9, 19 so that the corresponding rows are removed. After that, it can transfer this data back from RAM to the storage devices 9, 19 at the same time by means of the corresponding data buses 8, 18 for re-recording to the storage devices 9, 19. The main control unit 7 (GUU) sends the address latch ALE enable signals via the lines 6, 16 and addresses via buses 8, 18 in order to indicate their cells in the storage devices 9, 19, where this data should be stored (possibly in a memory cell different from the one where they were originally stored).

Alternatively (i.e., in alternative embodiments of the present invention, or in other ways of driving the same embodiment), the main control unit (GUU) may store some data in any row that must be deleted using lines 6, 16, in order to send identical instructions to the storage devices 9, 19 to copy (or move) this data to other rows. After performing this procedure, the main control unit (GUU) uses lines 6, 16 in order to send each of the storage devices 9, 19 identical instructions that will cause them to erase the data.

Although the invention has been disclosed here with reference only to a single embodiment, many modifications are possible within the scope of the claims of the invention, as should be clear to a person skilled in the art. For example, the number of NAND flash memory devices is not limited to two and can be any larger number. Moreover, although it is preferred that the universal serial bus (USB) standard used by the USB controller is USB 2.0, the present invention can be practiced with any versions of the USB standard that will be implemented in the future.

It should also be noted that embodiments of this invention may have many functions that are not shown in detail here, but which are known in other publicly accessible portable storage devices, such as password protection, access controlled by checking biometric data, such as verification fingerprints etc. The implementation of such functions will be clear to those skilled in the art.

Claims (14)

1. A portable storage device including data interface for transferring data to and from the device, interface controller the main control node, and, at least two AND-NOT flash memory devices connected via respective buses to the main control unit for transferring data to and from it, wherein the interface controller is configured to forward data received through the interface to the main control node, moreover, the main control unit is configured dividing the data packets received from the interface controller into groups of data packets; transmitting different groups of data to each of the NAND flash devices at the same time using the appropriate data buses; and controlling AND-NOT flash memory devices using control signals that are sent to said at least two AND-NOT flash memory devices, wherein said memory control device transmits at least CONNECTION signals to said at least two flash memory devices AND NOT, and at the same time transmits data groups using the specified buses. 2. The device according to claim 1, in which the NAND flash memory devices are configured to simultaneously transmit groups of data packets to the main control node, the main control node being configured to connect them to form data packets and transfer these data packets to the controller interface for transmission through the interface. 3. The device according to claim 1, which includes two AND-NOT flash memory devices, the main control node being configured to separate data packets into groups of data packets, where each word of this data to be stored is divided into two bytes, which included in the data packet groups for the various NAND flash memory devices. 4. The device according to any one of the preceding paragraphs, in which the main control unit sends identical control signals to the simultaneously indicated at least two flash memory devices AND NOT via the pins of the main control unit, each of which is connected by electrical connection to the control signal line, moreover, each control signal line leads to the corresponding inputs of the control signals of each of the flash memory devices AND. 5. The device according to claim 4, in which the memory management device transmits the identical signals WRITE, READ, CONNECTION and the address latch (ALE) signal to the corresponding storage devices. 6. The device according to claim 1, wherein said interface is a universal serial bus interface (USB interface), and the interface controller is a universal serial bus controller (USB controller). 7. The device according to claim 6, in which the interface operates in accordance with the universal serial bus standard (USB standard) and has a data transfer rate of at least 480 megabits / s. 8. The device according to claim 1, in which the corresponding parallel data buses are 8-bit buses. 9. The device according to claim 1, in which a predetermined packet size is 512 bytes. 10. The device according to claim 1, in which the main control node before transmitting a signal to each of the NAND flash memory devices, which causes them to erase a section in their respective memory areas, instructs each NAND flash memory device to transfer a data group, stored in this section of the memory area, in another cell. 11. The device according to claim 10, in which the specified other cell is in random access memory (RAM). 12. The device according to claim 10, in which the specified other cell is located anywhere in the corresponding memory areas outside the section that is to be deleted. 13. A method of storing data on a portable data storage device including a data interface for transmitting data to and from the device, an interface controller, a main control node containing a cache memory, and at least two flash memory devices AND-NOT, the method contains stages in which: the interface controller sends data packets received through the interface to the main control node, the main control node divides the data packets received from the interface controller into groups of data packets and transmits different groups of data packets simultaneously to each of the NAND flash devices at the same time via different corresponding buses, and controls the NAND flash devices control signals that are sent to said at least two NAND flash memory devices, wherein said memory control device transmits RECORD instructions and CONNECTION control signals to said at least D, two flash devices and NOR, and then, while the control signals connection still sent, transmits a group of data packets to the corresponding flash memory NAND using appropriate bus corresponding to the flash memory device stores a group of data packets. 14. A method of extracting data from a portable data storage device including a data interface for transmitting data to and from the device, an interface controller, a main control node containing a cache memory, and at least two flash memory devices AND-NOT, the method contains stages in which: the main control unit simultaneously sends the corresponding READING instructions and CONNECTION signals to the flash memory devices; flash memory devices in response to the READ instructions, and while still receiving CONNECTION control signals, simultaneously transmit data to the main control node through various corresponding buses; the main control node connects the data received from the flash memory devices to form data packets, and transmits the data packets to the interface controller; and the interface controller sends data packets received from the main control node from the specified device through the data interface.

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