RU2312593C1 - Method and device for detecting cardio cycle start in real time mode - Google Patents

Abstract

FIELD: medicine; medical engineering.

SUBSTANCE: method involves filtering cardiosignal, digitizing it in time, forming threshold levels and comparing each digitized reading to the threshold levels. The number of readings taken in turn between the threshold levels is counted. The counting result reaching value of n, reference point of n-th discrete electric cardiosignal reading of the cardiocycle next in turn is taken for start point on time axis. Discrete readings coming out of the threshold levels earlier than given number of n is reached in counting, the counting restarts from zero. To determine count number of n, two additional threshold levels are formed. One of them is set above zero line at half T-tooth amplitude value and the other one at the same value below the zero line. Each discrete electric cardiosignal reading value is compared to given threshold levels and the number of readings selected in turn between the levels is counted. Maximum value of this kind Nm is determined in each cardiocycle. The value of n is set equal to 1/2 Nm. Device has filter, analog commutator, clock pulse oscillator, four comparators, four threshold level sources, four AND-gate circuits, two pulse counters, digital comparator, unit for setting maximum value and multiplier.

EFFECT: high reliability in determining cardiocycle start in arrhythmia and QRS-complex shape variation cases.

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Description

The invention relates to medicine, in particular to electrocardiography, and can be used to measure the duration of a cardiocycle, signal segmentation, as well as in methods for analyzing heart cycle variability. The method implemented in the device provides an increase in the reliability of determining the beginning of a cardiocycle.

In systems for the automatic assessment of the parameters of an electrocardiogram signal (EX), in particular, in Holter monitoring devices, one of the main tasks is to assess the degree of variability of the cardiac cycle, i.e. detection of arrhythmias, which are a diagnostic indicator of disorders of the cardiovascular system, in particular, conduction disturbance of the passage of pacemaker excitation pulses. In this case, a necessary condition for the diagnosis is a reliable determination of the beginning of the cardiocycle or the allocation of the so-called reference point.

The known method implemented in the device [1], which consists in the fact that allocate R-wave, the amplitude of which form a threshold level for ECS. At the moment of intersection of the cardiosignal with a threshold level, a reference point is formed.

The disadvantages of this method are:

1. In some cases, the amplitude of the R wave of the QRS complex can be comparable with the amplitude of the T wave (this was detected in the first standard lead even in patients with a normal electrocardiogram), which complicates reliable isolation of the QRS complex.

2. In ECS with a split R wave, the reliability of isolating the beginning of the cardiocycle is reduced.

Closest to the proposed method (prototype) is a method for isolating the beginning of a cardiocycle [2], which consists in the fact that the signal is amplified, filtered, sampled. After sampling the EX, its discrete samples are compared with two threshold levels. One level is set above the zero line by half the amplitude of the P wave, and the other is set below the zero line by the same value. If the amplitude of the next sample is between threshold levels, then the count of the number of such samples begins. When the specified number n is reached as a result of the count, the position on the time axis of the last of the counted, that is, the nth discrete counts, is taken as the beginning of the next cardiocycle. If the amplitude of the next discrete counting of the ECS goes beyond the threshold levels earlier than when the number n is reached, then the counting starts anew.

The disadvantage of this method is the following. The use of a constant value of the counting number, determined on the basis of statistical data, reduces the reliability of distinguishing the beginning of the cardiocycle when the duration of the cardiocycle changes, in particular in the presence of arrhythmia. If the count number n is longer than the durations of the TP and ST segments, for example, with an increase in the heart rate and a corresponding decrease in the indicated durations, then the count of the ECS samples will not reach the value n, and the next reference point will be skipped.

The proposed method of allocating a reference point in each cardiocycle eliminates the specified disadvantage of the prototype.

The essence of the proposed method is as follows. To determine the count number n, two threshold levels are additionally formed, one level is set above the zero line by half the amplitude of the T-wave, and the other is set below the zero line by the same value, the value of each discrete ECS sample is compared with these threshold levels, the number is calculated alternately taken samples between these levels, and in each cardiocycle determine the maximum such number Nm, and the number of counts n is taken to be equal to half this value Nm.

. Параллельно осуществляют сравнение каждого отсчета ЭКС с пороговыми уровнями ±Δ₁, ±Δ₂. Если амплитуда очередного отсчета оказывается между пороговыми уровнями ±Δ₂, то начинают счет числа таких отсчетов. Если же амплитуда очередного дискретного отсчета ЭКС выйдет за пороговые уровни ±Δ₂, то счет начинают заново. В каждом кардиоцикле определяют максимальное число соседних отсчетов Nm, расположенных между пороговыми уровнями ±Δ₂. Это число будет больше числа отсчетов, содержащихся в ТР сегменте. Поэтому значение числа счета n для следующего кардиоцикла принимается равным n=k·Nm, где k - коэффициент пропорциональности меньше 1. Для практической реализации k можно принять равным 0,5. Если амплитуда очередного отсчета оказывается между пороговыми уровнями ±Δ₁, то начинают счет числа таких отсчетов. При достижении в результате счета отсчетов между пороговыми уровнями ±Δ₁ числа n принимают за начало очередного кардиоцикла положение на оси времени последнего из сосчитанных, то есть n-го дискретного отсчета (фиг.1). Если же амплитуда очередного дискретного отсчета ЭКС выйдет за пороговые уровни ±Δ₁ раньше, чем при счете достигнуто число n, то счет начинают заново.The count number n can be generated using the fact that the duration of the cardiocycle almost never changes abruptly. To determine the counting number, threshold levels ± Δ ₂ are additionally formed, which are equal, for example, to half the amplitude of the T-wave. Since the amplitude of the T-wave is greater than the amplitude of the P-wave, then

. In parallel, each ECS reference is compared with threshold levels of ± Δ ₁ , ± Δ ₂ . If the amplitude of the next sample is between the threshold levels of ± Δ ₂ , then the count of the number of such samples begins. If the amplitude of the next discrete counting of the ECS goes beyond the threshold levels ± Δ ₂ , then the count starts again. In each cardiocycle, the maximum number of neighboring samples Nm located between threshold levels ± Δ _{2 is} determined. This number will be greater than the number of samples contained in the TP segment. Therefore, the value of the counting number n for the next cardiocycle is taken to be n = k · Nm, where k is the proportionality coefficient less than 1. For practical implementation, k can be taken equal to 0.5. If the amplitude of the next sample is between the threshold levels of ± Δ ₁ , then the count of the number of such samples begins. When the result of counting the samples between the threshold levels of ± Δ _{1, the} number n is taken as the beginning of the next cardiocycle the position on the time axis of the last of the counted, that is, the nth discrete samples (Fig. 1). If the amplitude of the next discrete counting of the ECS goes beyond the threshold levels ± Δ ₁ earlier than when the number n is reached, then the counting starts anew.

The proposed method allows more reliable, compared with the known method (prototype), to highlight the beginning of the cardiocycle for a wide class of electrocardiograms with various modifications of the shape of the elements in the presence of arrhythmia.

Let us explain the principle of achieving a technical result by performing the above actions with an electrocardiogram.

The invention and a possible implementation of the proposed method is illustrated by the following graphic material:

- figure 2 is a structural diagram of a device that implements the proposed method;

- figure 3 is an embodiment of a block 19 for generating a maximum value;

- figure 4 is a timing chart explaining the operation of the device as a whole.

To achieve a technical result, which consists in increasing the reliability of distinguishing the beginning of a cardiocycle in the presence of arrhythmia and variations in the shape of the QRS complex, and implementing the proposed method in a device containing a filter, the input of which is the input of the device, and the output is connected to the information input of an analog key, the control input of which connected to the output of the clock generator, the output of the analog switch is connected to the inverting input of the first comparator and to the non-inverting input of the second comparator, to it the first threshold level source is connected to the inverting input of the first comparator, and the second threshold level source is connected to the inverting input of the second comparator, the outputs of the first and second comparators are connected to the first and second inputs of the first circuit And, the output of which is connected to the first input of the second circuit And, and to the input zeroing the first pulse counter, the second input of the second AND circuit is connected to the output of the clock generator, and the output is connected to the counting input of the first pulse counter, a digital com a parator, third and fourth comparators, third and fourth threshold level drivers, third and fourth I circuits, a second pulse counter, a maximum value generating unit, a multiplier, the output of the analog key being connected to the inverting input of the third comparator and to the non-inverting input of the fourth comparator, to the non-inverting the third threshold source is connected to the input of the third comparator, and the fourth threshold level source is connected to the inverting input of the fourth comparator, the third outputs of the fourth and fourth comparators are connected to the first and second inputs of the third circuit And, the output of which is connected to the first input of the fourth circuit And, to the input of the zero setting of the second pulse counter, and to the first control input of the unit for generating the maximum value, the second input of the fourth circuit And is connected to the output a clock pulse generator, and the output with a counting input of a second pulse counter, the bit outputs of which are connected to the information input of the maximum value generating unit, the output of the latter is connected to the input multiplier, the output of the first pulse counter is connected to the first input of the digital comparator, the second input of the digital comparator is connected to the output of the multiplier, the output of the digital comparator is connected to the second control input of the maximum value driver and is the output of the device.

The device consists (Fig. 2) of a filter 1, an analog switch 2, a clock generator (GTI) 3, comparators 4, 5, 12, 13, threshold level drivers 6, 7, 14, 15, circuits I 8, 9, 16 , 17, counters 10, 18, a digital comparator 11, a maximum value generating unit 19, a multiplier 20.

The input of the filter 1, which is the input of the device, receives an electrocardiogram. The output of the filter is connected to the information input of the analog key 2, the control input of which is connected to the GTI output, the information output of the key 2 is connected to the inverting inputs of the first 4 and third 12 comparators and to the non-inverting inputs of the second 5 and fourth 13 comparators, and is connected to the non-inverting input of the first comparator 4 6 source threshold level + Δ _1, and to the inverting input of a second comparator 5, connected to a source 7 of threshold -Δ _1, to the noninverting input of the third comparator 12 is connected a source 14 are threshold level of + Δ _2, and to the inverting input of the fourth comparator 13 is connected a source 15 threshold -Δ _2. The output of the first comparator 4 is connected to the first input of the first circuit And 8, and the output of the second comparator 5 is connected to the second input of this circuit, the output of the first circuit And 8 is connected to the first input of the second circuit And 9 and to the input "Account" (C) of the counter 12, the second input of the circuit And 9 is connected to the output of the GTI 3, the output of the circuit And 9 is connected to the inputs "Zero setting" (R) of the counter 12 and trigger 14, the input "Count" (C) of the counter 10 is connected to the output of the GTI 3, the discharge outputs of the counter 10 connected to the corresponding inputs of the digital comparator 11, the output of which is the output of the device. The output of the third comparator 12 is connected to the first input of the third circuit And 16, and the output of the fourth comparator 13 is connected to the second input of this circuit, the output of the third circuit And 16 is connected to the first input of the fourth circuit And 17, to the input "Account" (C) of the second counter 18 and to the first control input of the maximum value generating unit 19, the second input of the fourth circuit And 17 is connected to the output of the GTI 3, the output of the circuit And 17 is connected to the “Account” (C) input of the second counter 18, the bit outputs of which are connected to the corresponding bit information inputs of the block 19 shapers Nia maximum value, the last output connected to the input of the multiplier 20, the output of the multiplier 20 is connected to the second input (B) of the digital comparator, whose output is connected to the second control input unit 19 forming the maximum value.

Block 19 forming the maximum value can be performed according to the scheme shown in figure 3. It contains a register 21 and a trigger 22. The input “Input” (D) of the register 21 is the information input of block 19. The output “Output” (Q) of the circuit 21 is the output of the maximum value generating unit 19. The first and second control inputs of this block are the inputs "Reset" (R) and "Installation" (S) of the trigger 22, respectively. The trigger output is connected to the input "Account" (C) of the register 21.

The device operates as follows. The EKS is cleaned by filter 1 from low-frequency additive noise (isoline drift, industrial frequency induction 50 Hz) and is fed to the first (information) input of analog key 2, with the help of which a continuous signal is converted into a discrete one. Under the influence of pulse signals having a repetition period equal to the sampling period and coming from the output of the generator 3 clock pulses (GTI signals in figure 4) to the second (control) input, the analog switch 2 is periodically closed and discrete readouts of the cardiac signal are formed at its output ( signals "Counts EX" in figure 4). Comparators 4 and 5 compare the amplitudes of each sample, respectively, with a positive threshold level and a negative threshold level (levels + Δ ₁ and -Δ ₁ in Fig. 4, b). If the amplitudes of the samples do not go beyond threshold levels, high-level signals are set at the outputs of the comparators; otherwise, low-level signals are set. The AND 8 circuit is an OR circuit for low-level signals, therefore, a low level signal appears at the output of the And 8 circuit every time when the amplitude of the ECS samples exceeds threshold levels (the signal "Set 0 ct.10" in Fig. 4, c). This signal is input to the "Zero" (R) input of the counter 10 and sets the latter to the initial zero state whenever the amplitudes of the discrete samples exceed threshold levels. When the amplitudes of the discrete samples are below the threshold levels, a high level signal is present at the output of the And 8 circuit, which is fed to the first input of the And 9 circuit and allows the passage of its clock pulses from the output of the 3 clock pulses generator (signals “Count 10” on figure 4, g). The pulses passing through the circuit And 9 to the input "Count" (C) are considered counter 10. Figure 4, e shows the output signals of a four-digit binary counter (signals "Outputs of the counter 10") as an example. The corresponding bit outputs of the counter 10 are connected to the inputs of the digital comparator And 11. The output signal of this counter through the digital comparator 11 is compared with the output signal of the multiplier 20, equal to the number of counts n. When the counter counts this number n, a high level signal will appear at the output of the digital comparator 11 (Fig. 4, l). The beginning of this impulse is taken as the beginning of the next cardiocycle. With the arrival of the next ECS count, the output of the counter 10 increases by 1, and a low level signal appears at the output of the digital comparator 11.

Comparators 12 and 13 compare the amplitudes of each sample, respectively, with a positive threshold level and a negative threshold level (levels + Δ ₂ and -Δ ₂ in Fig. 4, b). If the amplitudes of the samples do not go beyond threshold levels, high-level signals are set at the outputs of the comparators; otherwise, low-level signals are set. The AND 16 circuit is an OR circuit for low-level signals, therefore, a low-level signal appears at the output of the And 16 circuit every time when the amplitude of the ECS samples exceeds threshold levels (signal "Set 0 sc. 18" in Fig. 4, f). This signal is input to the "Zero" (R) input of the counter 18 and sets the latter to the initial zero state whenever the amplitudes of the discrete samples exceed threshold levels. When the amplitudes of the discrete samples are below the threshold levels, a high level signal is present at the output of the And 16 circuit, which is fed to the first input of the And 17 circuit and permits the passage of its clock pulses from the output of the 3 clock pulses generator (signals “Count count. 18” on figure 4, g). The pulses passing through the circuit And 17 to the input "Count" (C) are considered counter 18. Figure 4, h shows the output signals of a five-digit binary counter (signals "Counter outputs 18") as an example. This signal is fed to the information input of the maximum value generating unit 19. At the time of the transition of the high-level signal to low at the output of circuit 11, block 19 will go into a “standby” state (trigger 22 “capsizes” and a high-level signal appears at its output). In this state, it will remain until a high-level logic signal transitions to a low level at its first control input. At this moment, i.e. when the ECS count goes beyond the threshold levels ± Δ ₂ and a signal of a low logic level appears at the output of block 16, block 19 will go back to the initial state and remember the value of the input signal that will appear at its output (trigger 22 will go back to the initial state and will occur at its output the transition of the high level logic signal to low, the register 21 will remember the input signal) (figure 4, and). The output signal of block 19 is supplied to a multiplier 20, which generates an output signal proportional to the input with a proportionality coefficient less than 1 (Fig. 4, k) (in Fig. 4, and, for simplicity of understanding, analog signals equivalent to digital are presented) [3] .

This device can be implemented on the basis of 555 series chips. For example, as a digital comparator 11, you can use the chip K555SP1, circuit I 16, 17 - K555LI1, counter 18 - K555IE19, register 21 - K555IR43, trigger 22 - K555TP2. If the proportionality coefficient of the multiplier 20 is, for example, 0.5, then this block can be implemented, for example, on the shift register of the K555IR10 chip. Analog comparators 12, 13 can be implemented on operational amplifiers, for example, the KR1049UD1 chip [4].

The technical and economic effect of the proposed method and device for its implementation is to increase the reliability of the allocation in real time of the beginning of the cardiocycle in the presence of arrhythmia and regardless of possible deviations from the normal parameters of the QRS complex (shape, amplitude, duration). Reliable identification of the beginning of the cardiocycle improves the conditions for its further processing (determining its duration, beginning and end of elements, analysis of rhythm variability, etc.), which in turn provides a better diagnosis of possible diseases of the human cardiovascular system.

Literature

1. Cardiomonitors. Equipment for continuous monitoring of the ECG / A.L. Baranovsky, A.N. Kalinichenko, L.A. Manilo et al.: Ed. A.L. Baranovsky and A.P. Nemirko. M .: Radio and communication. 1993. S.194-204.

2. RF patent 2195164, А61В 5/02 A method for isolating the beginning of a cardiocycle and a device for its implementation / A.A. Mikheev // BI 2002, No. 36.

3. Ugryumov EP Digital circuitry. SPb .: BHV - St. Petersburg, 2000, 289 p.

4. Perelman B.L., Shevelev V.I. Domestic microcircuits and foreign analogues. Reference book, STC Mikrotekh, 1998 - 376 p.

Claims (2)

1. A method for isolating the beginning of a cardiocycle in real time, namely that the electrocardiogram is filtered, sampled by time, threshold levels are formed, one level is set above the zero line by half the amplitude of the P wave and the other below the zero line by the same value , and compare the values of each discrete readout of the electrocardiogram (EX) with these levels, count the number of alternately taken samples located between threshold levels, and if the result is the even of a given number n is taken as the beginning of the next cardiocycle the position of the n-th discrete readout of the electrocardiogram on the time axis, and if the discrete samples go beyond threshold levels earlier than the specified number n is reached when counting, the counting starts again from zero, characterized in that to determine the count number n, two threshold levels are additionally formed, one level is set above the zero line by half the amplitude of the T-wave, and the other is set below the zero line by the same value, a comparison is made the values of each discrete ECS sample with given threshold levels, count the number of alternately taken samples between these levels, and in each cardiocycle determine the maximum such number Nm, and the count number n is taken to be equal to half this value Nm. 2. A device for isolating the beginning of the cardiocycle in real time, containing a filter, the input of which is the input of the device, and the output is connected to the information input of the analog key, the control input of which is connected to the output of the clock generator, the output of the analog key is connected to the inverting input of the first comparator and the non-inverting input of the second comparator, the first source of the threshold level is connected to the non-inverting input of the first comparator, and the second is connected to the inverting input of the second comparator a threshold level source, the outputs of the first and second comparators are connected to the first and second inputs of the first circuit And, the output of which is connected to the first input of the second circuit And, and to the zero setting input of the first pulse counter, the second input of the second circuit And is connected to the output of the clock and the output is with a counting input of the first pulse counter, characterized in that a digital comparator, a third and fourth comparators, a third and fourth threshold level former, a third and a fourth are additionally introduced into the device circuit And, a second pulse counter, a maximum value generating unit, a multiplier, the analog key output being connected to the inverting input of the third comparator and to the non-inverting input of the fourth comparator, the third threshold level source is connected to the non-inverting input of the third comparator, and the fourth is connected to the inverting input of the fourth comparator threshold level source, the outputs of the third and fourth comparators are connected to the first and second inputs of the third AND circuit, the output of which is connected to the first mu input of the fourth AND circuit, to the zero input of the second pulse counter and to the first control input of the maximum value generating unit, the second input of the fourth AND circuit is connected to the output of the clock pulse generator, and the output to the counting input of the second pulse counter, the discharge outputs of which are connected to information input of the maximum value generating unit, the output of the latter is connected to the input of the multiplier, the output of the first pulse counter is connected to the first input of the digital comparator, the second digital input second comparator connected to the output of the multiplier, the output of the digital comparator is connected to a second control input of the maximum value and is an output device.

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