RU2289161C1 - Device for processing two-dimensional and three-dimensional images - Google Patents

Abstract

FIELD: computer engineering; two-dimensional and three-dimensional images processing problem.

SUBSTANCE: device consists of processor matrix, control unit, rotation junction, pressure junction, memory junction matrixes, commutation unit, volume detection junction, and code former. Additional informational input is introduced in the device in every matrix processor local memory input commutator, memory junction matrix, additional pressure junction inputs, connected with processor matrix outputs, additional control unit outputs, connected with additional commutation unit inputs. For each k-th matrix control signal matrix collection of elements is divided into non-overlapping subsets; for each subset first cascade amplifier is introduced. The whole set of m-th cascade amplifiers is divided into non-overlapping subsets; for each m-th cascade amplifiers, excluding the last one, an m+1 cascade amplifier is introduced, output of which is connected with input of every amplifiers of m-th cascade; last cascade amplifiers inputs are connected with corresponding outputs of control unit.

EFFECT: increased speed and accuracy of two-dimensional and three-dimensional images processing.

56 dwg, 2 tbl

Description

The invention relates to computer technology, is intended to solve the problems of processing two-dimensional and three-dimensional images. It can be applied in stationary and on-board systems of technical vision, orientation and navigation of autonomous robots, in computer-aided design systems for the analysis and synthesis of objects of complex geometric shapes. A distinctive feature of the device is its high speed and the possibility of using such a method of programmed processing of scenes when the role of elementary operands is performed not by individual elements of the description of geometric objects, but by whole two-dimensional and three-dimensional images containing processed geometric objects inside themselves. Along with simplifying the programming process, this method allows you to create programs that are invariant with respect to the geometric shape of the processed objects and the spatial position of the objects inside the images. High speed, small size and reliability will allow you to create robots with a fundamentally new level of autonomy.

.A device for parallel processing of three-dimensional scenes [1, 2], which is a multiprocessor SIMD system and consisting of a homogeneous processor matrix of the format A × A × A (where A is an integer), a program control unit, rotation, compression, image memory units, is known . In the device, a high speed of processing three-dimensional scenes is achieved by deeply parallelizing the basic procedures for processing scenes (set-theoretic operations, analysis of objects for intersection, procedures for calculating areas and volumes, geometric transformations of rotation, transfer, compression) performed on binary three-dimensional images of the A × format A × A. The disadvantage of this device is the low processing speed of two-dimensional high-resolution images due to the low degree of parallelization of geometric transformations of transfer, rotation, compression of binary images of the format

.

. Кроме того, данное устройство позволяет выполнять ввод и вывод бинарных изображений формата А×А с высокой степенью параллелизации.Closest to the claimed device is an improved version of the specified device [3], which contains in addition to means for highly parallel processing of binary images A × A × A as well as means for highly parallel processing of binary images

. In addition, this device allows you to input and output binary images of format A × A with a high degree of parallelization.

The disadvantages of the prototype are: low accuracy and speed of solving image processing problems. The disadvantages are caused by: 1) low accuracy and low speed of calculating the volume (area) of the monochrome content of the binary image; 2) low speed of transfer and rotation of composite images of high and ultra-high resolution; 3) low speed of determining the boundary coordinates of a single-color object in a binary image; 4) low speed of image compression; 5) in an irrational way of connecting the image memory with the processor matrix; 6) low speed of information input into the processor matrix; 7) the low maximum allowable frequency of the processor matrix control.

The first reason is due to the fact that to calculate the number of processor elements (PE) of the A × A × A matrix having a logical 1 signal at the output, the prototype uses an analog adder 43 and a pulse voltmeter 44 [3], each i-th input of which connected to the output of the i-th processor element of the matrix A × A × A; the digital code of the sum is formed by analog-to-digital conversion of the signal-result of the summation [1]. If U ₁ is the logical “1” level, U ₀ is the logical “0” level, then, since U ₁ > 0, U ₀ > 0, U ₁ / U ₀ <100, for A≈10 there will be A ³ × U ₀ > 10 × U ₁ , i.e. analog-to-digital calculation of the total number of pixels of a three-dimensional binary image A × A × A having the state “1” (in other words, the calculation of the volume of a single content of the binary image A × A × A) cannot be carried out with an accuracy of one pixel. Accurate volume determination requires additional processing procedures. In addition, the time of such an analog-to-digital calculation is large, with a high resolution of the processor matrix, the amplitude of the signal from the output of the analog adder can reach several tens and hundreds of volts, it is clear that the transient time will be extremely long here. The method of connecting the inputs of the adder to the processor matrix is also unsuccessful. Direct connection with the outputs of the processors will result in switching elements of the adder (and, therefore, additional power consumption) for any change in the status of the outputs of the processors, even when there is no need to measure the volume. In addition, the calculation of the volume in the prototype is performed using a separate command without parallelizing the process of performing this procedure with other operations (for example, rotations and shifts).

. Обработка составных изображений mA×mA×mA (где m>1 - целое) связана с обменом информацией между отдельными фрагментами А×А×А этих изображений, такой обмен сопровождается необходимостью организации временного хранения передаваемой информации. В прототипе обмен целыми фрагментами А×А×А (при поворотах на углы n×90° и при параллельном переносе на m×А шагов содержимого составных изображений, где n, m - целые числа) с наибольшей скоростью осуществляется внутри процессорной матрицы. В то же время конструкция прототипа и его система команд позволяют выполнять обмен целыми фрагментами А×А×А в матрице только с одновременным осуществлением поворота передаваемых фрагментов на углы, кратные 90°, а это замедляет скорость выполнения параллельных переносов (из-за необходимости восстановления углового положения сдвинутого изображения после процедуры переноса). Кроме того, в прототипе любое обращение к памяти изображений (и при записи - команда ВВЫВ [2], и при чтении - команда ЧПИ [3]) сопровождается сдвигом фрагмента А×А×А на шаг, что при организации одношагового переноса составного бинарного изображения mA×mA×mA (где m>2) становится излишним и приводит к необходимости осуществления временного хранения сдвигаемого фрагмента А×А×А в локальной памяти матрицы. Но такое хранение в матрице прототипа, как было сказано выше, связано с необходимостью последующего восстановления угловой пространственной ориентации сохраненного фрагмента. Все это отрицательным образом сказывается на скорости обработки составных изображений в прототипе.The second reason is significant because of the importance of processing composite images in applications. In most tasks, the full placement of objects inside images is possible only at a resolution of S> 100. At the same time, the resolution of the A × A × A processor matrix cannot currently exceed A = 100 (for on-board devices, this figure is much lower) due to reasons related to the need to ensure acceptable dimensions, reliability, power consumption and cost of the device. In this regard, processing of high-resolution images can be carried out only by fragment-by-fragment processing. Moreover, the highest processing speed of three-dimensional images is achieved when the fragment being processed simultaneously is a fragment A × A × A; and the highest processing speed of two-dimensional images is achieved if the fragment being simultaneously processed is a fragment

. The processing of composite images mA × mA × mA (where m> 1 is an integer) is associated with the exchange of information between the individual fragments A × A × A of these images, this exchange is accompanied by the need to organize temporary storage of the transmitted information. In the prototype, the exchange of whole fragments A × A × A (during rotations by angles n × 90 ° and parallel transfer by m × A of the steps of the contents of composite images, where n, m are integers) with the highest speed is carried out inside the processor matrix. At the same time, the prototype design and its command system allow the exchange of entire fragments A × A × A in the matrix only with simultaneous rotation of the transmitted fragments by angles that are multiples of 90 °, and this slows down the speed of parallel transfers (due to the need to restore the angular position of the shifted image after the transfer procedure). In addition, in the prototype, any access to the image memory (during writing, the command EXIT [2], and when reading, the command NIP [3]) is accompanied by a shift of the fragment A × A × A by a step, which when organizing a one-step transfer of a composite binary image mA × mA × mA (where m> 2) becomes redundant and leads to the need for temporary storage of the shifted fragment A × A × A in the local memory of the matrix. But such storage in the matrix of the prototype, as mentioned above, is associated with the need for subsequent restoration of the angular spatial orientation of the saved fragment. All this negatively affects the processing speed of composite images in the prototype.

) с одновременным анализом содержимого этого сдвинутого изображения на пустоту. В момент выхода объекта за пределы изображения определяется искомая х-я координата.The third reason is caused by the lack in the prototype of means for high-speed determination of the position of the object in the binary image and determination of the overall dimensions of the object, this significantly increases the time it takes to solve the problems of processing flat and spatial images. So, the calculation of the extreme left xth coordinate of a single-color object (formed by all pixels of an image with brightness 1) of an arbitrary shape is achieved in the prototype only by repeatedly sequentially performing a one-step shift of a binary image containing an arbitrary shape object to the right (in the direction

) with the simultaneous analysis of the contents of this shifted image to void. At the moment the object leaves the image, the desired xth coordinate is determined.

The fourth reason is due to the wrong choice of the compression axis for modeling geometric transformations of axial compression over the contents of binary A × A images in nodes 4 [3] of compression and the lack of hardware for modeling central compression of A × A images with a maximum degree of parallelization. In the prototype, the role of the compression axis is played by the straight line PR [2], passing through the center of the square A × A and parallel to the side of this square. This reduces the total number of coefficients for which image compression could be implemented with a high degree of parallelization. In addition, the solution of some applied image processing problems (for example, the tasks of constructing three-dimensional images from flat stereo images in real time) require multiple central compression of A × A fragments by a fixed coefficient. In the prototype, such a transformation can only be performed by sequentially performing several axial contractions and rotations, which reduces the speed of solving the problem.

The fifth reason is due to the fact that in the prototype the inputs of the image memory data are connected directly to the outputs of the processor matrix, and the outputs of the image memory data are connected to the inputs of the matrix only through the switching unit. As a result, it became impossible to combine the inputs of the image memory data with its data outputs. This connection method makes it impossible to exchange image memory with image input / output nodes, bypassing the local processor matrix memory, this increases the I / O execution time, and makes the local matrix memory an even more scarce resource. In addition, such a connection increases the cost of additional image memory, reduces the reliability of the device.

The sixth reason is caused by the low speed of entering large amounts of data into the device. So, when entering digitized photo images into the memory of the prototype, the values of the bits of the brightness code of one photo pixel are entered into the processor matrix through various inputs of this matrix. Thus, the correspondence between the entered information about the brightness of the pixel and its y-th and z-th coordinates in the matrix A × A × A is violated. Due to the peculiarities of the image processing process in the devices under consideration (which assumes the existence of such a correspondence between the pixel brightness information and the position of this information in the A × A × A matrix), this input method requires additional procedures to transfer the entered information about each photo pixel to its processor matrix coordinate corresponding to this photo pixel. In addition, the presence in the prototype of only one node input images does not allow you to quickly enter into the device stereo images in order to build on their basis three-dimensional models of objects of photographed scenes. The prototype also lacks hardware and software for parallel input of data from the outputs of sensor arrays (for example, tactile) into the processor matrix A × A × A of the device, and therefore data input from the outputs of such sensors is possible only through the external interface of the prototype control unit . The above reduces the speed of image input.

The seventh reason is due to the fact that in the prototype every k-th control signal of the processor matrix comes from the control unit to all the PE-m of the matrix on the same wire line. Since there are many PE-ins and they are distributed in space, the stray capacitances and resistances of the wire lines are high, which reduces the maximum permissible matrix control frequency. The simple refinement of the control output in order to increase the rate of recharge of stray capacitances is inefficient, because with increasing current, the area of printed conductors increases (which leads to an increase in stray capacitances) and the level of interference increases. The used elemental base and the supporting structure of the prototype do not allow to reduce the dimensions of the device and increase the density of installation. All this reduces the maximum allowable frequency of the processor matrix control, and therefore reduces the computing performance of the device as a whole.

The aim of the invention is to increase the speed and accuracy of processing two-dimensional and three-dimensional images.

This goal is achieved by the fact that an additional information input is connected to the information output of the register of this processor in the input switch of the local memory of each matrix processor, an additional register is introduced into each matrix processor, the information input of which is connected to the information output of the local memory of this processor, the control input is connected with an additionally entered control output of the control unit, and the information output is connected to the corresponding input of the volume detection unit and with the corresponding input of the fill code generator, the volume determination unit is made in the form of a digital combinational adder, the fill code generator is made in the form of several unconnected multi-input OR circuits, the outputs of which are connected to additionally entered information inputs of the control unit, a matrix of buffer nodes is introduced memory, each node of which consists of two single-bit registers, the information input of the first register is connected to the corresponding output of the processor matrix, the input input is connected to the local memory recording control input, the information output is connected to the information input of the second single-bit register, the control input of which is connected to the control input of the operand register of the matrix processor, and the information output is connected to the corresponding inputs of the switching unit, additional compression nodes are introduced in which additional inputs connected to the outputs of the processor matrix, and the outputs are connected to the information inputs of the switching unit, information input and information the output of each memory node is connected to the corresponding input of the processor matrix, which is both an information input and an information output of the device; introduced additional outputs of the control unit associated with additional inputs of the switching unit, the additional outputs of which are connected to the control inputs by connecting the information outputs of the sensors to the information inputs of the processor matrix, for each k-th signal of the matrix control, many matrix elements are divided into disjoint subsets, for each subset the amplifier of the first stage, the output of which is connected to the kth control input of an element of this subset, the whole set of amplifiers of the mth the stage is divided into disjoint subsets, for each subset of amplifiers of the mth stage of the kth matrix control signal, an amplifier m + of the 1st stage is introduced, the output of which is connected to the input of each amplifier of the mth stage of its subset, the inputs of the amplifiers of the last stage are connected to the output a control unit corresponding to the kth matrix control signal.

Unlike the prototype in the claimed device, the volume determination unit is a fully digital circuit, the volume (area) of the image object is calculated with an accuracy of one pixel, the amplitude of the signals inside the unit does not exceed the logical level “1”. Transients inside the node are fleeting, there is no need for a cycle of analog-to-digital conversion - all this increases the speed of image processing. The inputs of the adder are not directly connected to the outputs of the PE, therefore, changing the state of the outputs of these PEs does not lead to the obligatory switching of the elements of the adder and to additional energy consumption. Volume calculation is performed in parallel with other operations (rotations and shifts), which also increases the processing speed.

Unlike the prototype, the claimed device implements transfer commands (PRN a1, a2; PRN +; PHV a1, a2) that allow transferring the contents of a binary fragment A × A × A without changing the angular position of this content and per unit of clock cycles. In addition, addressless commands (SDV, SDV +, SDLU, INE +, P1X, P1X +, P1XV, etc.) have been implemented, which increase the processing speed of two-dimensional and three-dimensional images by reducing the time it takes to update information about the addresses of the image operands used. In each processor of the A × A × A matrix, the function “negation of equivalence” is often implemented in hardware, which is often used when comparing the analyzed images with the reference image.

Replacing the A ^3- input OR circuit of the prototype with the binary image fill code shaper (KZBI) in the claimed device allows to obtain significantly more information about the nature of the distribution of the contents of the binary image A × A × A in one cycle than in the prototype, since the multi-bit KZBI of the claimed device is much more informative than the single-bit output of the A ^3- input circuit OR prototype. So, in the claimed device to determine the boundary x-coordinates of the object inside the image A × A × A, only one cycle of access to the shaper KZBI is required, and in the prototype this requires a whole processing procedure, consisting of several one-step shifts of the contents of the image A × A × A and several cycles of accessing the A ³ input circuit OR.

In the compression nodes of the claimed device, the compression axis does not pass through the center of the square A × A (as in the prototype), but along the side of this square, therefore, the range of coefficients, axial compression of the image A × A to which can be performed with the maximum degree of parallelization, in the claimed device twice as wide as in the prototype. In addition, the compression nodes of the claimed device are hardware implemented central image compression operations A × A, performed with the utmost degree of parallelization. All this increases the processing speed.

Unlike the prototype in the claimed device, the inputs and outputs of the same name in the image memory are combined and connected only with the inputs of the processor matrix of the same name, as a result, the number of wire connections and electrical connections between the electronic components of the device has become smaller. The exchange of information between the image memory and input-output nodes became possible without the participation of the processor matrix, which increased the exchange rate. There was an opportunity to further increase the image memory.

Unlike the prototype in the claimed device, the input of 2 ^a- level digitized fragments A × A of photo images is carried out by sequentially inputting a binary images A × A in compliance with the correspondence between the bit bit of the pixel brightness code and the coordinate position of this pixel in the image, as a result, upon completion of input There is no need to perform additional procedures for transferring information about the brightness of a pixel from neighboring matrix processors to its matrix processor. In addition, the composition of the claimed device introduced an additional site for inputting photo images, which made it possible to input and process stereo images.

Unlike the prototype, the claimed device uses a more advanced special elemental base and another type of supporting-connecting structure, which allows to reduce the dimensions of the device and stray capacitance of wire connections. In addition, the wired network of each k-th signal of the matrix control is divided into several sections with a stray capacitance not exceeding the permissible value of C _add . Each such section is recharged using an additionally introduced amplifier that transmits the kth control signal either directly from the control unit or through a serial chain of relay amplifiers, while the area (and capacity) of the conductors does not increase. Since the recharge time of parasitic capacities is reduced, the maximum allowable frequency of the processor matrix control in the claimed device will be higher than in the prototype.

. Фиг.4 поясняет принцип реализации в устройстве одношагового переноса плоских изображений формата

в направлениях ОпХп и ОпYп. На фиг.5 показаны системы процессоров матрицы А×А×А, являющиеся замкнутыми относительно своих ортогонально-кольцевых связей (ОКС) и реализуемые при помощи микросхемы БИС24. На фиг.6, 7 изображены вариант схемы узла определения объема и вариант схемы формирователя КЗБИ соответственно. Фиг.8 поясняет реализацию в устройстве операций переноса и поворота составных трехмерных изображений на углы, кратные 90°. На фиг.9, 10, 11, 12, 13 показан полный спектр р-дискретизирующих преобразований, моделирующих повороты бинарного изображения 9×9 на углы 0°<α≤45°. Полный спектр р-дискретизирующих преобразований, моделирующих геометрические преобразования сжатия бинарного изображения 9×9, показан на фиг.14. Фиг.15 иллюстрирует программное сжатие бинарного изображения А×А×А. Фиг.16 поясняет принцип моделирования поворота трехмерных бинарных составных изображений на угол, не кратный 90°. Фиг.17, 18 поясняют принцип моделирования поворота двумерных бинарных составных изображений на угол, не кратный 90°. Фиг.19 поясняет принцип моделирования центрального сжатия двумерных бинарных составных изображений. Фиг.20 поясняет принцип построения трехмерных моделей объектов по их плоским стереоизображениям. Принципиальная схема микросхем БИС24А, БИС24 В, БИС24С, БИС24D показана на фиг.21, их корпуса и расположение выводов показаны на фиг.22. На фиг.23, 24 изображены принципиальные схемы микросхем БИССС и БИСП соответственно. На фиг.25 показан вариант конструкции платы БОХВИ. На фиг.26 представлен чертеж печатных проводников одной из плат БОХВИ. На фиг.27 изображена функциональная схема узла ввода фотоизображений.Figure 1 shows the functional diagram of the device. Figure 2 shows a General view of a variant of the device. Figure 3 shows a schematic diagram of a processor element of the matrix A × A × A and shows the main data transmission paths inside and outside the matrix when performing the operation of a one-step transfer of the binary image A × A × A in the direction

. Figure 4 explains the principle of implementation in the device one-step transfer of flat format images

in the directions OpHp and OpYp. Figure 5 shows the processor system matrix A × A × A, which are closed relative to their orthogonal-ring bonds (ACS) and implemented using the chip BIS24. Figures 6, 7 show a variant of the circuit of the volume determination unit and a variant of the circuit of the KZBI shaper, respectively. Fig.8 explains the implementation in the device of the transfer and rotation of composite three-dimensional images at angles that are multiples of 90 °. Figures 9, 10, 11, 12, 13 show the full spectrum of p-sampling transformations simulating the rotation of a binary image 9 × 9 at angles 0 ° <α≤45 °. The full range of p-sampling transformations modeling geometric compression transformations of a 9 × 9 binary image is shown in FIG. 15 illustrates software compression of an A × A × A binary image. Fig.16 explains the principle of modeling the rotation of three-dimensional binary composite images at an angle not a multiple of 90 °. 17, 18 explain the principle of modeling the rotation of two-dimensional binary composite images by an angle that is not a multiple of 90 °. Fig. 19 illustrates the principle of modeling central compression of two-dimensional binary composite images. Fig. 20 illustrates the principle of constructing three-dimensional models of objects from their flat stereo images. The circuit diagram of the BIS24A, BIS24 V, BIS24S, BIS24D microcircuits is shown in Fig. 21, their cases and pinouts are shown in Fig. 22. On Fig, 24 shows a schematic diagram of a chip BISSS and BISP, respectively. On Fig shows a variant of the design board BOCHVI. On Fig presents a drawing of the printed conductors of one of the boards BOHVI. On Fig depicts a functional diagram of the node input image.

The device consists of a control unit 1 (CU) and a unit 2 for processing, storage, input and visualization of images (BOCHVI). Block 1 includes a central control processor 3 with register 4 microwaves and programmable registers 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, memory 15 programs and data, controllers 16 of external devices 17, multiplexer 18 of the local memory address, elements 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 And, trigger 29, delay element 30. Communication of block 1 with external devices is carried out via interface 31. Block 2 consists of matrix 32 processors 33, memory 34 images, switch 35 turns, node 36 compression, switch 37 cyclic transfer, buffer memory 38, b farm memory 39, switch 40 3D-shifts, switch 41 2DX-shifts, switch 42 2DY-shifts, node 43 for determining the volume, shaper 44 code fill binary images (KZBI), nodes 45 input image, matrices 46 tactile sensors, node 47 display switch 48 words. The node 36 consists of a transducer 49 compression and switch 50 compression. Each processor 33 consists of a local memory 51, a single-bit register 52 of the first operand, a single-bit register 53 of the second operand, a single-bit register 54 of the volume, a local memory input switch, consisting of OR circuit 55, circuits 56, 57, 58, 59, 60, 61, 62, 63 And, in addition, the processor 33 includes an arithmetic-logical unit, consisting of an AND-NOT circuit 64 and a “denial of equivalence” circuit 65 (modulo 2 addition). The microoperation code is decoded in the matrix 32 by decoders 66. The input control code of the matrix 32 is decoded by the decoder 67. The volume determination unit 43 consists of adders 68, 69, 70. Each photo image input unit 45 consists of a matrix 71 of CCD devices 72, switches 73, and analog digital converters 74, multiplexers 75, keys 76, binary counter 77, decoder 78, AND circuits 79, OR 80, CCD control circuits 81.

. На фиг.4 (а, б) показан способ представления содержимого трехмерного бинарного изображения 9×9×9 в виде двумерного бинарного изображения формата 27×27. В таблице 1 перечислены все команды БОХВИ и дано их описание. Каждой команде соответствует своя микропрограмма - набор микрокоманд, последовательное выполнение которых приводит к выполнению операции, заданной в команде. После дешифрации кода операции адрес начального микрослова команды записывается в регистр микроадреса процессора 3. По этому микроадресу из памяти микропрограмм процессора 3 извлекается управляющее микрослово и загружается в регистр 4. Это микрослово содержит управляющее поле, разряды которого используются для генерации сигналов требуемых микроопераций, а также поле следующего микроадреса и поле кода микроветвления. Поле следующего микроадреса содержит базовый микроадрес, который указывает на следующее микрослово при естественной последовательности выборки микрослов. Этот базовый микроадрес может быть модифицирован с целью микроветвления, поле кода микроветвления определяет, какие признаки необходимо проверить и использовать для модификации микроадреса. Часть управляющего поля микрослова образует поле управления БОХВИ, в это поле входят следующие группы двоичных разрядов:The device operates as follows. The memory 15 stores the processing program. Each command of the program before its execution is extracted from the memory 15 and placed in the registers of processor 3, while the address of the first operand is located in register 11, the address of the second operand is in register 12. Next, the operation code of the extracted command is decrypted, after which the processor control microprogram 3 generates microoperation signals needed to complete this command. The command system of the claimed device includes arithmetic-logical commands, conditional and unconditional jump commands, BOCHVI commands. The purpose and method of executing all arithmetic-logical commands, conditional and unconditional transition instructions are completely determined by the selected design of the processor 3, memory 15, interface 31, which are executed according to one of the known schemes (in particular, the central processor, main memory can be taken as their basis and the computer interface "Electronics-100/25"). The content of one-bit words stored at the same address in A ^3- nodes of local memory 51 of processors 33 of matrix 32, depending on the command being executed, is interpreted by the device either as a three-dimensional binary image A × A × A, or as a two-dimensional lantern image of the format

. Figure 4 (a, b) shows a method for representing the contents of a three-dimensional binary image 9 × 9 × 9 in the form of a two-dimensional binary image format 27 × 27. Table 1 lists all the BOCHVI teams and their description is given. Each command has its own firmware - a set of microcommands, the sequential execution of which leads to the execution of the operation specified in the command. After decryption of the operation code, the address of the initial word of the command is recorded in the microaddress register of processor 3. According to this microaddress, the control microword is extracted from the microprogram memory of processor 3 and loaded into register 4. This microword contains the control field, the bits of which are used to generate signals of the required microoperations, as well as the field next microaddress and microbranch code field. The next microaddress field contains the base microaddress, which indicates the next microwave in the natural sequence of sampling of microwaves. This basic microaddress can be modified for the purpose of microbranching; the field of the microbranching code determines which features should be checked and used to modify the microaddress. Part of the control field of the microword forms the control field of the BOCHVI, the following groups of binary digits enter into this field:

UAE COM CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 1 bit 3 categories 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit one
bit

All control commands for the BOCHI device are listed in table 1.

The listed control commands BOCHVI are performed as follows.

The firmware of the P1X command consists of a micro-command, in the control field of the BOCHI microsword of which the bits are set:

UAE COM CP1 CP2 SSM ZLP + A1 + A2 WELL ZUO RFP 0 011 one 0 0 one 0 0 0 0 0

After deciphering the command code, the processor 3 by the clock pulse C1 writes the microword of the P1X command to the microword register 4. After that, the address multiplexer 18 connects the outputs of the first operand address register 11 to the ADR inputs of the processor matrix, and the multiplexers formed by decoders 66 and elements 56, 57, 58, 59, 60, 61, 62, 63 connect the data inputs of the local memory 51 to the outputs respective processors 33 through inputs iX1. By the clock pulse C2, through CWR1, the contents of the local memory 51 are read at the ADR address in registers 52, as a result, the initial (rotatable) three-dimensional binary image A × A × A appears on the outputs oD of all processors 33, and the resulting ( rotated) image A × A × A. At the same time, the contents of the line A × 1 × 1 of the last (with respect to Ox) layer A × A × 1 are recorded in A bits of the program-addressable register 13, this provides the possibility of transmitting data from the BOCHI to the control unit. With the arrival of C3, the WR signal will record the rotated image in the local memory of the processors 33 at the ADR address.

The firmware of the П1Х + command consists of a micro-command, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 011 one 0 0 one one 0 0 0 0 0

The execution of this command differs from the execution of P1X only in that after recording the rotated image in the local memory, the contents of register 11 are increased by 1 by pulse C4 by means of a signal + 1A1.

The firmware of the П1ХУ command consists of one micro-command, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 011 one 0 one one 0 0 0 0 0 0

The execution of this command differs from the execution of P1X only in that the rotated image is read from the local memory simultaneously to register 52 and to register 54 of each processor 33. In this case, the signal CWR3 from the output of element 23 AND sets the trigger flag 29 to log.1 for the duration of the calculation procedure, the volume and the formation of the code KZBI. With the end of reading in the registers 54, the process of calculating the volume of the read image A × A × A and the formation of the code KZBI begins. Then, the signal CWR3, passing through the delay element 30, resets the trigger flag 29 to log.0, informing the processor 3 about the completion of the summation procedure and the procedure for generating the KBDI.

The firmware of the P1X2 a2, a1 command consists of several microcommands, while the first microcommands are connected with reading address a1 and address a2 from memory 15 and writing the read values to register 11 of the address of the first operand and register 12 of the address of the second operand, respectively (method of organizing such reading depends on the choice of one of the known constructions of block 1). After reading the addresses of the operands, a microword is executed, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 011 one 0 0 0 0 0 0 0 0 0

Writing to the local memory is carried out by means of the following microword, the control field of the BOCHI which contains bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP one 011 0 0 0 one 0 0 0 0 0 0

The firmware of the P1X2U a2, a1 command differs from the firmware of the P1X2U a2, a1 command in that the penultimate microword has a bit CCM = 1.

The firmware of the P1 Y command consists of a micro command:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 one hundred one 0 0 one 0 0 0 0 0 0

The execution of the P1Y command differs from the execution of the P1X command in that here the outputs oD of the processors 33 are connected to the inputs of the local memory via the inputs iY1.

The firmware of the P1Y + command consists of a microword:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 one hundred one 0 0 one one 0 0 0 0 0

The execution of the P1Y + command differs from the execution of the P1X + command in that here the outputs oD of the processors 33 are connected to the inputs of the local memory via the inputs iY1.

The firmware of the P1Y2 a2, a1 command starts by reading the addresses a1, a2 (as in the P1X2 a2, a1 command). At the end of the reading, a microword is executed, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 one hundred one 0 0 0 0 0 0 0 0 0

Writing to the local memory is carried out by means of the following micro-command, the control field of which the BOCHI contains bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP one one hundred 0 0 0 one 0 0 0 0 0 0

The firmware of the command P1Y2V a2, a1 differs from the firmware of the command P1Y2 a1, a2 only in that it has a discharge value CCM = 1 in the penultimate microword of the command.

The firmware of the P2Y command consists of a micro-command, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 101 one 0 0 one 0 0 0 0 0 0

The execution of the P2Y command differs from the execution of the P1X command in that here the outputs oD of the processors 33 are connected to the inputs of the local memory via the inputs iY2.

The firmware of the P1Z command consists of a microword whose BOCHI control field contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 110 one 0 0 one 0 0 0 0 0 0

The execution of the P1Z command differs from the execution of the P1X command in that here the outputs oD of the processors 33 are connected to the inputs of the local memory via the inputs iZ1.

The firmware of the P12 + command consists of a microword, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2. + A3 WELL ZUO RFP 0 110 one 0 0 one one 0 0 0 0 0

The execution of the command differs from the execution of the P1X + command in that here the outputs oD of the processors 33 are connected to the inputs of the local memory via the inputs iZ1.

The firmware of the P1ZV command consists of a microword, the control field of the BOCHI which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 110 one 0 one one 0 0 0 0 0 0

The execution of the command differs from the execution of the P1XU command in that here the outputs oD of the processors 33 are connected to the inputs of the local memory via the inputs iZ1.

The firmware of the P1Z2 a2, a1 command starts by reading the addresses a1, a2 (as in the P1X2 a1, a2 command). At the end of the reading, a microword is executed, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 110 one 0 about about 0 0 0 0 0 0

The image-result of the rotation is recorded in the local memory by means of the following microword, the BOCHI control field of which contains bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP one 110 0 0 0 one 0 0 0 0 0 0

The firmware of the P1Z2V a2, a1 command differs from the firmware of the P1Z2 a1, a2 command only in that the penultimate microcommand has a discharge value CCM = 1.

The firmware of the SDV command consists of a micro command, the control field of the BOCHVI microword of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 111 one 0 0 one 0 0 one 0 0 0

After deciphering the code of the ADD command, the central processor 3, according to the clock pulse C1, writes the microword of the ADD command into the microword register 4. After that, the multiplexer 18 connects the outputs of the register 11 of the address of the first operand to the inputs of the ADR of the processor matrix, and the multiplexers formed by decoders 66 and elements 56, 57, 58, 59, 60, 61, 62 and 63 connect the data inputs of the local memory 51 with the outputs oD neighboring (in the direction —Ox) processors 33 through the inputs of the iD processors 33. The inputs of the iD processors 33 related to the first (in the direction Ox) layer A × A × 1 are inputs of the processor matrix 32. The outputs oD of the processors 33 related to the last ( in the direction Ox) to the layer A × A × 1 of the matrix A × A × A, are the outputs and the processor matrix 32. By the clock pulse C2, through the signal CWR1, the contents of the local memory 51 with the address ADR are read into the registers 52, the data of the buffer memory 39 are written to the buffer memory 38. As a result, the initial (shifted) three-dimensional binary image is formed on the outputs oD of the processors 33 A × A × A, and the resulting (shifted) image A × A × A is formed at the data inputs of the local memory 51. With the arrival of C3, the WR signal will write the shifted image to the local memory 51 of the processors 33 at the ADR address, the last layer A × A × 1 of the original image is written to the buffer memory 39 (Fig. 3). Depending on the value of the KUVM field (matrix input control code) of the software-addressable register 14 pointing to the data source for the matrix inputs, the execution of the ADD command is accompanied by:

а) КУВМ = 0000 - by writing the contents of the last layer A × A × 1 of the initial (not shifted) image A × A × A to the first layer A × A × 1 of the resulting (shifted) image A × A × A — cyclic shift;

b) KUVM = 0001 - by recording the state A ^{2 of the} outputs of the buffer memory 38 in the first layer A × A × 1 of the resulting image A × A × A;

на 1 шаг вдоль оси ОпХп (фиг.4 - г, е);c) KUVM = 0010 - by recording part of the contents of the last layer A × A × 1 of the original image A × A × A and part of the outputs of the buffer memory 38 in the first layer A × A × 1 of the resulting image for modeling the operation of shifting a flat image

1 step along the axis of OPXn (figure 4 - d, e);

на 1 шаг вдоль оси ОпYп (фиг.4 - в, д);d) KUVM = 0011 - by recording part of the contents of the last layer A × A × 1 of the original image A × A × A and part of the outputs of the buffer memory 38 in the first layer A × A × 1 of the resulting (shifted) image to simulate the shift operation of a flat image

1 step along the axis OpYn (Fig.4 - c, d);

d) KUVM = 0100 - by writing the contents of the last layer A × A × 1, compressed by a factor k, of the original image A × A × A to the first layer A × A × 1 of the resulting image A × A × A, compression type (axial or central ) and the coefficient number k are determined by the KZP code (parameter value code) of register 14;

e) KUVM = 0101-recording state A ^{2 of the} outputs of the memory 34 images in the first layer A × A × 1 of the resulting image A × A × A;

g) KUVM = 0110 - by writing the contents of the last layer A × A × 1, rotated by an angle α≤45, of the original image A × A × A to the first layer A × A × 1 of the resulting image A × A × A, the angle number α is given KZP code of the register 14;

h) KUVM = 0111 - by writing the state A of the outputs of the software-addressable register 6 into the first layer A × A × 1 of the resulting image A × A × A in the form A of identical lines A × 1 × 1 of this layer;

i) KUVM = 1000-record state A ² outputs node 451 input photo No. 1 in the first layer A × A × 1 of the resulting image A × A × A;

j) KUVM = 1001 - by recording the state of A ² outputs of node 452 for inputting photo image No. 2 into the first layer A × A × 1 of the resulting image A × A × A;

l) KUVM = 1010 - by recording the state of A ² outputs of the matrix of 461 tactile sensors in the first layer A × A × 1 of the resulting image A × A × A;

The firmware of the SDV + command consists of a microcommand whose BOCHI control field contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 111 one 0 0 one one 0 one 0 0 0

The execution of the SDV + command differs from the execution of the SDV command in that, with the end of the shift, the signals + 1A1, + 1A2 increase the operand addresses by 1.

The firmware of the SDLD command consists of one micro command, the control field of which the BOCHI contains bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 111 one 0 one one 0 0 one 0 0 0

The execution of the SDLD command differs from the execution of the SDL only in that the shifted image is read from the local memory both to the register 52 and to the register 54 of each processor 33. At the end of the reading, the process of calculating the volume of the read image A × A × A starts.

The execution of the ADD command a2, a1 differs from the execution of the ADD command only in that before the shift is made, address a1 (in register 11) and address a2 (in register 12) are extracted from memory 15.

The firmware of the PRN + command consists of two microcommands:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 000 one 0 0 0 0 0 0 0 0 0

and

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP one 000 0 0 0 one one one 0 0 0 0

The first micro command reads the original (copied) binary image A × A × A from the local memory 51 at the address stored in register 11 to the registers 52 of the processors 33. The second micro command reads the read image into the local memory 51 at the address stored in the register 12. After copy the contents of registers 11 and 12 is increased by 1.

The firmware of the PRN command a2, a1 differs from the firmware of the PRN + command only in that before the last two microcommands are executed, the addresses a1, a2 are read from memory 15 to registers 11 and 12, respectively.

The firmware of the PRNV command a1, a2 differs from the firmware of the PRN command a1, a2 in that the penultimate microword has the CCM = 1 bit. As a result, immediately after reading the copied image, the calculation of the volume of the read image and the formation of the KBBI begin.

The firmware of the INE + command consists of two microcommands:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP one 001 one 0 0 0 0 0 0 0 0 0

and

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP one 001 0 one about one one one 0 0 0 0

When the first microcommand is executed with the arrival of C2, the first operand image is read into the registers 52, and when the second microcommand is executed via C2, the second operand image is read into the registers 53, then C3 writes the result image of the set-theoretic operation (from the outputs of elements 62 AND NOT) to local memory 51 at the address of the second operand. After that, the contents of registers 11 and 12 are increased by 1.

The firmware of the INE a2, a1 command differs from the firmware of the INE + command in that before the last two microswitches are read, addresses a1, a2 are read from memory 15 to registers 11 and 12, respectively.

The firmware of the CM2 + command differs from the INE + command by the KMO code = 010. The KMO code = 010 also differs in the firmware of the CM2 a1, a2 command from the INE a1, a2 command.

The firmware of the ZPI command consists of one micro-command, the BOCHI control field of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 111 one 0 0 one 0 one one 0 0 one

When the ZPI command is executed with the arrival of the SZ, the state of all A ² inputs of the iD matrix 32 (the information source is determined by the KUVM code) is recorded by the SZP pulse in the memory of 34 images at the address of the SIA, whose value is located in the programmable address register counter 7. At the same time, the contents are shifted by a step matrix at the address whose value is stored in register 11 (to enable operational control of the recorded information). After recording, the contents of the register 7 signal + 1A3 increases by 1.

The firmware of the ZUO command consists of one micro-command, the BOCHI control field of which contains the bits:

UAE Kmo CP1 CP2 Ccm ZLP + A1 + A2 + A3 WELL ZUO RFP 0 111 one 0 0 one 0 one one 0 one 0

When the ZUO command is executed with the arrival of C3, the state of all A ² inputs of the iD matrix (the information source is determined by the KUVM code) is recorded by the SZO pulse in the memory of the display unit 47 at the ALO address, the value of which is located in register 5. At the same time, the contents of the matrix 32 are shifted by a the value of which is stored in register 11 (to enable operational control of the recorded information). After recording, the contents of register 5 by the signal + 1A3 increases by 1. The design and operation of unit 47 do not differ from the design and operation of the prototype display unit.

The adder of the volume determination unit 43 in the general case can be performed according to any of the known binary adder schemes [5]. The choice of a specific circuit of the adder 43 is determined by the choice of the element base of the processor matrix 32 and the method of layout of the electronic components of the matrix 32 on the circuit boards of the device. To reduce the dimensions of the A × A × A matrix and increase the clock frequency of its control, it is necessary to place the matrix components with the highest possible density. Since the entire processor matrix 32 cannot be placed on one semiconductor chip, the processors 33 and part of its interprocessor communications are realized within several (tens to hundreds) crystals, and the other part of the interprocessor communications is in the form of wire bonds between these crystals. The reliability of intercrystal connections is determined by the applied method of making an electrical connection (one-piece connections are more reliable than split ones).

Hence, to increase the reliability of the device, it is necessary to reduce the number of crystals used, increase the share of intra-chip interprocessor connections, and reduce the share of detachable cross-chip connections. At the same time, an unjustified decrease in detachable connections can lead to an unacceptable increase in the length of wire ties or to a sharp decrease in the maintainability of the device. The largest share of prototype interprocess connections is made up of orthogonal-ring connections (ACS), which realize rotations of the contents of the matrix A × A × A by angles n × 90 ° (where n is an integer) around the central orthogonal axes (Ox, Oy, Oz) of the A × cube A × A (FIG. 5-g). Therefore, it is advisable to place all processor elements 33 (with their ACS) inside one crystal, the corresponding cubes 1 × 1 × 1 of which, when the cube A × A × A rotates through angles that are multiples of 90 ° degrees, pass into each other. Processor elements that satisfy this condition form a closed system with respect to their ACS. In the matrix A × A × A, there are 4 types of such closed processor systems (ZPS1, ZPS6, ZPS8, ZPS24) containing 1, 6, 8 and 24 processor elements 33 each, respectively (Fig. 5). The most numerous and universal is a 24-processor closed system (ZPS24) - figure 5 (g). In the case of the placement of ZPS24 inside one crystal (we will call this crystal BIS24 by convention) all the ACS of processors 33 of this ZPS24 are also placed inside this crystal. We take as a basis the above-described method of packaging processors 33 in a chip, then we can offer the following design of the assembly 43 (Fig. 6), which allows high-density packing of crystals of an A × A × A matrix on a board. The node 43 is a multi-stage adder, each first stage 68 of which is located inside the BIS24, is executed according to the parallel combiner adder, and sums the logical states from the outputs of the registers 52 of 24 processors of this crystal; the second stage 69 of the adder 43 is placed inside the same crystal and sums the code from the outputs of the first stage of the adder 68 of its crystal with the output code of the second stage 69 of the neighboring BIS24 crystal.

Summation at this stage is carried out sequentially from crystal to crystal (Fig.6), forming according to the summation scheme a sequential chain of connected BIS24 microcircuits (S-chain). From these BIS24 crystals placed on one side of the BOCHVI board, several such S-chains are formed (independent of each other according to the summation scheme). The execution time of the second summation stage depends on the number of BIS24 crystals included in the longest S-chain (the shorter the S-chain, the higher the speed of summation). The codes of partial sums taken from the outputs of steps 69 of the crystals located at the end of the S-circuits are supplied to the inputs of the following steps-adders 70, made according to one of the known schemes of pyramidal adders [5] using a traditional element base. The microcircuits of stages 70 are located on the circuit board outside the circuit areas occupied by the BIS24 microcircuits (Fig. 26).

A-bit shaper 44 of the binary image filling code (KZBI) consists of A independent single-bit shapers KZBI. Each i-th single-bit KZBI shaper represents an A ^2- input OR circuit, the inputs of which are connected to the outputs of the registers 54 of all processors 33 belonging to the i-th layer A × A × 1 of the matrix. Logical 1 at the output of the jth single-bit KZBI shaper means that the jth layer A × A × 1 of a three-dimensional binary image A × A × A stored at the moment in the registers 54 of the matrix A × A × A is not empty (i.e. e. contains at least one pixel 1 × 1 × 1 in the state log.1). The choice of a specific circuit of the shaper 44 depends on the choice of the element base of the processor matrix and the method of layout of the electronic components of the matrix on the circuit boards of the device. If we take as a basis the above-described method of packing processors 33 in a BIS24 chip, then we can propose the following design of unit 44 (Fig. 7), which allows high-density packing of matrix crystals 32 on a board. Six 4-input elements 441 OR-NOT are introduced into BIS24, one element 44 ₁ per one layer of ZPS24. Processors 33 of the i-th layer of ZPS24 (where 0≤i≤5) are simultaneously included in the j-th layer A × A × 1 (where 0≤i≤A-1) of the processor matrix A × A × A. Each element 44 ₁ is the first stage of the single-bit KZBI shaper, the second stage 442 is made according to the “mounting OR” scheme, the third stage 44 _{3 is} made according to the NAND circuit and combines the outputs of all stages 442 of the j-th single-bit KZBI shaper.

The inputs of the processor matrix 32 are simultaneously information inputs and outputs of the device and allow you to organize high-speed input-output of large amounts of information. In the case of using the claimed device for the purpose of sensing robots, these inputs can be used to enter video information, as well as information coming from the outputs of the arrays of 46 tactile (or other types) sensors that model the robot receptors. The simplest example of a matrix 46 is an array of unconnected pairs of contacts working for closing and opening. A more complex organized array of sensors is encountered when entering photo images from the outputs of nodes 45.

The work of the nodes 45 of the input image will consider the example of a device with a processor matrix 9 × 9 × 9. The luminous flux, modulated by illumination, through the optical system (lenses, fiber optic cable) enters the matrix 71 of 27 CCD devices 72 (Fig.27). Each CCD device 72 focuses its own section of 9 × 243 input image 243 × 243. Each CCD device 72 contains 9 lines of photosensitive elements with 243 elements in each line (Fig.27). Each line has its own shift register, so 9 analog signals are simultaneously taken from one device 72. From 27 devices 72, 243 analog signals corresponding to the horizontal line of the input image are simultaneously taken. CCD devices 72 are combined into groups of 3 devices 72 in each group, each group of devices 72 corresponds to 9 analog-to-digital 8-bit converters 74. The outputs of CCD devices 72 are connected to the inputs of ADC converters 74 using switches 73. Connection of outputs ADC converters 74 to the inputs of the 9 × 9 × 9 processor matrix are implemented using multiplexers 75 and keys 76. The counter 77 controls the switches, while the lower part of the counter (0, 1, 2 bits) controls the switches 75, the oldest part of the counter (3, 4 digits) controls 73. In addition, the third state of the outputs of the switches 76 is controlled by the output of the decoder 67 (Y8 for node 451, Y9 for node 452). The photo image is taken by the CTF team, consisting of a micro command, the control field of the BOCHVI micro-word of which contains the bits:

UAE KMO CP1 CP2 SSM ZLP + A1 + A2 + A3 WELL ZUO RFP 0 111 one 0 0 0 0 0 0 one one about

The SNU signal reads the CCD arrays, after which the circuit 81 shifts the read content to the output of the CCD devices 72. If Y8 (U9) = 1, the signals from the outputs of the switches 74 go to the inputs of the 9 × 9 × 9 matrix. When executing commands like SDV (or RFI), information from the inputs of matrix 32 is recorded in the first layer A × A × 1 of matrix 32 at the address stored in register 11 (or in memory 34 at the address stored in register 7). After recording, the signal + 1A3 adds 1 to the counter 77 and the content at the inputs of the matrix 32 changes. At the same time, the contents of the address register-counters 5, 7 are changed.

Consider the use of the above-mentioned BOHVI control commands to implement the simplest and most commonly used high-resolution image processing procedures. The principle of processing such images using the claimed device is illustrated by the example of a three-dimensional binary composite image 3A × 3A × 3A (Fig. 8-a). A variant of placing this image in the local memory 49 of the matrix 19 is shown in Fig. 8 (b) and consists in placing all 27 of its fragments F (i, j, k) of the A × A × A format at 27 consecutive addresses (ADR1 ... ADR27 ) of memory 49. Let us establish a one-to-one correspondence between the fragments F (i, j, k) of the 3A × 3A × 3A image and the address of this fragment in the memory 49, then the parallel transfer of the contents of the binary image 3A × 3A × 3A to the vector [qA, rA , sA] (where q, r, s are integers) is reduced to a sequential exchange of contents between fragments A × A × A with addresses ADR1 ... ADR27 (by sequentially execution of the PRN commands) and filling the freed fragments with empty contents (using the CM2 a1, a1 commands).

The shift of the composite binary image 3A × 3A × 3A by one step in the direction Ox already implies the exchange of layers A × A × 1 between fragments F (i, j, k). A program that implements a 3A × 3A × 3A image shift by 1 step along Ox is shown in Fig. 8 (c).

Compressions and rotations of images A × A × A are simulated in the device using the so-called. p-discretizing transformations [2, 6]. Moreover, the entire spectrum of p-discretizing transformations simulating the rotation of the binary image A × A at angles 0 ° <α≤45 ° is implemented in the device in hardware (at the rotation nodes), and from the whole spectrum of p-discretizing transformations modeling the geometric compression transformations, part of the transformations (the most frequently used) is implemented in BOCHVI in hardware (in compression nodes), another part of this spectrum is implemented in software. Let us explain what was said on the example of a device with a 9 × 9 × 9 matrix. The full spectrum of p-sampling transformations simulating the rotation of a 9 × 9 binary image at angles of 0 ° <α≤45 ° is shown in Figs. 9, 10, 11, 12, 13. The full spectrum of p-sampling transformations simulating geometric transformations of binary compression 9 × 9 images relative to the aspect side of this image is shown in FIG. 14 (for example, compression of a single row 9 × 1). The method of implementing p-discretizing transformations in the nodes of rotation and compression of the claimed device does not differ from the method of implementing these transformations in the nodes of rotation and compression of the prototype. In addition, the device allows a fairly high speed to simulate the compression of binary images programmatically. Fig. 15 illustrates software compression of an A × A × A binary image relative to the face plane of an A × A × A cube format of this image.

)A×(3/

)A×(3/

)A изображения 3А×3А×3А (фиг.16-а), при этом сначала выполняется расшивка внутреннего куба, затем выполняются повороты его отдельных фрагментов А/

)×(А/

)×(А/

) (фиг.16-6), а затем повернутые фрагменты сшиваются в единое трехмерное изображение (фиг.16-в).Rotations of the composite binary image 3A × 3A × 3A by angles multiple of 90 ° around the axes Ox, Oy, Oz are performed by sequential execution of the commands P1X, P1Y, P1Z, P2Y. Rotations by angles not multiple of 90 ° are generally performed only on the contents of the inner cube (3 /

) A × (3 /

) A × (3 /

) A of the image 3A × 3A × 3A (FIG. 16-a), first the internal cube is expanded, then the individual fragments A / A are rotated

) × (A /

) × (A /

) (Fig. 16-6), and then the rotated fragments are stitched into a single three-dimensional image (Fig. 16-c).

)×(3

) включает в себя (фиг.17,18): 1) расшивку изображения (фиг.17-в); 2) поворот центрального содержимого фрагментов А×А расшитого изображения (фиг.18-а); 3) сшивание повернутых фрагментов в единое изображение (фиг.18-а). Принцип расшивки, поворота фрагментов расшитого изображения и последующего сшивания повернутых фрагментов в единое изображение дан в описании прототипа.Rotate a composite binary flat image (3

) × (3

) includes (Fig. 17,18): 1) image alignment (Fig. 17-c); 2) rotation of the central content of fragments A × A of the embroidered image (Fig. 18-a); 3) stitching rotated fragments into a single image (Fig.18-a). The principle of expanding, rotating fragments of the embroidered image and subsequent stitching of the rotated fragments into a single image is given in the description of the prototype.

)×(m

) состоит из:Compression of a composite binary flat image (m

) × (m

) consists of:

(аппаратным или программным способом);1) fragment compression

(hardware or software);

в единое изображение (m

)×(m

). На фиг.19 (д) изображен результат центрального сжатия отдельных фрагментов А×А бинарного изображения, представленного на фиг.17(а). Здесь моделирование центрального сжатия каждого исходного фрагмента А×А (фиг.19-а) относительно центра G этого фрагмента (фиг.19-6) совмещено с моделированием параллельного переноса центра сжатого фрагмента из точки G в точку W (фиг.19 - в, г). На фиг.19 (е) показан окончательный результат сжатия составного изображения после сшивания отдельных сжатых фрагментов А×А в единое составное изображение.2) stitching compressed fragments

into a single image (m

) × (m

) Fig. 19 (e) shows the result of central compression of individual fragments A × A of the binary image shown in Fig. 17 (a). Here, the simulation of the central compression of each source fragment A × A (Fig. 19-a) relative to the center G of this fragment (Fig. 19-6) is combined with the simulation of parallel transfer of the center of the compressed fragment from point G to point W (Fig. 19 - c, d). On Fig (e) shows the final result of compression of the composite image after stitching individual compressed fragments A × A into a single composite image.

Before processing them, the grayscale composite images are placed in the memory 51 of the matrix 32. In this case, the binary brightness code of one pixel is located in the memory 51 of the processor 33, which in the A × A × A matrix corresponds to this pixel in such a way that each bit of this brightness code is located at its address, i.e., the bits of brightness codes of all pixels of the fragment A × A × A are located in the memory 51 at the same address. The numerical processing of the brightness codes is carried out simultaneously in all processors 33 sequentially, bit by bit (using the INE and CM2 commands, which form a functionally complete Boolean basis). The transmission of brightness codes between neighboring pixels inside the matrix 19 for the implementation of numerical procedures related to filtering, smoothing images, contouring and highlighting surfaces on images is carried out using the above-described single-step shifts and rotations of 90 °.

We will explain the general principle of constructing three-dimensional models of objects using their flat stereo images using the claimed device as an example of constructing a three-dimensional model of a curved black segment from its two flat images obtained by photographing this segment on a white background in two directions that differ by an angle φ (Fig. 20) . Let the flat binary image in FIG. 20 (a) be the filtered image of the curved line segment obtained by the node 32, and the flat binary image in FIG. 20 (b) be the filtered image of the same curved section, but obtained by the node 31. We synthesize from each the specified flat image two three-dimensional image as follows. We compress both flat images to a resolution of mAx mA, place a compressed flat image on the edge of the mA × mA of the composite cube mA × mA × mA perpendicular to Oh (Fig.20 - c, d). Then, sequentially performing mA once a one-step shift in the direction Ox and gluing together the initial and shifted images, we obtain a binary model of the surface area (Fig.20 - d, f). Each photo will have its own surface. We turn one surface relative to another by an angle φ (Fig.20 - g) and perform the set-theoretic operation “intersection” on them. The result of the operation will be the desired three-dimensional pixel model of the curved segment.

A variant of the device, the dimensions of which allow it to be used as an on-board computer in the recognition and orientation system of an autonomous robot, is shown in FIG. 2. BOCHVI of this device includes: a 9 × 9 × 9 processor matrix (A = 9); 729-input combiner, 9-bit KZBI code generator, rotation units, compression units, buffer memory, image memory, display unit and photo input unit. BU made in the form of a single board. The capacity of the local memory of each PE matrix is 512 bits. The output of the synthesized images is carried out on a monitor screen, the input of photo images is carried out using two lenses connected to BOCHVI with flexible fiber optic cables.

To reduce the dimensions of the device and increase its reliability, 6 types of specialized digital circuits can be used as the main element base of the BOCHVI (we will conditionally designate them: BIS24A, BIS24V, BIS24S, BIS24V, BISSS, BISP).

Chips BIS24A, BIS24 V, BIS24S, BIS240 are designed to build a processor matrix, the first steps of the node for determining the volume and shaper KZBI. These microcircuits are analogs of the BIS24 crystal, have the same functional purpose and composition, and differ only in the location of the external terminals. The use of several types of crystals instead of one type of crystal BIS24 allows you to increase the clock frequency of the control due to the high density of installation. Each of these chips contains:

- 24 processor elements 33, forming together a complete closed-loop system ZPS-24;

- combination combiner with 7-bit output;

- 6 shapers code fill layer;

- sum code converter.

The circuit diagram of the BIS24A, BIS24V, BIS24S, BIS240 microcircuits is shown in Fig. 21, their cases and pinouts are shown in Fig. 22. The designation of the findings and their functional purpose are given in table.2. Chips BIS24A, BIS24 V, BIS24S, BIS240 allow you to implement all types of ZPS processor matrix.

table 2 Pin designation Appointment A0 ... A8 Address (ADR0 ... ADR8) of the local memory of processors П0 ... П23 ID4 ... ID11 Data inputs (iD4 ... iD11) of processors P4 ... P11 OD4 ... OD11 The outputs of these processors P4 ... P11 id0 ... id3, id12 ... id23 Data inputs (iD0 ... iD3, iD12 ... iD23) of processors П0 ... П13, П12 ... П23 od0 ... od3, od12 ... id23 Data outputs (oD0 ... oD3, oD12 ... oD23) of processors П0 ... П13, П12 ... П23 s10 ... s15 The outputs (SL0 ... SL5) of the shaper 6-bit code KZBI chips CWR1, CWR2, CWR3 Managing write to process registers П0 ... П23 Wr Management of recording in the local memory of processors П0 ... П23 ism0 ... ism6 Inputs (iS0 ... iS6) of the second stage of the adder osm0 ... osm6 Outputs (oS0 ... oS6) of the second stage of the adder INS0, INS1, INS2 Microoperation code address PR Controlling the Sum Code Converter (PR) rsrv Reserve

Switching BIS24 to ZPS24 mode is done by disabling its sum code converter (PR = 0).

To switch the BIS24 to ZPS6 mode, it is necessary to set PR = 0 and electrically connect the external inputs (iD) of the following PE microcircuits to each other:

1) P0, P1, P2, P3; 2) P4, P5, P6, P7; 3) P8, P9, P10, P11; 4) P12, P13, P14, P15;

5) P16, P17, P18, P19; 6) P20, P21, P22, P23.

Log.0 is set on the external inputs of the iS0-iS6 adder, the sum code is removed only from the outputs oS1, oS2, oS3 of the adder of the microcircuit ((24/4) ₁₀ = (110) ₂ ).

To switch BIS24 to ZPS8 mode, it is necessary to set PR = 1 and electrically connect the external inputs (iD) of the following PE microcircuits:

1) P0, P9, P23; 2) P1, P5, P22; 3) P2, P6, P13; 4) P3, P10, P14; 5) P4, P17, P21;

6) P7, P12, P18; 7) P8, P16, P20; 8) P11, P15, P19.

A log.0 is set at the inputs iS0-iS6 of the adder, the sum code is removed from the outputs oS0-iS3 of the adder of the microcircuit.

In ZPS1 mode, the BIS24 chip is switched by: 1) connecting all 24 of its iD information inputs; 2) at the external inputs of the adder, log 0 is set, the sum code is removed from the 3rd or 4th output of the adder of the microcircuit ((24) ₁₀ = (1100) ₂ ).

The BISSS chip is designed to build shear nodes, compression nodes, buffer memory, and the 1st image memory bank. The circuit diagram of the microcircuit is shown in Fig. 23 and consists of 4 identical single-bit parts, with one DI input and with one DO output each. In BOCHVI, each i-th DI input of the BISSS chip is connected to the same output of the A × A × A matrix, and each i-th output DO is connected to the opposite (in the Ox direction) input of the A × A × A matrix.

BISP is designed to build a rotation node and a 2nd image memory bank. The circuit diagram of the microcircuit is shown in Fig. 24 and consists of 4 identical single-bit parts, with one DI input and with one DO output each. In BOCHVI, each i-th DI input of the BISSS chip is connected to the same output of the A × A × A matrix, and each i-th DO output is connected to the opposite (in the direction of Ox) input of the A × A × A matrix.

The bearing-connecting structure of the BOCHVI is made according to the scheme of the electronic block described in [4], which significantly reduces the dimensions of the device, reduces the length of wire connections, increases the clock frequency of control, and ensures maintainability of the device. Structurally, the BOCHVI consists of a set of flat mechanically rigid boards having the same dimensions and interconnected by special detachable contact connectors, evenly spaced along the entire plane of the boards (Fig. 2, 25-a). The width and height of the BOCHI are determined by the overall dimensions of the largest board containing inside itself the PE of the outer shell of the matrix 9 × 9 × 9. The smallest dimensions of the BOCHVI are achieved if microcircuits are placed on both sides of each board. An embodiment of the wiring diagram of a 5-layer board containing PE immediately 2 cubic shells (9 × 9 × 9, 7 × 7 × 7) of a 9 × 9 × 9 matrix (cubic shell on each side of the board) is shown in Fig.25 (b) On Fig presents a drawing of the printed conductors of the upper layer of a fragment of this board (with microcircuits) containing the body of the cube shell 9 × 9 × 9 matrix. The overall dimensions of the entire BOCHVI board do not exceed 180 mm × 220 mm. The length of the BOCHVI is determined by the total number of docked boards (figure 2). The entire processor matrix, together with a 729-input adder, a full 9-bit KZBI driver, and a set of matrix control signal amplifiers, occupy from two to three boards. Buffer memory, rotation and compression nodes, 2 banks of image memory occupy two more boards. Thus, the minimum necessary set of BOCHVI consists of 4-5 boards. The composition of the BOCHI can be expanded by connecting additional boards (for example, boards of the 3rd, 4th bank of image memory, boards of high-speed input-output images, etc.) to the 81-bit data bus.

Thus, the dimensions of the BOHVI allow you to use the considered version of the claimed device as an on-board computer and to evaluate the possible clock frequency of the control of the BOHVI about 200-300 MHz. At this frequency, only formal image processing performance reaches 150-200 billion operations per second. Given that the device operates at all stages of image processing (from inputting source images, making decisions to synthesizing output images) exclusively with pixel models of objects (i.e., there is no need to change the method of geometric modeling, for example, in the transition from pixel modeling to modeling by polyhedra and vice versa), problem-solving algorithms are more compact and much shorter than traditional numerical processing algorithms, volume (area) calculation operations, the formation of KZBI performed simultaneously with other processing operations and have a high degree of parallelization, independent of the geometric complexity of the processed objects, the gain in image processing speed will be significantly higher than the formal productivity mentioned. The device allows you to quickly perform preprocessing of source images, quickly synthesize complex three-dimensional standards of objects, and quickly compare the analyzed objects with these standards.

Thus, in comparison with the prototype of the claimed device can improve the speed and accuracy of image processing. The speed and small dimensions of the device make it possible to create inexpensive sensible robots with an extremely high degree of autonomy on its basis, which, in turn, will automate spheres of human activity that are currently not subject to automation.

INFORMATION SOURCES

1. Auth. USSR certificate No. 1456965.

2. Auth. USSR certificate No. 1612307.

3. Auth. USSR certificate No. 1817109.

4. Patent for the invention No. 2192716.

5. Ugryumov EP Digital circuitry. BHV-Petersburg, 2001.

6. Auth. USSR certificate No. 1817108.

Claims (1)

A device for parallel processing of two-dimensional and three-dimensional images, comprising a processor matrix, a control unit, a rotation node matrix, a compression node matrix, a memory node matrix, a switching unit, a volume determination unit and a fill code generator, each matrix processor contains local memory, a local memory input switch and operand registers, information outputs of a processor matrix are connected to information inputs of matrices of rotation nodes, compression nodes, memory nodes and a control unit, information inputs odes of the processor matrix are connected through the switching unit to the information outputs of the matrix of rotation nodes, compression nodes and a control unit, the control input groups of which are connected to the corresponding control inputs of the processor matrix, rotation nodes, compression, memory nodes, the information inputs of the volume determination node and the fill code generator are connected with the corresponding outputs of the matrix processors, and their information outputs are connected to the corresponding information inputs of the control unit, characterized in then an additional information input is connected to the input switch of the local memory of each matrix processor, connected to the information output of the register of this processor, an additional register is entered into each matrix processor, the information input of which is connected to the information output of the local memory of this processor, the control input is connected to the additional control output control unit, and the information output is connected to the corresponding input of the volume determination unit and to the corresponding input of the forms of the fill code driver, the volume determination unit is made in the form of a digital combinational adder, the fill code generator is made in the form of several unrelated multi-input OR circuits, the outputs of which are connected to additionally entered information inputs of the control unit, a matrix of buffer memory nodes is introduced, each node of which consists of of two single-bit registers, the information input of the first register is connected to the corresponding output of the processor matrix, the control input is connected to the control input By recording local memory, the information output is connected to the information input of the second single-bit register, the control input of which is connected to the control input of the operand register of the matrix processor, and the information output is connected to the corresponding inputs of the switching unit, the information input and information output of each memory node is connected to the corresponding matrix input processors, which is both an information input and an information output of the device; additional outputs of the control unit are introduced, connected to the additionally entered inputs of the switching unit, the additional outputs of which are connected to the control inputs by connecting the information outputs of the sensors to the information inputs of the processor matrix, for the k-th signal of the matrix control, the set of matrix elements is divided into disjoint subsets, for each subset the amplifier of the first stage, the output of which is connected to the k-th control input of each element of this subset, the whole set of the mth stage cascade is divided into disjoint subsets, for each subset of amplifiers of the mth stage of the kth matrix control signal, in addition to the last stage, an amplifier of the (m + 1) th stage is connected, the output of which is connected to the input of each amplifier of the mth the cascade of its subset, the inputs of the amplifiers of the last stage are connected to the output of the control unit corresponding to the k-th signal of the matrix control.

Images