RU22237U1 - VORTEX TYPE FLOW METER SENSOR CORRELATION PROCESSING DEVICE - Google Patents

Abstract

A device for correlating a signal of a vortex-type flowmeter sensor, comprising a preamplifier, a signal conditioner and a phase-locked loop, characterized in that it is equipped with an autocorrelator assembly, a locking assembly, a normalizing divider and a matching output stage, while the phase locked loop consists of a phase a type I detector, an integrator with two inputs, a voltage controlled oscillator, and a binary divider, the autocorrelator assembly consists of a shear re a histra, a multi-input multiplier, a resistor analog combiner, a low-pass filter and an amplitude discriminator, and the blocking unit contains an input signal determiner, a multiplier, a low-pass filter and a comparator, while the input of the device as a whole is the preamplifier input, the output of which is connected to the input of a signal conditioner , the output of the signal conditioner is connected to one of the two inputs of the phase detector of the automatic frequency control unit, with the information input of the shift register common to by the multi-input multiplier of the autocorrelator node and the information input of the signal value determiner of the blocking node, the output of the phase detector is connected to one of the two inputs of the integrator, and the output of this integrator is connected to the input of the voltage-controlled generator, the output of which is connected to the input of the binary divider, with the clock input of the shift register the autocorrelation unit and through the normalizing divider - with one of the two inputs of the matching output stage, one of the two outputs of the binary divider is connected to the other input

Description

DEVICE CORRELATION PROCESSING DEVICE SENSOR FOR VORTEX TIN FLOW METER.

The useful model relates to devices for converting the output signal of a vortex tin flow sensor into a high-quality information signal for a flowmeter measuring device with a multi-factor negative effect on the sensor in real operating conditions.

A device 1 is known, consisting of an amplifier, an adjustable filter, a Schmitt trigger with a variable width of the hysteresis loop, a phase-locked loop (PANF) with a phase II phase detector based on triggers with input control logic, for example, as in the CD4046B chip and control unit. The device provides the selection of the main harmonic of the sensor signal of the vortex type flowmeter by adaptive filtering of the sensor signal and phase automatic adjustment of the frequency at the output of the device to the frequency of the main harmonic of this signal. The frequency properties of the filter and the width of the Schmitt trigger hysteresis loop are adjusted depending on the amplitude of the signal generated by the low-frequency (LF) filter at the output of the phase detector, while switching resistors are used as control elements of the above nodes.

M.K.L. GOlFl / 32

However, the known device is not able to deplete a sufficient wall of noise suppression in the case of high noise of the signal for the following reasons:

- the regulation does not take into account the dependence of the amplitude of the input signal on the density of the medium being measured. This means that when the density of the measured medium changes, the amplitude-frequency characteristics of the circuit will not be optimal for the input signal. Therefore, the signal-to-noise ratio, accuracy and stability of the flowmeter are reduced;

- the use of passive filters does not make it possible to sufficiently get rid of short-term malfunctions of the vortex sequence such as “excess pulses that can be caused by inhomogeneity of the medium being measured, external influences on the sensor, and other reasons. As a result, the accuracy and stability of the flowmeter are also reduced;

The phase II type II detector included in the PLL assembly has low noise immunity, which limits the range of measured flow rates and leads to improper operation of the device as a whole, even with a small level of interference at the detector input.

The closest technical solution is the prototype of the claimed object, in terms of processing the input signal, the set of essential features is device 2. The device consists of a preliminary amplifier, a signal conditioner, a circuit that determines the short-term disappearance of a signal, a key, and a PLL that contains a type II phase detector, low-pass filter, and a voltage-controlled generator (VCO). The device provides the determination of the fundamental harmonic of the signal, the sensor of the vortex type flowmeter, the phase automatic frequency adjustment and the device output

to the frequency of this signal.

In the known device for restoring a vortex signal at the output of the device, for short-term disappearances of the input frequency, a detector for the disappearance of the input signal that controls the electronic key is used. The key opens the connection between the output of the phase detector and the input of the LF filter, thereby preserving the voltage at the output of the filter and, consequently, the frequency at the output of the device close to the frequency of the signal until it disappears.

But this device is also not without drawbacks, the main of which include the following:

- although the application of this circuit allows, to some extent, eliminating interference such as the disappearance of a signal, a noise such as “excess pulses” remains unavoidable, which leads to unreliable readings of the device;

- the phase II type detector used in the PLL node has low noise immunity and, as a result, the device has a limited dynamic range, and the correct operation of the system and the PLL node and the device as a whole, without sufficient filtering of the input signal, even with a small noise level, looks problematic.

The required technical result of the claimed device is to minimize the above-mentioned disadvantages of the known device and to obtain the most reliable information signal for the measuring device of the flow meter.

The required technical result is ensured by the fact that the known device comprising a preamplifier, a signal conditioner and a PLL assembly is provided with an autocorrelator assembly, a locking assembly, a normalizing divider and a matching output stage, while the assembly

The PLL consists of a type I phase detector (an element of "reliable OR"), an integrator, a voltage controlled oscillator and a binary divider, the autocorrelator assembly consists of a shift register, a multi-input multiplier on the elements of an exclusive OR, a resistor analog adder, a low-pass filter, and an amplitude discriminator, and blocking unit contains a determinant of the value of the input signal, a multiplier on the element “exclusive OR, low-pass filter and a comparator, while the input of the device as a whole is the input of the preamplifier, the output to which is connected to the input of the signal conditioner, the output of the signal conditioner is connected to one of the two inputs of the phase detector of the automatic frequency control unit, with the information input of the shift register, the common input of the multi-input multiplier of the autocorrelator unit and the information input of the determinant of the signal value of the blocking unit, the output of the phase detector is connected to one from two inputs of the integrator, and the output of the integrator is connected to the input of a voltage-controlled generator, the output of which is connected to the input of binary d divider, with a clock input of the shift register of the autocorrelator node and - through a normalizing divider - with one of the two inputs of the matching output stage, one of the two outputs of the binary divider is connected to the other input of the phase detector and one of the two inputs of the multiplier of the lock node, the other output of the binary divider, which is the previous discharge, connected to the clock input of the determinant of the signal value of the blocking node, the outputs of the shift register are connected to the inputs of the multi-input multiplier, the outputs of which are connected to the odes of the resistor analog adder whose output - through the low-pass filter and the amplitude discriminator - is connected to another integrator input, the output of the input signal value determiner is connected to

.

{the other input of the multiplier whose output is through a low filter

frequency and the comparator is connected to another input of the matching output stage, while the output of the matching output stage is the output of the device as a whole.

Note that from the well-known sources of information (including patent), devices that are identical to the proposed and / or devices with a set of essential features (including distinctive) that are equivalent to the set of features of the proposed technical solution and exhibit the same new properties are not identified, allowing to achieve the required technical result during implementation. This allows us to argue that the proposed technical solution is new, non-obvious, has "significant differences (etc.), that is, satisfies the" criteria of a utility model.

The graphic materials presented:

FIG. 1 is a functional diagram of the inventive device;

FIG. 2 is a functional diagram of the PLL node 3 of FIG. 1;

FIG. 3 is a functional diagram of an autocorrelator assembly 4 of FIG. 1.;

FIG. 4 is a functional diagram of the locking unit 5 of FIG. 1;

FIG. 5 is a graph of the amplitude of the signal 54 as a function of the ratio of the fundamental frequency of the signal 24 (Pbx) and the clock frequency (FT) of signal 37;

FIG. 6 the dependence of the amplitude of the voltage at the output of the autocorrelator 4 on the ratio of the frequencies FBX and FT;

FIG. 7 time relationships between signals 24, 40.41 and 50. The device (see Fig. 1) consists of a preamplifier 1, a shaper 2

of the signal, PLL node 3, autocorrelator node 4, blocking node 5, normalizing divider 6, and matching output stage 7. In turn, the PLL node (see Fig. 2) consists of a type I phase detector

5

8, integrator 9, voltage controlled oscillator 10 and binary divider 11. The autocorrelator assembly (see Fig. 3) consists of a shift register 12, a multi-input non-multiplier 13, exclusive elements I.I., a resistor analog adder 14, a filter 15 KGH and amplitude discriminator 16. The locking unit (see Fig. 4) consists of a determinant 17 of the input signal value, a multiplier 18 on the exclusive OR element, a low-pass filter 19 and a comparator 20. The input of the device (see Fig. 1) is the preamplifier input 21, output 22 of which connected to the entrance 23 fo tors, signal. The output of the signal shaper is connected to one 25 of the two 25 and 26 inputs of the phase detector 8 of the automatic frequency control unit, with the information input 27 of the shift register 12, the common input 28 of the multi-input multiplier 13 of the autocorrelator unit and the information input 29 of the determiner 17 of the input value of the blocking unit. The output 30 of the phase detector is connected to one 31 of the two inputs 31 and 32 of the integrator 9, and the output 33 of this integrator is connected to the input 34 of the voltage controlled generator 10. The output 35 of this generator is connected to the input 36 of the binary divider 11, with the clock input 37 of the shift register 12 of the autocorrelator assembly, and - through the normalizing divider 6 - with one 38 of the two 38 and 39 inputs of the matching output stage 7. One 40 of the two 40 and 41 the outputs of the binary divider is connected to the other 26 input of the phase detector and one 42 of the two 42 and 43 inputs of the multiplier 18 of the blocking node, and the other 41 output of the binary divider, which is the previous bit, is connected to the clock input 44 of the determiner 17 of the input value of the blocking node. The outputs 45 of the shift register are connected to the inputs 46 of the multi-input multiplier. The outputs 47 of the multi-input multiplier are connected to the inputs 48 of the resistor analog totalizer, the output 49 of which, through the low-pass filter 15 and the amplitude discriminator 16, is connected to the other 32 input of the integrator 9. The output 50 of the input signal value determiner is connected to the other 43 input of the multiplier 18, the output 51, which, through a low-pass filter 19 and a comparator 20, is connected to the other 39 input of the matching output stage, while the output 52 of the matching output stage is the output of the device as a whole.

In the graphic materials in figures 1 ... 4 (to explain the principle of operation of the device), additional positions denote: 53 -input filter 15 IC filter node 4 of the autocorrelator; 54 - filter output 15 low frequency node

4 autocorrelator; 55 - input amplitude discriminator 16 node 4 of the autocorrelator; 56 - the output of the amplitude discriminator 16 node 4 of the autocorrelator; 57-input filter 19 LF node 5 lock; 58 filter output 19 LF block 5 lock; 59 - input of the comparator 20 nodes

5 locks; 60 - the output of the comparator 20 node 5 lock; 61 - input normalizing divider 6; 62 - output normalizing divider 6.

The device operates as follows. The vortex flowmeter sensor shown in FIG. 1 at the top and is not indicated by a separate position, generates an electrical analog signal containing a useful (informational) component, the frequency of which is a function of the flow rate of the measured medium, and a noise component, the character of which is determined by the heterogeneity of the measured medium, the roughness of the inner surface of the pipeline, the pressure pulsations of the measured medium, external influences on the pipeline, etc. The signal is input to the device.

Before setting out the principle of operation of the device as a whole, we consider the characteristics and principle of operation of individual nodes of the device, while, for simplicity, the signal numbering is taken according to the positions of the outputs of the nodes with which they are formed (according to figures 1 ... 4), except

signal 21, the numbering of which is taken at the position of the input of the preamplifier 1.

Preamplifier 1 (see Fig. 1) is made according to the well-known scheme of an alternating current amplifier (see Gutnikov V. S., "Integrated Electronics in Measuring Devices, Leningrad," Energoatomizdat, 1988, p. 37) and can be implemented on the basis of charge amplifiers, and potential amplifiers, depending on the type of sensitive elements used in the flow sensor and the method of signal collection. Shaper 2 signal (see figure 1) is also made according to the well-known Schmitt trigger scheme. (see P. Horowitz, W. Hill, "The Art of Circuit Engineering Volume 1, Moscow," Mir, 1983, p. 215)

Node 3 of the PLL (see Fig. 1) is also known and executed according to the scheme (see P. Horowitz, W. Hill, “The Art of Circuit Engineering Volume 2, Moscow,“ Mir, 1983, p. 80) with a phase detector of type I and with intermediate frequency multiplication. The functional diagram of the PLL node is shown in FIG. 2. However, it should be noted that instead of the low-pass filter in this circuit, a two-input integrator 9 is used, made, for example, according to the well-known circuit (see Gutnikov V. S., “Integrated electronics in measuring devices, Leningrad,“ Energoatomizdat, 1988, p. 98 ) at the same time, the presence of the second input allows you to perform additional adjustment in the PLL loop. In addition, the use of an integrator in the feedback circuit makes the PLL system astatic, which allows maintaining, in steady state, a constant phase shift between the signals at the inputs of the phase detector 8 over the entire operating range.

The autocorrelator unit 4 is made according to the well-known multichannel correlator scheme (see Galushkin A. I., Zotov Yu. Ya., Shikunov Yu. A. “Operational Processing of Experimental Information Moscow,

“Energy, 1972, p. 158) and performs the function in this device

frequency discriminator.

Since the processed input signal takes only two values with the levels “log.O and“ LOG.1, a simple shift register 12 can be used as the delay line of the input signal FBX, and two-input elements “exclusive OR” as a multi-input signal multiplier 13. The first inputs of these elements are combined into a common input 28 and they are fed a processed input signal 24 (FBX). And the other 46 inputs of the multi-input multiplier are delayed, in the shift register 12 for a time multiple of the clock frequency FT (signal 35), signals 45 from the corresponding outputs of the shift register. The resulting correlation signals 47 from the outputs of the multi-input multiplier 13 are added using a resistor analog adder 14 and averaged over time using a low-pass filter 15. Note that with a change in the FT clock frequency, the time shift between the input signals delayed in the register (signals 45) also changes in fractions of the frequency period of the input signal FBX, in addition, at FT frequencies comparable to the frequency of the input signal, the input signal is discretized in time. As a result, the signal 54 (correlation function) at the output of the low-pass filter 15 with the appropriate choice of the parameters of the resistor analog adder 14 and depending on the ratio of the input FBX and the clock frequency FT takes the form (see Fig. 5). The local maxima in this graph are due to the maxima of the correlation function with time delays in the shift register 12 times the period of the main harmonic of the input signal FBX. It should be noted that this type of correlation function is preserved even with a large level of interference in the input signal FBX.

9 amplitude discriminator 16 can be performed, for example,

but a circuit with two comparators having different thresholds of operation and has an output amplitude characteristic depending on the input voltage, such as shown in figure 6. To obtain a “unambiguous relationship between the ratio of the frequencies at the inputs 27 and 37 of the correlator and the state of its output 56 deadband “A-B (see Fig. 5, 6) of the amplitude discriminator 16 is selected above the local maxima in the graph of the correlation function.

The functional diagram of the output signal blocking unit 5 is shown in Figure 4. Using the determinant 17 of the input signal value, which is a D-trigger with edge recording, a signal 50 is generated. In this case, the processed input signal 24 is supplied to the trigger information input 29, and to the input 44, enter the signal 41 generated by the binary divider And, while the trigger on the inverting output generates a signal 50 in accordance with the values of the input signal 24 at time instants; they coincide with the trailing edge of the signal 41 (see Fig. 7). Note that the signals 41 and 40 are taken from two consecutive bits of the binary divider 11.

Node 5 lock determines the average value of the correlation between the signals 40 and 50 fed to the input of the multiplier 18 made on the element exclusive OR. The output signal 51c of the multiplier 18 is averaged using a low-pass filter 19 and fed to the input 59 of the comparator 20, made, for example, according to the Schmitt trigger circuit, which compares this value with the specified settings (thresholds) which are selected depending on the level of noise in the input signal and, according to the comparison results, generates a blocking signal 60.

10

by the division factor and normalizes the “signal impulse prices 62 according to the formula:

F62, F35 - signal frequencies 62 and 35, respectively; CRC, is the conversion coefficient determined during calibration of the flowmeter.

The output matching stage 7 is intended for matching the output signal of the device with a secondary device (indication means). The best option for the output stage is an optocoupler that can match the signal with almost any indication.

The operation of the device as a whole is based on the principle of correlation signal processing when using a multiplier (type I phase detector) as a phase detector 8 in the PLL node 3, while the device performs the following functions: input of a flow sensor signal;

limiting the amplitude of the input signal to match the logic levels;

determination of the frequency of the fundamental harmonic of the input signal; blocking the output signal of the device when it is impossible to determine the frequency of the fundamental harmonic in the input signal; rationing of the “pulse price of the output signal; matching the output signal of the device with the measuring device of the flow meter;

sinusoid, may have short gaps, spikes, phase flips, a significant noise component. The fundamental frequency of the signal 22 is uniquely related to the flow rate of the medium being measured. Then this signal is generated using the signal shaper 2 for matching with logical levels. A characteristic form of the signal, which is used for further processing, is shown in figure 7, signal 24.

From the output of the former 2, the signal 24 is fed to the input 25 of the phase detector 8 of the node 3 of the PLL. The PLL operation is well known and described in many sources, for example (see P. Horowitz, W. Hill, “The Art of Circuit Engineering Volume 2, Moscow,“ Mir, 1983, p. 78), so we only note that when the PLL node 3 is in a state of synchronization with the input signal, the frequency of the signal 35, at the output of the voltage controlled oscillator 10, is directly proportional to the fundamental frequency of the input signal 24, and the ratio of the frequencies FBX and FT is equal to:

N is the division coefficient of the binary divider 11;

FBX, is the fundamental frequency of the input signal 24;

FT is the frequency of the signal 35 at the output of the voltage controlled oscillator 10.

For simplicity, we will assume the level of “log. 1 equal to + U, level “log. About equal to -U, and the level corresponding to half the logical (0.5Unor.) Equal to OU.

Consider the operation of the PLL node 3 with an open feedback circuit between the output 40 of the binary divider and the input 26 of the phase detector. Let at the input 27 nodes of the autocorrelator and 25 nodes of the PLL

m F / F

-1- -TEX there is no input signal 24 with a frequency equal to FBX, and at the output of 35 nodes

PLL frequency RT

K - coefficient of disproportionality with dimension Hz / V;

UH is the voltage at the output of the integrator 9;

FO is the initial frequency of the voltage controlled oscillator 10.

In this case, the average level of the constant component of the signal at the output of the 30 phase detector is close to the OU level, which is characteristic of the vortex flowmeter signal, and does not affect the operation of the integrator. Then, if the ratio of the frequencies FBX and FT lies in the range from O to “A (see Fig. 5), the output 56 of the autocorrelator assembly contains + U voltage (see Fig. 6). In this case, the voltage at the output of the integrator 33 decreases, which leads to a decrease in the frequency FT and, consequently, to an increase in the ratio FBX / FT until the ratio between the frequencies is reached; its point “A in FIG. 5. At this point, the voltage level at the input 32 of the integrator becomes equal to OU and the voltage at its output is fixed. When the frequency ratios in the area from point "B in figure 5 and above, the opposite picture is observed. Thus, at the output 35 of the PLL node, the frequency corresponding to the input is maintained, and the ratio of the frequencies FBX and FT does not go beyond the values corresponding to section “AB in FIG. 5. The width of the section "AB is determined by the levels of the amplitude discriminator, and it is selected such that the frequency at the output 40 of the PLL, with the appropriate choice of the division coefficient N, binary divider 11, always lies within the capture range of the PLL. With a closed feedback loop, the picture will be similar to that described above except that when the frequencies of the input signal and the signal from the output of 40 nodes

.

thirteen

F, K UH + FO, PLL become close, the phase effect begins to affect

detector. As a result, at the output 40 of the PLL node, a frequency equal to the fundamental frequency of the input signal 24 is set, and the FBX / FT ratio becomes equal to the division coefficient N, in the category corresponding to output 40, of the binary divider, i.e. the PLL goes into synchronization state. In this case, the voltage levels OU are set at both inputs of the integrator, and the phase shift between signals 24 and 40 at the inputs 25 and 26 of the phase detector is 90.

It should be noted that when the PLL system with a phase I phase detector is in a state of synchronization with the input signal, it is close to the correlation receiver (see E. I. Manaev, “Fundamentals of Radio Electronics, Moscow,“ Radio and Communication, 1985, p. . 479). In turn, the correlation receiver is equivalent to a receiver with a matched filter, which follows from the equivalence of optimal filtering and the calculation of the cross-correlation function. This explains the high noise immunity of the claimed device and the high reliability of determining the frequency of the fundamental harmonic of the input signal 24.

The operation of the blocking unit 5 is reduced to determining the moments when the PLL node is in a synchronized state, i.e. moments when a reliable signal is present at the output of the 35 PLL node. This happens as follows, using the determinant of the values of the input signal 17, a signal 50 is generated in accordance with the values of the input signal 24 at times tl and t2 (see Fig. 7). Moreover, if the PLL node is in a state of synchronization with the input signal, then, as the phase shift between signals 24 and 40 was noted, it is close to 90, and the times tl, t2 correspond to the maxima of the main harmonic of the input signal. In this case, the probability of that.

lc / iJK9O

14 that signal 24 takes a true value of "O or" 1 is maximum.

Thus, the signal 40 coincides with the signal 50, but is shifted relative to it by 180 (see Fig. 7) and it is believed that the signals 40 and 50 are completely correlated. In this case, at the output 51 of the multiplier 18 and at the output 60 of the blocking unit there is a level of "log. About which allows the passage of the signal 62 through the output matching stage 7.

With a large level of interference in the input signal, the operation of the determinant 17 by interference is possible, however, this does not lead to a significant change in the voltage level at the output of the 19 LF filter since the correlation value between signals 50 and 40 is determined in each period of the input signal. In this case, the output of the blocking node 60 is also “log. O and the passage of the signal 62 through the output stage 7 is allowed.

When the correlation level between signals 50 and 40 decreases to a certain value determined by the threshold of the comparator 20, the signal 60 takes the value of "log.1. This means that the signal 62 is not reliable and the passage of the signal 62 through the output is consistent; its cascade 7 is blocked.

In the absence of an input signal 24, a signal 40 corresponding to the initial frequency FO of the voltage controlled oscillator 10 is applied to the correlator input 42. In this case, the voltage at the output 58 of the inverter filter 19 also exceeds the response threshold of the comparator 20, i.e. the signal 60 has a value of "log.1 and the frequency signal at the output 52 of the matching stage 7 is missing.

The pore divider 6 performs the normalization of the "pulse price of the signal 62 according to the formula:

fifteen

.

16

F62, F35 - signal frequencies 62 and 35, respectively;

CRC, is the conversion coefficient determined by the calibration of the flowmeter.

The CRC coefficient defines "the steepness of the conversion and is selected so that" the price of the output pulse has a convenient value (for example, 0.1 l / imp, 1 l / imp, 10 l / imp, etc.).

The signal 62 through the output matching stage 7 (see Fig. 1) is supplied to the output of the device.

The setup of the device consists in setting the output characteristic of the autocorrelator assembly 4, in setting the limits for changing the output frequency of the voltage-controlled generator 10 in accordance with the frequency range of the input signal FBX and in setting the conversion coefficient Kpr by calibration on a standard flowmeter stand. The scatter of parameters (ratings) of the applied components does not affect the performance of the device as a whole.

The main advantages of the device in its use with a vortex flow sensor are:

a wide range of measured costs (up to 1: 1000) while maintaining measurement accuracy;

the ability to work when the density of the measured medium changes by 1000 or more times, i.e. the ability to work on liquid and gas without rebuilding the device;

the possibility of trouble-free operation with small non-linear sections of the pipeline before and after the flow sensor without installing a straightener;

the possibility of trouble-free operation in environments with a high content of heterogeneous inclusions;

the possibility of trouble-free operation on rapidly varying and pulsating flows without loss of measurement accuracy;

high degree of reliability of the output signal, i.e. if the determination of the flow rate of the measured medium is possible, then the output signal corresponds to reality. If the flow rate is below the measurement limit or the noise level is excessively high, there is no output signal. In other words, the device can be in two states: it either shows correctly or does not show at all.

Thus, the combination of essential features (including distinguishing ones) of the proposed device ensures the achievement of the required technical result, meets the criteria of the “utility model, and is subject to protection by the RF title document (patent) in accordance with the request of the applicant.

Sources of information taken into account when compiling a description of the claimed utility model:

1.CIIIA patent, M. Cl O01P1 / 32, 1981;

2.CIIIA patent, M. IOi G01Fl / 32, 1984, prototype.

Claims (1)

A device for correlating a signal of a vortex-type flowmeter sensor, comprising a preamplifier, a signal conditioner and a phase-locked loop, characterized in that it is equipped with an autocorrelator assembly, a locking assembly, a normalizing divider and a matching output stage, while the phase locked loop consists of a phase a type I detector, an integrator with two inputs, a voltage controlled oscillator, and a binary divider, the autocorrelator assembly consists of a shear re a histra, a multi-input multiplier, a resistor analog combiner, a low-pass filter and an amplitude discriminator, and the blocking unit contains a determinant of the input signal value, a multiplier, a low-pass filter and a comparator, while the input of the device as a whole is the preamplifier input, the output of which is connected to the input of the signal conditioner , the output of the signal conditioner is connected to one of the two inputs of the phase detector of the automatic frequency control unit, with the information input of the shift register common to by the multi-input multiplier of the autocorrelator node and the information input of the signal value determiner of the blocking node, the output of the phase detector is connected to one of the two inputs of the integrator, and the output of this integrator is connected to the input of the voltage-controlled generator, the output of which is connected to the input of the binary divider, with the clock input of the shift register the autocorrelator node and through the normalizing divider - with one of the two inputs of the matching output stage, one of the two outputs of the binary divider is connected to the other input the house of the phase detector and one of the two inputs of the multiplier of the blocking node, the other output of the binary divider, which is the previous bit, is connected to the clock input of the determinant of the signal value of the blocking node, the other output of the binary divider, which is the previous bit, is connected to the clock input of the determinant of the signal value of the blocking unit, the outputs of the shift register are connected to the inputs of the multi-input multiplier, the outputs of which are connected to the inputs of the resistor analog adder, the output of which through the filter is low frequency and amplitude discriminator is connected to another input of the integrator, the output of the input signal value determiner is connected to another input of the multiplier, the output of which is connected through the low-pass filter and the comparator to the other input of the matching output stage, while the output of the matching output stage is the output of the device as a whole.