RU2216033C2 - Computer - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: computer using data stream control for information processing has central processor unit incorporating program fragment processor for executing program segments, input-output selector switch, command loading switch, command memory, and data access unit depending for its operation on data stream computing principle. EFFECT: enhanced speed due to reduced capacity of associative memory. 2 cl, 15 dwg

Description

 The present invention relates to computing, in particular to computing devices in which data flow control is used to process information (especially for use in digital computing systems with high speed).

BACKGROUND OF THE INVENTION
An information processing apparatus in which a data stream is used to process information is described in US Pat. No. 4,675,806 to Uchida. Uchida describes a system in which the execution of commands is based on data availability and in which the data stream and the commands are shared, but the data is transmitted in accordance with the instructions and requirements of the commands. Such a device has a relatively low level of speed, which is common for other computing devices that use data flow control and direct addressing to RAM as a hardware for storing data during the calculation. Reduced performance occurs due to the complex organization of hardware for control tools and time spent in the process of dynamic memory allocation.

 Another known device for processing data described in the patent of the Russian Federation 2029359, in which the data stream is used to control the calculation process, contains a central processor, an input / output switch, a command loading switch, a memory for storing commands, a data access unit, and the first and second information outlets. In this device, the first control output of the central processor is connected to the first control input of the I / O switch, the first control input of which is connected to the first control input of the data access unit, the first information input of which is connected to the information output of the command download switch, the first control input of which is connected to the second control output of the central processor, the first and second information outputs of which are connected, respectively, with the first information input of the command load selector and the first information input of the I / O switch, the third information output of the processor is connected to the first information output of the computer, the null input of the data access unit is connected to the null output of the computer, and the information input of memory for storing commands and the information input of the command download switch are connected to the first information input of the computer.

 In this device, a data stream is used to control the calculation process, and associative memory (data access unit) is used to store data and calculation results. Associative memory simultaneously performs the function of hardware management tools. In accordance with this, performance is increased, since there is no loss of time on memory allocation processes.

 However, in this device, the device’s performance directly depends on the associative memory (in the data access unit) and is limited by the speed of data output from the associative memory (the number of operands ready to be executed per unit time N = 1 / Tam, where Tam = the operating time of the associative memory with moment of request for data output).

 The value of Tam directly depends on the amount of associative memory. Since the value of Tam, determined from the request time from the work program, increases as the size of associative memory increases, the performance of the device decreases as the size of associative memory increases.

 Thus, when processing large volumes of work programs, such a device cannot have a high level of performance.

SUMMARY OF THE INVENTION
The objective of the present invention is to increase performance by reducing the amount of associative memory while introducing at the same time local data processing that is consistent with the principles of von Neumann calculation, without compromising the general idea of controlling the flow of data of the calculation.

 An object of the present invention is to improve performance by introducing a fragment program into a processor data stream processing system, whereby fragment programs, which are programs that are better suited to be executed using von Neumann calculation principles, are sent to the fragment program to be executed on the processor.

 This problem is solved in a computer containing a central processor, an input-output switch, a command loading switch, a memory for storing commands, a data access unit, the first and second information outputs, resetting the input and the first and second information inputs. The first control output of the central processor is connected to the first control input of the I / O switch. The first control output of the I / O switch is connected to the first control input of the data access unit. The first information input of the data access unit is connected to the information output of the I / O switch. The memory input address for storing commands is connected to the information output of the command loading switch. The first control input of the command loading switch is connected to the second control output of the central processor. The first and second information outputs of the central processor are connected to the first information input of the command loading switch and to the first information input of the input-output switch, respectively. The third information output of the central processor is connected to the first information output of the computer. The nulling input of the data access unit is connected to the nulling input of the computer. The information input of the memory for storing commands and the second information input of the command loading switch are connected to the first information input of the computer. The fragment program processor is introduced. The first control output of the fragment program processor is connected to the second control input of the data access unit. The first control output of the data access unit is connected to the second control input of the I / O switch. The second control output of the I / O switch is connected to the first control input of the central processor and to the first control input of the program fragment processor. The second control output of the fragment program processor is connected to the third control input of the input-output switch. The second information input of the I / O switch is connected to the information output of the fragment program processor. The second control output of the data access unit is connected to the second control input of the central processor. The first information input of the central processor is connected to the information output of the memory for storing instructions. The control input of the memory for storing commands is connected to the control output of the command loading switch. The second control input of the command loading switch and the first information input of the fragment program processor are connected to the first information input of the computer. The control output of the memory for storing commands is connected to the third control input of the central processor. The third control output of the central processor is connected to the third control input of the data access unit. The second information input of the data access unit is connected to the second information input of the computer. The resetting input of the computer is connected to the second control input of the fragment program processor, to the fourth control input of the data access unit, to the fourth control input of the input-output switch and to the fourth control input of the central processor. The fourth control output of the central processor is connected to the fifth control input of the data access unit. The third information input of the data access unit is connected to the second information output of the central processor. The fifth control input of the central processor is connected to the third control output of the data access unit. The first information output of the data access unit is connected to the second information input of the central processor. The second information output of the data access unit is connected to the second information output of the computer. The third control input of the fragment program processor is connected to the fourth control output of the data access unit. The third information output of the data access unit is connected to the second information input of the fragment program processor. In addition, the fragment program processor comprises an execution unit, an output register unit, a load register unit, and an input register unit. The information output of the executive unit is connected to the information input of the output register block. The first control input of the output register block is connected to the first control input of the fragment program processor. The second control input of the fragment program processor is connected to the first control input of the executive unit, with the second control input of the output register block, with the first control input of the load register block and with the first control input of the input register block. The first control output of the input register block is connected to the first control output of the fragment program processor. The first information input of the fragment program processor is connected to the information input of the download register block. The information output of the download register block and the information output of the input register block are connected to the information input of the executive block. The second control input of the executive unit is connected to the first control output of the output register block, to the first control output of the load register block and to the second control output of the input register block. The third control output of the input register block and the second control output of the output register block are connected to the third control input of the executive unit. The first control output of the executive unit is connected to the second control input of the load register block, to the second control input of the input register block and to the third control input of the output register block. The third control output of the output register block is connected to the second control output of the fragment program processor. The second information input of the fragment program processor is connected to the information input of the input register block. The third control input of the input register block, the third control input of the load register block and the fourth control input of the output register block are connected to the second control output of the executive unit. The third control output of the executive unit is connected to the fourth control input of the input register block, to the fourth control input of the load register block and to the fifth control input of the output register block. The information output of the output register block is connected to the information output of the fragment program processor. The third control input of the fragment program processor is connected to the fifth control input of the input register block. The sixth control input of the input register block, the fifth control input of the load register block and the sixth control input of the output register block are connected to the fourth control output of the executive unit. The fifth control output of the executive unit is connected to the seventh control input of the output registers.

 The essence of the present invention is that the introduction of the processor program fragment and the organization of the corresponding connections provide increased computer speed during processing of the main programs by increasing the exchange rate of associative memory by reducing its working volume.

 To execute the entire program, the principle of controlling the flow of calculation data is used. Fragment processing, which has a local character of computation and little parallelism (for example, fragments in the form of trigonometric or other functions indirectly associated with similar fragments), is performed without the participation of associative memory.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a functional diagram of a system according to the present invention.

 Figure 2 - functional diagram of the Central processor.

 FIG. 3 is a functional diagram of a control device of a central processor.

 FIG. 4 is a functional block diagram of the input register of the central processor.

 FIG. 5 is a functional block diagram of the output register of the central processor.

 6 is a functional diagram of an I / O switch.

 7 is a functional diagram of a data access unit.

 Fig. 8 is a functional diagram of a buffer of a data access unit.

 FIG. 9 is a functional diagram of a control device of a buffer of a data access unit.

 Figure 10 - functional diagram of the processor program fragment.

 11 is a functional diagram of the Executive unit of the processor program fragment.

 FIG. 12 is a functional block diagram of the output register of the processor program fragment.

 FIG. 13 is a functional block diagram of an input register of a processor of a program fragment.

 Fig. 14 is an illustration of a general view of a stream computing graph.

 15 is an illustration of a structure of an information packet.

DETAILED DESCRIPTION OF THE PRESENT INVENTION
A program diagram of a data flow system is described as a graph consisting of nodes and links connecting nodes. Nodes represent operations, and relationships represent the path of tokens through the system. Information provided by the node is collected in packets.

 Information markers are words that are divided into a number of fields. The fields may contain an operation code field for representing an operation performed with data, one data field for representing information to be processed, one or two address fields for representing an address or node to which processing results are sent, and other fields for representing a program execution context , tags or keys used for identification during data processing. Keys or tags are used to identify the fragment number, the iteration to be performed, the individual markers of a pair intended for one node, and so on.

 Information packets are also words that are divided into a number of fields. A packet may contain one or two data fields.

 Thus, a program written in accordance with a data flow graph will indicate the direction in which data is transferred during processing. Each node processes the input data and produces one or more results that are routed to one or more other nodes.

 The computer described in this application contains a central processor and a fragment program processor. The central processor processes the data in accordance with the principle of data flow. The fragment program processor for data processing uses the von Neumann principle.

 The computer described in this application contains a central processor 1, an I / O switch 2, a command loading switch 3, a memory 4 for storing commands, a data access unit 5, and a fragment program processor 6.

 The data access unit 5 contains an associative memory 109, a first buffer 106 and a second buffer 107. The first buffer 106 is for storing data sent to the central processor 1, and the second buffer 107 is for storing data sent to the processor 6 of the fragment program. The processor 6 of the fragment program comprises an execution unit 130. The execution unit 130 comprises a RAM 151.

 A set of instructions for processing data of the main program, that is, the program to be executed, is loaded into memory 4 for storing instructions. The set of instructions and data of the fragment programs are loaded into the processor 6 of the fragment program, in particular, into the RAM 151.

 Packets and markers intended for processing in the main processor are sent through the direct data access unit 5 to the central processor 1.

 The packets received in the central processor 1 are processed and processing results are obtained. If the result obtained is the final result, that is, if it is not intended for another node, then the result is sent to the output of the system. If the result is the result of a one-time input, that is, it is intended either for a one-time input to the subsequent node of the data flow scheme, or for input of a fragment into the processor program, then the result is sent directly to the direct data access unit for additional processing.

 The data access unit 5 sends information ready for further processing to the corresponding device. Information sent for additional processing in accordance with the principle of data flow is sent to the central processor 1, information intended for processing in accordance with the von Neumann principle is sent to processor 6 of the fragment program. Information intended for processing in the processor program fragment is identified as fragments. A fragment may consist of one or more instructions and corresponding operands.

 The data intended for input into the data flow circuit is sent to the first buffer 106 for further direction to the central processor 1 either immediately or after being stored in the first buffer 106. The data intended for insertion into the von Neumann circuit is sent to the second buffer 107 for further directing the fragment to the processor 6 of the program, either immediately or after storage in the second buffer 107.

 If the result is the result of double entry, that is, the result is intended to be one of two inputs to the subsequent node, then the result is sent indirectly to the associative memory 109 located in the direct data access unit 5, through the input-output switch 2 for additional processing.

 Each token received by the I / O switch 2 must be matched with its pair for further processing. An I / O switch 2 reads a key on each token received to determine if a token pair is already stored in associative memory 109. If this pair is detected, then these two tokens are connected together in a packet.

 If the received marker pair is not detected, then the marker is sent to associative memory 109 and stored there to wait for its pair to arrive.

 Paired data (or packet) intended for input into the data flow circuit is sent to the first buffer 106 for further direction to the central processor 1 either immediately or after storage in the first buffer 106. Data intended for introduction into the von Neumann circuit is sent to the second buffer 107 for further direction to the processor 6 of the program fragment either immediately or after storage in the second buffer 107.

 Thus, to prepare information for further processing, the I / O switch and associative memory functionally work together. As mentioned above, information ready for further processing is sent using the data access unit to the appropriate device for further processing.

BEST MODE FOR CARRYING OUT THE INVENTION
As shown in FIG. 1, the computer includes a central processor 1, an input / output switch 2, a command loading switch 3, a memory 4 for storing commands, a data access unit 5, and a fragment program processor 6.

 The computer also contains a first information output 7, a second information output 8, resetting the input 9, the first information input 10 and the second information input 11.

 The central processor 1 comprises a first control input 12, a second control input 13, a first information input 14, a third control input 15, a fourth control input 16, a fifth control input 17, a second information input 18, a first control output 19, a second control output 20, and a third control output 21, fourth control output 22, first information output 23, second information output 24 and third information output 25.

 The processor 6 of the fragment program comprises a first control input 26, a first information input 27, a second control input 28, a third control input 29, a second information input 30, a first control output 31, a second control output 32, and information output 33.

 The memory 4 for storing commands contains a control input 34, information input 35, address input 36, information output 37 and control output 38.

 The data access unit 5 contains a first control input 39, a second control input 40, a third control input 41, a fourth control input 42, a fifth control input 43, a zeroing input 44, a first information input 45, a second information input 46, a third information input 47, the first control output 48, the second control output 49, the first information output 50, the second information output 51, the third control output 52, the fourth control output 53 and the third information output 54.

 The command loading switch 3 comprises a first information input 55, a second information input 56, a first control input 57, a second control input 58, a control output 59, and an information output 60.

 The I / O switch contains a first control input 61, a second control input 62, a third control input 63, a fourth control input 64, a first information input 65, a second information input 66, a first control output 67, a second control output 68 and information output 69.

 As shown in FIG. 2, the central processor 1 comprises a control device 70, a switch 71, an output register unit 72, an arithmetic logic unit 73, and an input register unit 74.

 The control device 70 contains a zero-setting input 75-1, a first result transfer control input 75-2, a second result transfer control input 75-3, an initial control input 75-4, a command type bit input 75-5, a ready signal input 75-6 memory, input 75-7 signal of significance of the data bit, input 75-8 signal ready, the first control output of the output switch 76-1, the second control output of the output switch 76-2, the control output 76-3 transmission, the control output 76-4 reception, initial control output 76-5, first control output, connected nenny yield CPU 19 1, the second control output coupled to the output 21 of the CPU 1, and a third control output coupled to the output 22 of the CPU 1.

 Block 72 of the output register contains control inputs 77-1, 77-2 and 77-3, information inputs 77-4, 77-5 and 77-6 and information outputs 78-1, 78-2 and 78-3.

 The switch 71 contains an information output connected to the output 24 of the central processor 1, a first control input connected to an output 76-1 of the control device 70, a first information input connected to an output 78-2 of the output register unit 72, and a second information input connected to output 78-3 of the block 72 of the output register.

 Block 74 of the input register contains a control input 79-1, information input 79-2 and information outputs 80-1 ... 80-5.

 The arithmetic-logical device 73 (made in analog form for the device described in USSR patent 1367012, issued in 1985) contains an operation control input connected to the output 80-2 of the input register block 74, the input of the first operand connected to the output 80-3 block 74 of the input register, the input of the second operand connected to the output 80-4 of the block 74 of the input register, the initial control input connected to the output 76-5 of the control device 70, the first information output connected to the output 25 of the central processor 1, the second info a radiation output connected to an input 75-7 of a control device 70 and an input 77-4 of an output register unit 72, and a control output connected to an input 75-8 of a control device 70.

 As shown in FIG. 3, the control device 70 comprises OR elements 81-1 and 81-2, elements 82-1. . .82-4, 83-1 and 83-2 "AND", element 84 "OR", elements 85-1, 85-2 "AND", element 86 "OR", priority encoder 87, elements 88-1, 88 -2 and 89 "OR", triggers 90-1 ... 90-3, triggers 91-1 ... 91-3, elements 92-1 ... 92-6 "AND", element 93 "OR" and element 94 AND.

 As shown in FIG. 4, the input register block 74 comprises a status word register 95, a first operand register 96-1 and a second operand register 96-2.

 As shown in FIG. 5, the output register block 72 comprises a result register 97, first and second registers 98-1 and 98-2 of a command number, respectively, and a status indication register 99.

 As shown in FIG. 6, the I / O switch 2 contains OR elements 100-1 ... 100-4, AND elements 100-1 ... 100-2, priority encoder 102, triggers 103-1, 103-2, switching device 104, input registers 105-1,105-2.

 The switching device 104 may consist of two AND elements and one OR element, or a logical element, for example, an OR-NOT logical element.

 As shown in FIG. 7, the data access unit 5 comprises first and second buffers 106 and 107, respectively, a register 108 and an associative memory 109.

 The first buffer 106 contains the first and second control inputs 110-1 and 110-2, the first and second information inputs 110-3 and 110-4, the third and fourth control inputs 110-5 and 110-6, the external exchange input 110-7, the first and second control inputs of the transmission, respectively connected to the outputs 49 and 52 of block 5, the information output connected to the output 50 of block 5 and the external exchange output connected to the output 51 of block 5.

 The second buffer 107 contains the first and second control inputs 111-1 and 111-2, respectively, the first and second information inputs 111-3 and 111-4, the third and fourth control inputs 111-5 and 111-6, respectively, and the control and information inputs, connected respectively to the outputs 53 and 54 of block 5.

 Associative memory 109, made similar to the device described in the patent of the Russian Federation 2035069, issued in 1995, contains the first and second control inputs 112-1 and 112-2, respectively, the first information input 112-3, the third control input 112-4, the second information input 112-5, first information output 115-6, first control output 113-2, second information output 113-3 and second control output 113-4.

 As shown in Fig. 8, the first buffer 106 comprises OR elements 114-1 ... 114-5, an output switch 115, AND elements 116-1 ... 116-4, a memory register unit 117, a control device 118, an input switch 119, and first and second input registers 120-1 and 120-2, respectively.

 The second buffer is made similarly to the first.

 The control device 118 comprises control outputs 121-1 ... 121-12, a setup input 122-1, a first packet code input 122-2, a first receiving control input 122-3, a second packet code input 122-4, a second and third receiving control inputs 122-5 and 122-6, respectively, and the first ... fifth control inputs 123-1 ... 123-5.

 As shown in FIG. 9, the control device 118 comprises a priority encoder 124, counters 125-1 ... 125-2, logic elements 126-1 ... 126-4 "And", triggers 127-1 ... 127-3, element 128 " OR "and decoders 129-1 ... 129-3.

 As shown in FIG. 10, the fragment program processor 6 comprises an execution unit 130, an output register unit 131, a load register unit 132, and an input register unit 133.

 The Executive unit 130 contains the first. .. the third control inputs 134-1. .134-3, information input 135, information output 136 and the first ... fifth control outputs 137-1 ... 137-5.

 Block 131 of the output register contains the first ... seventh control inputs 138-1. ..138-7, information input 139, first ... third control outputs 140-1 ... 140-3 and information output 141.

 Block 132 of the boot register contains the first ... fifth control inputs 142-1. . .142-5, information input 143, first and second control outputs 144-1 and 144-2, and information output 145.

 Block 133 of the output register contains the first ... sixth control inputs 146-1. ..146-6, information input 147, first ... third control outputs 148-1 ... 148-3 and information output 149.

 As shown in FIG. 11, the execution unit 130 comprises a microprocessor 150, a random access memory 151, and an exchange bus 152. Instead of these elements, a standard microprocessor kit can be used, for example, a kit based on elements of the Intel 80386 type.

 As shown in FIG. 12, the output register block 131 comprises first and second registers 153 and 154, respectively, AND elements 155-1 ... 155-3, trigger 156, decoders 157-1 and 157-2, element 158 " OR "and register 159.

 As shown in FIG. 13, the input register block 133 comprises registers 160 and 161, an AND element 162, a decoder 163, a register 164, a trigger 165, and an OR element 166.

 Block 132 of the boot register has a similar structure.

 The principles of organization of computation in data flow control assume that the algorithm for solving the problem is presented as a graph of the computation process. The graph contains operators (commands) on the data (operands) and pointers (directions), following which the data (results) are transmitted from command to command, as shown in Fig. 14.

 In accordance with the graph, data processing is performed upon receipt of prepared data for processing at command inputs. The completion of data pairs related to a particular command is performed in associative memory 109, using the key when searching and generating data pairs. The key, as a rule, is a code that contains the bits of the command number, index, iteration, and so on.

 Each command has a number N-i, which can be used to store it in memory 4 for storing commands, the command code is COI-i, and the number N-j of the “assigned address” representing the command to which the data processing result belongs. In addition, the team has attributes that determine its processing conditions or its type. A command can be a two-input or a single-input command, which is determined by the operation code, depending on how many (one or two) inputs the command processes. The command can be a two-address or unicast command, depending on the number of transmission addresses of the result (s) of the command. For example, as shown in FIG. 14, command N1 is a single-input, unicast command, and command N2 is a single-input, unicast command.

 To organize the work of the graph, commands and data are presented as information objects consisting of multi-bit words, where the corresponding groups of bits form fields with the necessary functional purpose (Fig. 15).

 In general, the information is input to the central processing unit 1 as a data packet containing a status word (command) and two data words. A single-entry command packet contains only one information word.

The status word contains the following main groups of functional bits (fields):
COI - command code;
N - team number;
G is the generation number;
T is the iteration number;
I is the index;
F is the number of the fragment.

 The functional fields of the status word can be used in various ways. In particular, the main group of bits for searching data in associative memory 109 is limited to the fields N, G, T, I. Field F is entered if it is necessary to find input data for the fragments. The COI field may contain bits indicating the type of command (unicast, two-address, single-input, two-input).

 If the command has two outputs (destination addresses for the processing results), then the result of its execution will contain two status words corresponding to two transmission addresses.

 The bit groups of the status word are stored in memory 4 for storing instructions.

 Commands and data that are part of the marked fragments (Fig. 14) are stored in RAM 151 of the executive unit 130 of the processor 6 of the fragment program and do not occupy associative memory 109.

 The synchronization inputs of all blocks of the computer are connected to an external synchronization input (not shown).

 The main work programs and marked programs of the fragment are downloaded through the first information input 10 and executed by a computer (Fig. 1), which gives the results of data processing through the second information output 8.

 The computer uses data flow control for the calculation process in accordance with the main program and in accordance with the von Neumann principles of data processing to execute marked fragments. All instructions of the main executive program are entered into memory 4 for storing instructions, and all instructions and data for fragments are entered into the RAM 151 (Fig. 11). The calculation is initialized by loading the initial operand packages from an external system (not shown) through the second information input 11.

 The initial packets along with the corresponding control signals are input through the second information input 46 of the data access unit 5 and then through the external exchange input 110-7 of the first buffer 106, from which they are transmitted to the information (for example, fourth) input of the output switch 115. In this case communication control is carried out through the fourth control input, and the corresponding control signal from the control output 121-12 of the control device 118 is supplied through the element 116-4 "AND". The specified control signal is generated at the output of decoder 129-3. A group of bits of code that determines the type of the initial packet arrives through the input of decoder 129-3.

 The bits of the packet from the output 50 of the buffer 106 are transmitted to the second information input 18 of the central processor 1 through the corresponding output of the data access unit 5.

 The information transmitted through the output 50 of the data access unit 5 is accompanied by a transmission strobe at the output 52. The transmission strobe at the output 52 is a control signal for starting the central processor 1 through the fifth control input 17 and then through the input 75-4 of the control device 70 The bits of the operand packet are transmitted to the information input 79-2 of the input register block 74.

 The reception of the functional fields of the operand packet by the status word register 95 and the operand registers 96-1 and 96-2 is controlled by inputting a receiving control signal at the input 79-1 of the input register block 74. The bits of the command number are transmitted from the output 80-1 of the input register block 74 through the first information output 23 of the central processor 1 to the first information input 55 of the command loading switch 3. The control signal from the second control output 20 of the Central processor 1 is fed to the first information input 57 of the block 3 download commands. The control signal corresponding to the read code and the information signal corresponding to the address are formed respectively on the control and information outputs 59 and 60 of the switch 3 for transmission to the corresponding control and address inputs of the memory 4 for storing commands. The code of the operation bits and operand bits from the outputs 80-2, 80-3 and 80-4 of the input register block 74 are accompanied by an initial control signal from the output 76-5 of the control device 70 and are transmitted to the corresponding inputs of the arithmetic-logical block 73. Bits G, T , I of the functional field are transmitted to the input 77-6 of the block 72 of the output register. The bits of the functional field from the information output 37 of the memory 4 for storing instructions are transmitted through input 14 of the central processor 1 to input 77-5 of the block 72 of the output register. The bits of the functional field, transmitted to the input 77-5, contain the operation code and the command number for which the calculation result intended for the input 77-4 of the block 72 is intended.

 The inputs 77-1, 77-2 and 77-3 of the block 72 of the output register receive the corresponding signals that control the reception of the result by the register 97, the bit fields N and COI of the next command by the registers 98-1 and 98-2 and the bit fields G, T, I register 99. Functional fields of the result of the current command (half-packet) are generated at the outputs 78-1, 78-2 and 78-3 of the block 72 of the output register. These fields reflect the principles of calculation, presented using the graph of the calculation process, and are transmitted, respectively, to the output 24 of the central processor 1 and the information inputs of the switch 71. The control signals are transmitted from the outputs 76-1 and 76-2 of the control device 70 to the control inputs of the switch 71 The operation of the switch 71 depends on the availability of two-address instructions, that is, instructions whose execution result is an input operand for the next two instructions (having different numbers and different instruction codes). This condition is satisfied when there are two output registers 98-1 and 98-2 of the command number, the contents of which are sequentially transmitted through switch 71 and are accompanied by the result transmitted to the output 24 of the central processor 1.

 The control signals for the output switch 71 are generated upon receipt of the input fields 75-5 and 75-6 of the control device 70 functional fields such as commands and transmission strobe, respectively, from the information and control outputs 37 and 38 of the memory for storing commands through the inputs 14 and 15 of the Central processor 1 and when receiving at the input 75-7 a signal of significance of the result from the arithmetic-logical unit 73.

 Functional fields of the command type contain the following attributes: 1A (unicast command), 2A (two-address command) and 2I (two-input command), which are transmitted to triggers 92-2 ... 92-5. The state of the trigger determines the formation of control signals at the outputs 76-1 and 76-2 of block 70. Transmission gates corresponding to the modes of a single-input or two-input command are generated at outputs 22 and 19 of the central processor 1, and bits of the functional fields of the half-packet are output 24.

 If a one-input command is executed and the execution result does not require a pair search in associative memory 109, then the bits of the half-packet and transmission strobe are transmitted from the outputs 24 and 22 of the central processor 1, respectively, to the inputs 47 and 43 of the data access unit and to the inputs 110-3 and 110- 5 of the buffer 106. When bits arrive at input 110-3, the result is received by the first input register 120-1 and is transmitted through the first information output of the input switch 119 to the first information input of the switch 115. The second information output of the switch 119 using tsya for transmitting calculation results to the external control system. In this case, the corresponding control signal is generated at the first output of the decoder 129-1 of the control device 118. The bits of the code that determine the type of half-packet arrive at the input of decoder 129-1. Information from the second information output of the switch 119, together with the transmission gate from the output 121-7 of the control device 118, is transmitted to the output 51 of the buffer 106 and transmitted through the corresponding output of the data access unit 5 to the second information output 8 of the computer.

 If the result (operand) at the output 24 of the central processor 1 refers to a two-input instruction, then a pair operand is searched in the associative memory 109 in the data access unit 5. This result from the output 24 is transmitted to the input 65 of the I / O switch 2 and through the I / O switch 2 to the data access unit 5.

 The transmission strobe signal and the bits of the functional fields of the half-packet are transmitted from the outputs 19 and 24 of the central processor 1 to the inputs 61 and 65 of the input / output switch 2, respectively.

 In switch 2, the half-packet is transmitted from input 65 through register 105-1 to the first information input of switching device 104. A transmission strobe is transmitted from input 61 to trigger setup input 103-1. The output of the trigger 103-1 is connected to the first control input of the priority encoder 102. The control code of the switching device 104 is generated at the first and second control outputs of the priority encoder 102. The end result is that in switch 2, the bits of the functional fields of the half-packet are transmitted from input 65 to output 69, and output 67 generates the corresponding control signal and transmission strobe.

 The bits of the functional fields and the transmission gate are transmitted from the outputs 69 and 67 of the switch to the inputs 45 and 39 of the data access unit 5. The bit fields of the status word (as an associative search key), the operand, and the transmission strobe are respectively supplied to the inputs 112-3, 112-5, and 112-4 of the associative memory 109.

 Bit fields of the status word also go to the information input of the register 108. The transmission gate from the input 39 of the data access unit 5 is fed to the control input of the register 108.

 A half-packet to which no pair has been found remains in associative memory 109. If a corresponding operand pair is found, then bit fields of the first and second operands are generated at outputs 113-1 and 113-3. These bit fields are transmitted together with the bit fields of the status word from the output of the register 108 to the second information inputs 110-4 and 111-4 of the buffers 106 and 107, respectively. A transmission gate is transmitted from the output 113-2 of the associative memory 109 to the inputs 110-6 and 111-6 of the buffers 106 and 107, respectively.

 If the resulting packet is a package of operands of the main program, then the bits of its functional field are received on the register 120-2 of the buffer 106, and at the output 121-9 of the control device 118, a corresponding receive control signal is generated.

 The bit fields of the packet are transmitted from the output of the register 120-2 to the second information input of the switch 115, and the corresponding switching control signal is transmitted from the output of the element 116-1 "AND" to the corresponding control input of the switch 115. The switch 115 transmits the bit fields to the first output of the switch 115, which performs the function of a transmission gate, which is ultimately formed at the output of the OR element 114-1.

 If the block 74 of the output register of the central processor 1 is free, then all the information from the output of the switch 115 of the buffer 106 is transmitted to the central processor 1 and the data processing cycle is repeated.

 If the unit 74 of the central processor 1 is busy, then from the output 21 of the central processor 1 through the input 41 of the data access unit 5 to the input 110-1 of the buffer 106 is transmitted a transmission blocking signal. After that, the signal is transmitted from input 110-1 to input 123-2 of control device 118 and to the input of OR element 114-5. At the output of the OR element 114-5, a control signal is generated, which is transmitted to the fifth control input of the switch 115. Information from the second information input of the switch 115 is transmitted through the second output of the switch 115 and then, accompanied by a write signal from the output 121-11 of the control device 118, transmitted to the input of block 117 of the storage register. Information will be recorded in block 117 before the output of the lock signal from the output 21 of the central processor 1. If there is no information in the registers 120-1 and 120-2 and at the fourth information output of the switch 115, the output of the lock signal leads to the transmission of bits of the packet from block 117 through the third the information input of the switch 115 and the corresponding output of the buffer 106 and the output 50 of the data access unit 5 to the input 18 of the Central processor 1.

 If the packet generated at the output of register 108 and outputs 113-1 and 113-2 of associative memory 109 is the initial local program packet indicated by fragment F, then the bits of its functional fields are received by buffer 107.

 In other cases, the transfer of the initial packet of the fragment F to the input 30 of the processor 6 of the fragment program is carried out similarly to the above transmission of the operand packets through the buffer 106.

 The bits of the functional fields of the initial packet of the fragment and the transmission gate, generated respectively at the outputs 54 and 53 of the data access unit 5, are received respectively at the inputs 30 and 29 of the processor 6 of the fragment program. In contrast to the central processor 1, where after the execution of each packet, access to the associative memory 109 is performed, in the processor 6 of the fragment program, the marked fragments (parts) of the main program are executed and the final results are transferred to the associative memory.

 At the beginning of computer loading, programs (corresponding to the von Neumann processing principles) are loaded through the first information input 10.

 In this case, both the commands and the data are received through the input 27 of the processor 6 of the fragment program, from where they are transmitted to the input 143 of the load register block.

 The bits of the functional fields of the commands (corresponding to the command system of the executive unit 130) and data are transmitted from the output 145 of the block 132 to the information input 135 of the block 130. The transmission from the output 145 to the input 135 is accompanied by the transmission of the corresponding interrupt and ready signals from the outputs 144-1 and 144-2 block 132 to the inputs 134-2 and 134-3, respectively, of block 130.

 Through the bus 152 exchange under the control of the microprocessor 150 in the RAM 151 is the loading of commands and data fragments of work programs.

 Upon receipt of the initial packets of the fragment at the input 147 of the block 133 and the corresponding transmission gate to the input 146-5 of the block 133, the operands are received by the registers 160 and 161, and the field F of the status word is received by the register 164. The presence of the transmission gate at the input 146-5 prepares the trigger 165 and an interrupt signal is generated at the output 148-2. The interrupt signal arrives at input 134-2 of block 130 together with a bit field that enters information input 135 of block 130 from output 149 of block 133. The bit field at output 149 is received from register 164 under the control of the output of the read signal from trigger 165. Microprocessor 150 "identifies" the bit field transmitted through the exchange bus 152 from the input 135 of block 130, and provides the output of a group of control signals at outputs 137-1, 137-2, 137-3, and 137-4. This group of control signals is transmitted to the inputs 146-2, 146-2, 146-4 and 146-6 of the block 133, where the corresponding signals of sequential reading and transmission of data from the registers 160 and 161 are generated through the output 149 at the information input 135 of the block 130. Microprocessor 150 in accordance with the number and parameters of the fragment F starts the corresponding execution of the program. The completion of the program is accompanied by the interruption of the microprocessor 150. Due to this interruption, the microprocessor 150 generates an "output vector" that corresponds to the current number assigned to the register 159 of block 131. The "exit vector" is transmitted via the exchange bus 152 and the output 136 to the input 139 of block 131. Transfer " of the output vector "is accompanied by the transfer of the control signal from the output 137-5 of the block 130 to the input 138-7 of the block 131. Information is recorded in the register 159. Information from the register 159 is transmitted to the input of the decoder 157-1. At the output of decoder 157-1, an interrupt signal is generated and transmitted through output 140-1 to input 134-2 of block 130. When the microprocessor 150 receives the interrupt signal, a group of control signals is generated, which is transmitted through outputs 137-1 ... 137-4 of block 130 to inputs 138-3 ... 138-6 of block 131. The signals received at inputs 138-3 ... 138-6 control the reception (at the inputs of registers 153 and 154) of bit fields that are generated as a result of processing fragment F. The bit fields received at the inputs of the registers 153 and 154 are transmitted from the output 136 of the block 130 through the input 139 of the block 131.

 The data format in registers 153 and 154 corresponds to the half-packet format obtained as a result of the execution of instructions by the central processor 1. That is, the format of the results of processing the fragment program by the processor and the format of the results of processing by the central processor are the same and the results of processing by these two devices can be combined in associative memory (or where or else depending on the specific configuration of the system).

 A transmission gate is formed at the output 140-3 of the block 131 and transmitted to the output 32 of the processor 6 of the fragment program. The transmission gate is transmitted from the output 32 to the input 63 of the switch 2. The functional bit fields of the half-packet that are formed as a result of the fragment program are transmitted from the output 33 of the processor 6 to the input 66 of the switch 2.

 The bit fields of the half-packet are transmitted from the output 69 of the switch 2 to the input of the data access unit 5. The results of the fragment program execution and the execution of the main program are combined by means of a common field.

 Thus, the introduction of a fragment program into the processor system and the organization of corresponding links reduce the amount of data stored in associative memory.

 Reducing the amount of associative memory increases the speed of its exchange and increases the speed in the process of execution of the main work programs when using the flow control of calculation data.

Claims (2)

 1. An information processing system comprising a central processor 1, an input / output switch 2, a command loading switch 3, a memory 4 for storing commands, a data access unit 5, a first information output 7, a second information output 8, resetting input 9, the first information an input 10 and a second information input 11, the first control output 19 of the central processor 1 being connected to the first control input 61 of the input / output switch 2, the first control output 67 of the input / output switch 2 connected to the first control input 39 of the data access unit 5, the first information input 45 of the data access unit 5 is connected to the information output 69 of the input / output switch 2, the address input 36 of the memory 4 for storing commands is connected to the information output 60 of the command loading switch 3, the first control input 57 of the switch 3, the command download is connected to the second control output 20 of the central processor 1, the first information output 23 of the central processor 1 is connected to the first information input 55 of the command download switch 3, the second information output d 24 of the central processor 1 is connected to the first information input 65 of the input-output switch 2, the third information output 25 of the central processor 1 is connected to the first information output 7 of the system, the resetting input 44 of the data access unit 5 is connected to the resetting input 9 of the system, the information input 35 memory 4 for storing commands is connected to the first information input 10 of the system, the second information input 56 of the switch 3 download commands connected to the first information input 10 of the system, the processor 6 of the program fragment, and the first control output 31 of the fragment program processor 6 is connected to the second control input 40 of the data access unit 5, the first control output 48 of the data access unit 5 is connected to the second control input 62 of the input / output switch 2, the second control output 68 of the input / output switch 2 connected to the first control input 12 of the central processor 1 and to the first control input 26 of the fragment program processor 6, the second control output 32 of the fragment program processor 6 is connected to the third switch control input 63 Filling I / O 2, the second information input 66 of the I / O switch 2 is connected to the information output 33 of the fragment program processor 6, the second control output 49 of the data access unit 5 is connected to the second control input 13 of the central processor 1, the first information input 14 of the central processor 1 is connected to the information output 37 of the memory 4 for storing commands, the control input 34 of the memory 4 for storing commands is connected to the control output 59 of the switch 3 command download, the second control input 58 of the switch 3 command loads and the first information input 27 of the fragment program processor 6 are connected to the first information input of the system 10, the control output 38 of the memory 4 for storing commands is connected to the third control input 15 of the central processor 1, the third control output 21 of the central processor 1 is connected to the third control input 41 block 5 access to data, the second information input 46 of block 5 data access is connected to the second information input 11 of the system, zeroing input 9 of the system is connected to the second control input 28 of the process and 6 of the fragment program, with the fourth control input 42 of the data access unit 5, with the fourth control input 64 of the input / output switch 2 and with the fourth control input 16 of the central processor 1, the fourth control output 22 of the central processor 1 is connected to the fifth control input 43 of the block 5 data access, the third information input 47 of the data access unit 5 is connected to the second information output 24 of the Central processor 1, the fifth control input 17 of the Central processor 1 is connected to the third control output 52 bl OK 5 data access, the first information output 50 of the data access unit 5 is connected to the second information input 18 of the central processor 1, the second information output 51 of the data access unit 5 is connected to the second information output 8 of the system, the third control input 29 of the processor 6 of the fragment program connected to the fourth control output 53 of the data access unit 5 and the third information output 54 of the data access unit 5 is connected to the second information input 30 of the fragment program processor 6.  2. The system according to claim 1, characterized in that the fragment program processor 6 comprises an execution unit 130, an output register unit 131, a load register unit 132 and an input register unit 133, the information output 136 of the execution unit 130 being connected to the information input 139 of the unit 131 output register, the first control input 138-1 of the output register block 131 is connected to the first control input 26 of the fragment program processor 6, the second control input 28 of the fragment program processor 6 is connected to the first control input 134-1 executor block 130, with a second control input 138-2 of the output register block 131, with a first control input 142-1 of the load register block 132 and with a first control input 146-1 of the input register block 133, a first control output 148-1 of the input register block 133 connected to the first control output 31 of the fragment program processor 6, the first information input 27 of the fragment program processor 6 is connected to the information input 143 of the load register block 132, the information output 145 of the load register block 132 and the information output 149 of the input re block 133 the histories are connected to the information input 135 of the executive unit 130, the second control input 134-2 of the executive unit 130 is connected to the first control output 140-1 of the output register unit 131, with the first control output 144-1 of the load register unit 132 and with the second control output 148- 2 input register blocks 133, a third control output 148-3 of the input register block 133 and a second control output 140-2 of the output register block 131 are connected to a third control input 134-3 of the executive block 130, the first control output 137-1 of the executive b OKA 130 is connected to the second control input 142-2 of the load register block 132, to the second control input 146-2 of the input register block 133 and to the third control input 138-3 of the output register block 131, the third control output 140-3 of the output register block 131 is connected with the second control output 32 of the fragment program processor 6, the second information input 30 of the fragment program processor 6 is connected to the information input 147 of the input register block 133, the third control input 146-3 of the input register block 133, the third control input 142-3 of block 1 32 load registers and the fourth control input 138-4 of the output register unit 131 are connected to the second control output 137-2 of the executive unit 130, the third control output 137-3 of the executive unit 130 is connected to the fourth control input 146-4 of the input register unit 133, with a fourth the control input 142-4 of the load register block 132 and with the fifth control input 138-5 of the output register block 131, the information output 141 of the output register block 131 is connected to the information output 33 of the fragment program processor 6, the third control input 2 9, the fragment program processor 6 is connected to the fifth control input 146-5 of the input register block 133, the sixth control input 146-6 of the input register block 133, the fifth control input 142-5 of the load register block 132 and the sixth control input 138-6 of the output register block 131 connected to the fourth control output 137-4 of the Executive block 130, and the fifth control output 137-5 of the Executive block 130 is connected to the seventh control input 138-7 of the block 131 of the output register.

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