RU2210862C1 - Broadband transceiving device - Google Patents

Abstract

FIELD: radio communications. SUBSTANCE: broadband transceiving device has transmitting section, receiving section, and burst generating and decoding unit. Newly introduced in receiving section are pseudorandom sequence generator unit incorporating third and fourth pseudorandom sequence generators and synchronizing unit; burst generating and decoding unit is provided with third and fourth outputs. EFFECT: enhanced reliability of data received. 1 cl, 1 dwg

Description

 The invention relates to radio communications, and in particular to broadband transceiver devices with pseudo-random tuning of the operating frequency (PFC), and can find application in duplex radio lines of any length when transmitting discrete information.

 Known broadband transceiver devices [1, 2, 3, 4, 5], transmitting messages in the frequency hopping mode. A common disadvantage of these devices is that, having a strict frequency tuning program, they are not able to adapt to changing interference conditions, that is, control the choice of transmitter carrier frequency, based on the analysis of the interference situation during communication.

 The closest in technical essence to the proposed device is a device [6], operating in the frequency hopping mode. This device is selected as a prototype. It includes the first, second, third, fourth and fifth frequency synthesizers (MF1, MF2, MF3, MF4, MF5), a modulator (M), the first and second antenna devices (A1, A2), the first pseudorandom sequence generator (GPSP1) with output the frequency code of the current clock pseudo-random sequence (PSP) and the output of the frequency code of the next clock cycle PSP, the second pseudorandom sequence generator (GPSP2) with the output of the frequency code of the current clock bandwidth and the output of the frequency code of the next clock bandwidth, the commutator (K), a packet forming and decoding device in (UVDP), the first, second, third and fourth frequency converters (ПЧ1, ПЧ2, ПЧ3, ПЧ4), the first and second intermediate frequency amplifiers (UPCh1, UPCh2), the first and second demodulators (D1, D2), the first and second amplitude detectors (АД1, АД2), the first and second threshold devices (ПУ1, ПУ2), a comparison circuit (CC), and a clock generator (SG). The output of the information source (AI) is connected to the first input of the UVDF, the first output of which is connected to the second input M, the output of which is connected to the input A1. The output of the frequency code of the current clock cycle of the SRP GPSP1 is connected to the first input K and the input of MF2, the output of the frequency code of the next clock cycle of the SRP GPSP1 is connected to the input of MF4. The output of the frequency code of the current clock cycle of the SRP GPS2 is connected to the second input K and the input of MF3, the output of the frequency code of the next clock cycle of the SRP GPS2 is connected to the input of MF5. The output To is connected to the input MF1, the output of which is connected to the first input M. Output A2 is connected to the first inputs of the MF1, MF2, MF3, MF4. The MF2 output is connected to the second input of the IF1, the output of which is connected to the input of the UHF1, the output of the UHF1 is connected to the input D1, the output of which is connected to the second input of the UFDP and the first input of the SG. The MF3 output is connected to the second input of the frequency converter 2, the output of which is connected to the input of the UHF2, the output of the MCH2 is connected to the input D2, the output of which is connected to the third input of the UFDP and the second input of the SG. The MF4 output is connected to the second input of the MF3, the output of which is connected to the input of AD1, the output of which is connected to the input of PU1. The MF5 output is connected to the second input of the MF4, whose output is connected to the input of AD2, the output of which is connected to the input of PU2. The outputs PU1 and PU2 are connected respectively to the first and second inputs of the SS, the output of which is connected to the third input K and the fourth input of the UVDP. The SG output is connected to the third input of the SS, the input of GPS 1 and the input of GPS 2. The second output of the UFDP is connected to the input of the information receiver (PI).

 This device allows the reception and transmission of discrete information in the frequency hopping mode with a given quality by controlling the choice of the carrier frequency of the transmitter in a changing jamming environment during communication. The choice of the carrier frequency of the transmitter is controlled based on the analysis of the interference situation, which is carried out at the same end of the radio line as the controllable transmitter is located, using control receivers located in the same device as the controllable transmitter. It is assumed that the interference environment at both ends of the radio link is identical, which is true for short-haul radio links.

 The disadvantage of the prototype is the impossibility of its use in long-distance radio lines, which are characterized by different jamming conditions at both ends of the radio line. In this case, it is possible to select the carrier frequency of the transmitter, optimal for one end of the radio line, but affected by interference at the other end of the radio line.

 The aim of the invention is the development of a broadband transceiver with frequency hopping, which increases the reliability of the received discrete information in a duplex radio frequency hopper of any length under the influence of interference by controlling the choice of the carrier frequency of the transmitter of the device located at one end of the radio based on the analysis of the interference situation carried out by control receivers of the device located at the other end of the radio line.

To achieve a technical result in a broadband transceiver device, including: MF1, MF2, MF3, MF4, MF5, M, A1, A2, GSPP1, GSPP2, K, UFDP, MF1, MF2, MF3, MF4, MF1, MF2, D1, D2 , AD1, AD2, PU1, PU2, SS, moreover, the AI output is connected to the first input of the UVDF, the first output of which is connected to the second input M, the output of which is connected to the input A1, the output of the frequency code of the current clock of the SRP GPS1 is connected to the first input K, the output the frequency code of the current clock cycle of the SRP GPS2 is connected to the second input K, the output K is connected to the input MF1, the output of which is connected to the first input , the output A2 is connected to the first inputs of the inverter 1, inverter 2, inverter 3, inverter 4, the output of the inverter 2 is connected to the second input of the inverter 1, the output of which is connected to the input of the inverter 1, the output of the inverter 1 is connected to the input D1, the output of which is connected to the second input of the DFD, the output of the inverter 3 is connected to the second the input of the inverter 2, the output of which is connected to the input of the UPCH2, the output of the UPCH2 is connected to the input D2, the output of which is connected to the third input of the UFDP, the output of the MF4 is connected to the second input of the frequency converter3, the output of which is connected to the input of AD1, the output of which is connected to the input of PU1, the output of MF5 is connected to the second input of the inverter 4, the output of which is connected to aq2 course, whose output is connected to the input of PU2, PU1 and PU2 outputs respectively connected to first and second inputs of the SS, the SS output is connected to the fourth input UFDP, UFDP second output connected to the input UI, further introduced:
- a third pseudorandom sequence generator (GPSP3), the output of the frequency code of the current clock bandwidth of the SRP of which is connected to the MF2 input, and the output of the frequency code of the subsequent clock cycle of the SRP is connected to the MF4 input;
- a fourth pseudorandom sequence generator (GPSP4), the output of the frequency code of the current SRP clock cycle of which is connected to the MF3 input, and the output of the frequency code of the subsequent SRP clock cycle is connected to the MF5 input;
- synchronization unit (BS), the output of which is connected to the inputs of GPS 3, GPS 4 and the third input of the SS;
- the third and fourth outputs in the UVDP, which are connected respectively to the third input K and the input of the BS.

 Thanks to the new set of essential features, through the introduction of new blocks and connections, the reliability of the received discrete information in a duplex radio link with frequency hopping of any length is enhanced by controlling the choice of the carrier frequency of the device transmitter located at one end of the radio link based on the analysis of the interference situation carried out by control receivers a device located at the other end of the radio link.

 The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features identical to all the features of the claimed technical solution are absent, which indicates the compliance of the claimed device with the patentability condition of "novelty". Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed device from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the effect of the transformations provided for by the essential features of the claimed invention on the achievement of the specified technical result. Therefore, the claimed invention meets the condition of patentability "inventive step".

 The claimed device is illustrated in a structural diagram.

 The claimed device consists of a transmitting part, a receiving part and a device for generating and decoding packets 1.

The transmitting part includes:
- a block of pseudo-random sequence generators 2, consisting of a generator of the first SRP 2.0.1, a generator of the second SRP 2.0.2 and a switch 2.0.3, and the output of the frequency code of the current clock SRP GPSP1 2.0.1 is connected to the first input K 2.0.3, and the output the frequency code of the current clock cycle of the SRP GPS2 2.0.2 is connected to the second input To 2.0.3;
- transmitter 3, consisting of a first frequency synthesizer 3.0.1 and a modulator 3.0.2, and the output SCH 3.0.1 is connected to the first input M 3.0.2;
- first antenna device 4.

The receiving part includes:
- a block of pseudo-random sequence generators 5, consisting of a generator of the third SRP 5.0.1 and a generator of the fourth SRP 5.0.2;
- synchronization unit 6;
- comparison scheme 7;
- the first receiver 8.1, consisting of the first demodulator 8.1.1, the first intermediate frequency amplifier 8.1.2, the first frequency converter 8.1.3 and the second frequency synthesizer 8.1.4, and the output of the inverter 8.1.3 is connected to the input of the UPCH1 8.1.2, the output which is connected to the input D1 8.1.1, and the output of the midrange 8.1.4 is connected to the second input of the inverter 8.1.3;
- a second receiver 8.2, consisting of a second demodulator 8.2.1, a second intermediate frequency amplifier 8.2.2, a second frequency converter 8.2.3 and a third frequency synthesizer 8.2.4, and the output of the inverter 8.2.2 is connected to the input of the UCH2 8.2.2, the output which is connected to the input of D2 8.2.1, and the output of MF3 8.2.4 is connected to the second input of the MF2 8.2.3;
- the first control receiver 9.1, consisting of a first threshold device 9.1.1, a first amplitude detector 9.1.2, a third frequency converter 9.1.3 and a fourth frequency synthesizer 9.1.4, and the output of the frequency converter 9.1.3 is connected to the input AD1 9.1.2, the output of which is connected to the input of ПУ1 9.1.1, and the output of СЧ4 9.1.4 is connected to the second input of ПЧ3 9.1.3;
- the second control receiver 9.2, consisting of a second threshold device 9.2.1, a second amplitude detector 9.2.2, a fourth frequency converter 9.2.3 and a fifth frequency synthesizer 9.2.4, and the output of the inverter 9.2.3 is connected to the input of AD2 9.2.2, the output of which is connected to the input of ПУ2 9.2.1, and the output of СЧ5 9.2.4 is connected to the second input of ПЧ4 9.2.3;
- second antenna device 10.

 The output of the AI 11 is connected to the first input of the UVDP 1, the first output of which is connected to the second input of the transmitter 3 (second input M). The output of the GPS unit 2 (output K) is connected to the first input of the transmitter 3 (input MF1), the output of the transmitter 3 (output M) is connected to the input A1 4. Output A2 10 is connected to the first inputs of the receivers 8.1, 8.2 (to the first inputs, respectively, of the inverter 1 and IF2) and the first inputs of the control receivers 9.1, 9.2 (to the first inputs, respectively, of the FC3 and FC4). The output of the first receiver 8.1 (output D1) and the output of the second receiver 8.2 (output D2) are connected respectively to the second and third inputs of the UVD 1. The output of the first control receiver 9.1 (output PU1) and the output of the second control receiver 9.2 (output PU2) are connected respectively to the first and the second inputs of SS 7, the output of which is connected to the fourth input of UVDP 1. The output of BS 6 is connected to the first and second inputs of the GPS unit 5 (to the input of the GPS3 and the input of the GPS4) and the third input of the SS 7. First output of the GPS unit 5 (frequency code output the current cycle of the SRP GPSP3) is connected to the second input at the first receiver 8.1 (input MF2), the second output of the GPS unit 5 (output of the frequency code of the subsequent clock pulse of the GPS 3) is connected to the second input of the first control receiver 9.1 (input MF4). The third output of the GPS unit 5 (the output of the frequency code of the current clock pulse of the GPSSP4) is connected to the second input of the second receiver 8.2 (input SCH3), the fourth output of the GPS module 5 (the output of the frequency code of the next clock pulse of the GPSSP4) is connected to the second input of the second control receiver 9.2 (input MF5). The second output of the UVDP 1 is connected to the input of PI 12, and the third and fourth outputs of the UVDP 1 that are absent in the prototype are connected respectively to the input of the transmitter 3 (third input K) and the input of BS 6.

 In the claimed device, the synchronization unit 6 is designed to provide temporary synchronization of the receiving part of the device located at one end with the transmitting part of the device located at the other end of the radio line. It includes synchronization at the time of arrival of the signal and clock synchronization. Time synchronization can be provided by various methods and using various technical means [7, p. 15-23].

 The device for forming and decoding packets 1 is intended to form packets of information during transmission, decoding and unpacking them upon receipt. UVDP is most appropriate to build using microprocessor technology [8, p.329]. One of the options for its construction was considered in [9, Fig. 8, p. fifty].

 The remaining elements of the device can be performed according to known schemes considered in [10, 11, 12, 13].

 The necessity of introducing the GPS unit 5 is due to the impossibility of ensuring synchronous operation of the receiving part of the device located at one end of the radio line and the transmitting part of the device located at the other end of the long radio line if each correspondent has one GPS unit common to the receiving and transmitting parts, since time propagation of radio waves becomes commensurate with the operating time of the radio line at one frequency. This can lead to a malfunction of the radio link and the inability to communicate. The choice of the numbers of subsequent (n + x) SRP GPSP3 and GPSP4 clock cycles at which the interference situation will be analyzed depends on the operating conditions of the claimed device and will be determined by the number of clock cycles x for which the control receivers will be ahead of the working receivers, and which should be no less than time response of the transmitter control system, i.e.

где t_p - время реакции системы управления передатчиком;
t_псп - время одного такта ПСП.

where t _p is the response time of the transmitter control system;
t _PSP - the time of one clock cycle PSP.

The response time of the transmitter control system depends on the analysis time of the jamming situation, the algorithm for generating and decoding packets, the length of the radio line, the transmitter tuning time, and is determined by the expression
t _p = t ₁ + t ₂ + t ₃ + t ₄ ,
where t ₁ - time analysis of the interference environment;
t ₂ — packet formation time;
t ₃ is the transit time of the signal from the modulator of the device located at one end of the radio line through the propagation medium to the demodulator of the device located at the other end of the radio line;
t ₄ is the decoding time of the packet and the execution of the transmitter tuning command.

 To ensure communication in the radio line at one end of the device is placed the claimed device under 1, on the other - the claimed device under 2. Consider the operation of the devices on the example of the device under 1 (figure 1), the device under 2 works similarly.

 Frequency codes of the current clocks of the first and second memory bandwidth from the outputs of GPSP1 2.0.1 and GPSP2 2.0.2 are fed to the first and second inputs of K 2.0.3, respectively. Switch K 2.0.3 connects the frequency code of the current clock of one of the SRP to the input of SCh1 3.0.1. The necessary memory bandwidth, which is operational for the current clock cycle, is connected according to the control information for controlling the selection of the carrier frequency of the transmitter 3, formed in the device under 2, which is fed to the third, control input K 2.0.3 from the third output of the UVDP 1. At the same time, the other memory bandwidth at the current beat is considered a backup. The frequency synthesizer СЧ1 3.0.1 generates the carrier frequency of the transmitter 3, corresponding to the code of the current clock cycle of the operating memory bandwidth, synchronously with the formation of frequencies in the receivers of the device under 2. The generated carrier frequency of the transmitter is supplied to the first input М 3.0.2.

 The message from the AI 11 arrives at the first input of the UVDP 1 in the form of blocks of information of a fixed volume containing a header and data. In UVDP 1, information packets are formed by adding the service part to the information blocks and noise-resistant coding is carried out. The service part contains the opening flag, the address of the receiver and the sender, control information for controlling the selection of the carrier frequency of the transmitter of the device for 2, coming from the output of the SS 7 to the fourth input of the UVDP 1 and the clock signal generated in the UVDP 1. Thus formed a packet of information from the first output of the UVDP 1 is fed to the second input M 3.0.2, where the carrier frequency of the transmitter is modulated by the generated information packet. The received radio signal through A1 4 is radiated into space on the device under 2.

 The radio signal from the device under 2 is carried out with the help of receivers 8.1 and 8.2, simultaneously at two frequencies, corresponding to the codes of the current clock cycle of two SRPs set by GPSP3 5.0.1 and GPSP4 5.0.2 of GPSP unit 5. Reception at two frequencies is carried out in order to prevent information loss in case of erroneous reception of control information for controlling the choice of the carrier frequency of the transmitter of the device under 2. Using A2 10, the radio signal is received from the device under 2 and fed to the first inputs of inverter 8.1.3 and inverter 8.2.3 of receivers 8.1 and 8.2. The operation of the receivers is similar. Consider the principle of their action on the example of the first receiver 8.1.

 The frequency code of the current beat of the third SRP from the output of GPSP3 5.0.1 is fed to the input MF2 8.1.4. Frequency synthesizer SCH2 8.1.4 generates a frequency corresponding to the current clock code of the third SRP, synchronously with the formation of the carrier frequency of the transmitter of the device under 2.

 The generated frequency is fed to the second input of the inverter 8.1.3. The signal allocated at the intermediate frequency is amplified in UPCH1 8.1.2 and demodulated in D1 8.1.1.

 The demodulated signals from the outputs of both receivers are fed to the second and third inputs of the UVD 1. In the UVD 1, the transmitted information packet is allocated to the recipient address recorded in the service part of the packet, it is decoded, the service part is separated, and the received information block from the second output of the UVD 1 fed to the input of PI 12. From the service part, control information is allocated to control the selection of the carrier frequency of the transmitter of the device under 1, which from the third output of the DFT 1 goes to the third, control input K 2.0.3 and inhrosignal which the fourth output UFDP 1 is input to the BS 6. By analyzing the timing BS 6 synchronizes SS 7 and CST 5.0.1 and 5.0.2 with the transmitter portion of the device under operation 2.

 To control the choice of the carrier frequency of the transmitter of the device under 2 in the inventive device, an analysis of the interference situation at frequencies to which the receivers 8.1 and 8.2 will be tuned through x clocks in accordance with GPS codes 5.0.1 and GPS 5.0.0. An analysis of the interference environment is performed by the control receivers 9.1 and 9.2. Consider their work on the example of the control receiver 9.1.

 The frequency code of the subsequent (n + x) clock cycle of the third SRP from the output of GPSP3 5.0.1 is fed to the input of MF4 9.1.4. Frequency synthesizer СЧ4 9.1.4 generates the analyzed frequency corresponding to the code of the subsequent (n + x) measure of the third SRP.

 The frequency thus formed is fed to the second input of the inverter 3 9.1.3. At the first input of the inverter 3 9.1.3, the output A2 10 receives either noise, or in the case of interference at the analyzed frequency, a mixture of noise and noise. As a result of the conversion, the corresponding voltage at the intermediate frequency is released at the output of the inverter 3 9.1.3, which is then detected in AD1 9.1.2. By the magnitude of the voltage at the output of AD1 9.1.2 PU1 9.1.1 makes a conclusion about the presence or absence of interference at the analyzed frequency. Similar processes occur in the second control receiver 9.2 for the analyzed frequency, corresponding to the code of the subsequent (n + x) clock cycle of the fourth SRP specified by GPSSP4 5.0.2. The results of the analysis are fed, respectively, to the first and second inputs of SS 7. The comparison scheme works as follows. Let the memory bandwidth set by GPSP3 correspond to the working memory bandwidth of the unit GPSP 2 of the device under 2, and the memory bandwidth set by GPSP4 is the backup memory bandwidth. If there is interference at the analyzed frequency corresponding to the code of the subsequent (n + x) clock cycle of the operating memory bandwidth, and there is no interference at the analyzed frequency corresponding to the code of the subsequent (n + x) clock cycle of the reserve memory bandwidth, SS 7 generates control information for K 2.0.3 of the GPS block 2 devices under 2 for switching the memory bandwidth from the working to the backup one and feeds it to the fourth input of the UVDP 1 for transferring it to the device under 2 as part of the generated information package. In the absence of interference at the analyzed frequency corresponding to the code of the subsequent (n + x) clock of the operating frequency bandwidth, or there is interference at the analyzed frequencies corresponding to the codes of the subsequent (n + x) cycle of both frequency bandwidths, control information for switching the frequency bandwidth is not generated.

 Compared with the prototype, the use of the claimed device will improve the reliability of the received discrete information in duplex radio links with frequency hopping of any length.

Sources of information
1. Dickson R.K. Broadband systems. Per. from English - M .: Communication, 1979. -304 p.

 2. Gorshkov VV and other military communication systems using frequency hopping. Foreign electronics, 1986. 3, - p. 9-13.

 3. Klimenko N.N. VHF radio stations: state, development prospects, features of applying the frequency hopping mode. Foreign Radio Electronics, 1990, 7, - p. 3-20.

 4. Ribchester E. The Jaguar V Frequency - hopping radio. Electronics and Power, 1981, 27, 9, September, p. 627-629.

 5. IEEE Trans., 1988, COM-287. 9, p. 1561.

 6. Bulychev O.A., Kalinin V.M., Popov V.I. A method of transmitting information in a radio line with a pseudo-random tuning of operating frequencies and a device implementing it: US Pat. RF 2097923, MKI 6 H 04 V 1/74. Application 94024375/09 from 04/19/94, publ. 11/27/97. Bull. 33.

 7. Zhuravlev V.I. Search and synchronization in broadband systems. - M .: Radio and communications, 1986. -240 p.

 8. Microprocessors and microprocessor sets of integrated circuits: Reference: In 2 t. / N.N. Averyanov, A.I. Berezenko, Yu.I. Borschenko and others; Ed. V.A. Shakhnova. - M.: Radio and Communications, 1988, T. 2. - 368 p.

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Claims (1)

 A broadband transceiver device including first, second, third, fourth and fifth frequency synthesizers, a modulator, first and second antenna devices, a first pseudo-random sequence generator with a frequency code output of a current pseudo-random sequence, a second pseudo-random sequence generator with a frequency code output of a current pseudo-random sequence , switch, device for forming and decoding packets, first, second, third and fourth converters you, the first and second intermediate frequency amplifiers, the first and second demodulators, the first and second amplitude detectors, the first and second threshold devices, a comparison circuit, and the output of the information source is connected to the first input of the packet forming and decoding device, the first output of which is connected to the second input a modulator whose output is connected to the input of the first antenna device, the output of the first pseudo-random sequence generator is connected to the first input of the switch, the output of the second pseudo generator a random sequence is connected to the second input of the switch, the output of the switch is connected to the input of the first frequency synthesizer, the output of which is connected to the first input of the modulator, the output of the second antenna device is connected to the first inputs of the first, second, third and fourth frequency converters, the output of the second frequency synthesizer is connected to the second the input of the first frequency converter, the output of which is connected to the input of the first intermediate frequency amplifier, the output of the first intermediate frequency amplifier is connected to the input of the first demodulator, the output of which is connected to the second input of the packet forming and decoding device, the output of the third frequency synthesizer is connected to the second input of the second frequency converter, the output of which is connected to the input of the second intermediate frequency amplifier, the output of the second intermediate frequency amplifier is connected to the input of the second demodulator the output of which is connected to the third input of the packet forming and decoding device, the output of the fourth frequency synthesizer is connected to the second input of the fifth frequency converter, the output of which is connected to the input of the first amplitude detector, the output of which is connected to the input of the first threshold device, the output of the fifth frequency synthesizer is connected to the second input of the fourth frequency converter, the output of which is connected to the input of the second amplitude detector, the output of which is connected to the input of the second threshold devices, the outputs of the first and second threshold devices are connected respectively to the first and second inputs of the comparison circuit, the output of the comparison circuit is connected to the fourth input of the packet forming and decoding device, the second output of the packet forming and decoding device is connected to the input of the information receiver, characterized in that a third pseudo-random sequence generator is additionally introduced with the output of the frequency code of the current clock pseudo-random sequence, which is connected to the input of the second frequency synthesizer, and the output the frequency code of the subsequent beat of the pseudo-random sequence, which is connected to the input of the fourth frequency synthesizer, the generator torus of the fourth pseudo-random sequence with the output of the frequency code of the current clock pseudo-random sequence, which is connected to the input of the third frequency synthesizer, and the output of the frequency code of the next clock of the pseudo-random sequence, which is connected to the input of the fifth frequency synthesizer, the synchronization block, the output of which is connected to the inputs of the third and fourth generators pseudo-random sequences and the third input of the comparison circuit, in the device for forming and decoding packets introduced the third fourth outputs which are respectively connected to the third input of the switch and the input of the synchronization unit.