RU2191468C2 - Phase lock device - Google Patents

Abstract

FIELD: electronics, namely accurate tuning of controlled generator to outer signal frequency in condition of clock pulse skipping. SUBSTANCE: apparatus includes phase detector; digital-to-analog converter; voltage controlled generator; frequency divider; reversible module N counter; three switching units; OR-gate; parallel register and frequency comparator. EFFECT: accurate tuning of phase lock circuit to frequency of input signal in wide frequency range, improved response and operational stability of device. 5 dwg

Description

 The invention relates to electronics, in particular to phase-locked loop systems with digital detectors, is intended for fine tuning of a controlled oscillator to the frequency of an external signal under conditions of skipping clock pulses in a wide frequency range and can be used in instrumentation, television, and telecommunications.

 A device for phase locked loop (PLL) [1], which includes a phase detector based on a single vibrator, four keys and two D-flip-flops, a reversible counter, a digital-to-analog converter (DAC), a controlled generator and a frequency divider.

 In the specified device, fine tuning to a given frequency is ensured by the fact that the single-oscillator of the phase detector, which allows the input of signals to the trigger inputs, is triggered by the pulses of the input signal, so that the phase error when these pulses are missed is not calculated.

 However, such a device has a narrow frequency tuning range, since the pulse duration of the single-shot phase detector included in the phase detector should be equal to half the period of the input signal. In addition, the inclusion of an integral controller (counter) in the PLL circuit further narrows the frequency range in which the convergence of the tuning process is ensured.

 A PLL device [2] is also known, which includes a phase detector consisting of two counters and a D-flip-flop, two decoders, a reversible counter, a DAC and a controlled oscillator, and the detector operates in relay mode.

 The device provides fine tuning of the generator in conditions of skipped pulses of the input signal, since these pulses are clock for the phase detector and the reversible counter. In the absence of a signal at the input of the PLL circuit, the magnitude of the phase error recorded in the reverse counter does not change.

 However, such a device has a narrow operating range, since with a sharp change in the frequency of the input signal, the PLL can be tuned to frequencies that are multiples of a given one. In addition, the inclusion of an integral controller (counter) in the PLL circuit significantly degrades the dynamic characteristics of the device.

 The closest technical solution is the PLL device [3], which includes a phase detector, an averager, a digital PI controller, a DAC and a controlled oscillator, as well as a frequency error correction block when the averager overflows.

 The PLL under consideration provides accurate tuning of the generator in a wide range of frequencies, including when the input signal pulses are skipped, thanks to the use of an integral error correction unit.

 The disadvantage of this device is the exit of the system from the phase synchronization mode when the registers of the PI controller and the correction block are full. In addition, the introduction of an additional error correction loop degrades the dynamic characteristics of the PLL in the frequency capture mode.

 The technical result of the invention is to provide accurate tuning of the PLL to the frequency of the input signal, including when skipping part of its pulses, the ability to tune in a wide range of frequencies, as well as achieving high speed and stability of the system.

 To achieve a technical result, a PLL, consisting of a series-connected phase detector (PD), a DAC, a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider with a transmission coefficient of 1 / N, introduces a reversible counter (PC ) modulo N with the ability to set to a predetermined state, a parallel register, three key elements, an "OR" logic element and a frequency comparison unit (BSC).

 The first input of the LSC is connected to the input of the PLL circuit, the second input is connected to the output of the PM, and the output of the LSP is connected to the control inputs of the first and second key elements. Inputs PC +1 and -1 are connected to the PD error outputs, the PC clock input through the third key element is connected to the VCO output, the PC overflow output through the first and second key elements is connected to the control input of the third key element and the input of the OR element, the output of which connected to the PC installation input, to the data inputs of which a binary code of the number N / 2 (011 ... 1) is supplied. The PC data outputs are connected to the corresponding inputs of the register, the clock input of which is connected to the output of zeroing the PD and to the other input of the OR gate.

 Comparative analysis with the prototype showed that the proposed PLL device is characterized by the presence of a PC, a parallel register, a frequency comparison unit (BSC), an "OR" element, the first, second and third key elements, as well as functional relationships between them.

 The frequency comparison unit switches the PLL device operating modes depending on the magnitude of the frequency error. If this error does not exceed the set level, the device operates in phase synchronization mode, if it exceeds - in the frequency capture mode.

 The use of PC provides the conversion of a PWM phase error signal into a binary code by counting VCO pulses modulo N. The limits of code change from 00. ..0 to 11 ... 1 correspond to a change in phase error from - 2π to + 2π, a zero error code is 011 ..1. For phase errors exceeding 2π modulo, the code at the output of the counter depends on the operation mode of the PLL.

 In the phase synchronization mode, by connecting the overflow output of the PC with its installation input, an error code taken modulo 2π is generated through the first key element and the "OR" element.

 In the frequency capture mode, by connecting the overflow output of the PC through the second key element to the control input of the third key element, the maximum value of the error code is recorded.

 A parallel register connected to the PC data outputs provides storage of the phase error code during the period of conversion of the PD signal, and writing to the register is carried out by the PD reset pulse.

 Applications of PC and frequency comparison unit in PLL systems are well-known technical solutions. However, in this case, the introduction of new functional relationships, as well as the register allows you to process the phase error depending on the operating mode of the device. The calculation of the error modulo 2π in the phase synchronization mode makes it possible to avoid mixing the PLL tuning frequency when the input signal pulses are skipped. Fixing the maximum absolute value of the error value in the frequency capture mode allows accelerating the transient process in the PLL and avoiding tuning to multiple frequencies.

 Thus, the introduction of new connections and elements provides a significant increase in the accuracy and speed of the PLL device in comparison with analogs. Therefore, the noted differences of the proposed device from the prototype are significant.

 In FIG. 1, 2 and 3 are structural diagrams of a PLL device, a phase detector, and a frequency comparison unit, and FIGS. 4 and 5 are timing diagrams explaining the operation of the device in phase synchronization and frequency “capture” modes, respectively.

 The block diagram of the PLL device (Fig. 1) includes a digital PD 1, PC 2, key elements 3, 4 and 6, an OR element 5, parallel register 7, DAC 8, low-pass filter 9, VCO 10, a frequency divider 11, frequency comparison unit (BSC) 12.

The PLL input signal f _I and the feedback signal from the output of the PM 11 f _{os are} fed to the inputs of PD 1 and BSF 12, the output of PSB 12 is connected to the control inputs of elements 3 and 4. The lead outputs Q1 and lag Q2 of PD 1 are connected to the inputs +1 and -1 PC 2, respectively, and the zeroing output of PD 1 is connected to the input of the OR element 5 and the clock input of register 7. The binary code of the number N / 2 01 ... 1, the clock input, is fed to the data inputs D1 ... Dn PC 2 PC 2 through the key element 6 is connected to the output of the VCO 10, the overflow output PC 2 through the key element 4 is connected to the control input of the element 6 and through the key howl element 3 - the input of the element "OR", the output of which is connected to the input of the installation PC 2 V. The outputs Q1 ... Qn PC 2 are connected to the inputs D1 ... Dn of register 7, the clock input of which is connected to the output of zeroing PD 1 and other input element "OR". Digital code Q1 ... Qn register 7 outputs supplied to inputs D1 ... Dn 8 DAC, the output of which analog phase error signal through LPF 9 is supplied to the control input of the VCO 10. The output of VCO 10 is formed of PLL circuit output signal f _O coming through a frequency divider 11 to the feedback input of PD 1 and the frequency comparison unit 12.

Phase detector 1 can be implemented on the basis of two D-flip-flops 13, 14 and the element "And" 15 (figure 2). The signals f _I and f _OS arrive at the clock inputs of the triggers, the data inputs of which are supplied with logical "1". The outputs Q1 and Q2 of the triggers 13 and 14 are connected to the inputs of the element "And" 15, the output of which is formed the reset signal RST, which is fed to the reset inputs of the triggers R.

The frequency comparison unit can be implemented on the basis of the counter 16, PC 19, two elements "NOT-AND" 17 and 18, D-trigger 20 (figure 3). The input signal f _in goes to the clock input of the counter 16 and to the input of the element "NAND" 17, and the feedback signal f _oc to the input of another element "NAND" 18. The overflow output of the counter 16 is connected to its reset input, input PC 19 and the clock input of the D-flip-flop 20. The overflow output of the PC 19 is connected to the inverting inputs of the NAND elements 17, 18 and the data input of the D-flip-flop 20, the code 011 ... 1 is supplied to the data inputs of the PC 19.

In phase synchronization mode, the PLL operates as follows. The inputs of the PD 1 receive a sequence of pulses f _I and f _OS (Fig. 4 a, b), as a result, the PWM phase error signals are generated at the outputs Q1 and Q2. The phase error signals are fed to the inputs +1 and -1 of PC 2 and converted into a digital code by counting the pulses of the VCO 11 modulo N (Fig. 4 c). At the end of the period of the PWM signal at the output of PD 1, a zeroing pulse occurs (Fig. 4 e), according to which the error code is entered in register 7, and PC 2 is set to the initial state 01 .... 1.

 When PC 2 enters the state 00 ... 0 or 11 ... 1, an overflow signal is generated, which passes through the key element 3 and the "OR" element 5 to the input of the V installation, and the code 01 ... 1 is entered into the counter. Thus, at the output of PC 2, a phase error code taken modulo 2π is generated and entered into the register. This code is then converted by the DAC 8 to an analog error signal (Fig. 4 e), which is fed through the low-pass filter 9 to the input of the VCO 10. This conversion of the error signal prevents the PLL tuning frequency from shifting when the input signal pulses are skipped.

 In the "capture" frequency, the conversion of the phase error signal PD 1 into a digital code is carried out, as in the previous case, using PC 2 (Fig. 5 a-c). However, when PC 2 overflows, the signal from its output through the key element 4 goes to the control input of the key element 6, blocking the passage of pulses of the VCO 10 to the clock input of PC 2. As a result, the maximum value of the error code is recorded by PC 2 and then written to register 7. This ensures optimal performance, and also prevents tuning of the PLL to multiple frequencies.

The switching modes of the PLL device is performed by the BCCH 12, while the PC block 19 calculates the error in frequency as the difference between the number of pulses f _I and f _OS in the time interval specified by the counter 16 (figure 3). If the difference obtained does not exceed the specified level, the device operates in phase synchronization mode, if it exceeds - in the frequency capture mode. In the first mode, the signal BSCH 12 closes the key 3, allowing the passage of the signal overflow PC 2 to the input of the element "OR". In the second mode, the key 4 is closed, allowing the passage of the overflow signal PC 2 to the control input of the key element 6.

 Thus, the proposed PLL device provides, in comparison with the prototype, a higher frequency tuning accuracy, including when the input signal pulses are skipped, and high speed when processing frequency errors.

Sources of information
1. Pulsed phase locked loop systems. / B.V. Grigoriev, V.N. Drozdov, Yu.A. Sabinin et al. - L.: Energoatomizdat, 1982. - 88 p., Ill.

 2. AC 1781820 / MKI 5 H 03 L 7/06 / Zilberg E.V. A phase locked loop. / "BI", 1992 - 46, p. 210.

 3. AC 1739487 / MKI 5 N 03 K 7/00. / Vorobiev A.S. Device for phase locked loop / "BI", 1992 - 21, p. 218.

Claims (1)

 A phase-locked loop device consisting of a phase detector (PD) and a series-connected digital-to-analog converter (DAC), a low-pass filter, a voltage controlled oscillator (VCO) and a frequency divider, with one PD input being the input of the device and the other connected to the output of the divider frequency, characterized in that a reverse counter with an account module N (PC), first, second and third key elements, an OR logic element, a parallel register and a frequency comparison unit are introduced into it, with inputs +1 and -1 PC s are identical with the corresponding outputs of the phase error of the PD, the clock input of the RS through the third key element is connected to the output of the VCO, the overflow output of the RS through the first key element is connected to the input of the OR element and through the second key element to the control input of the third key element, the output of the OR element is connected to PC installation input, to the data inputs of which a binary code of the number N / 2 is supplied, PC data outputs are connected to the corresponding inputs of the parallel register, the clock input of which is connected to the output of zeroing the PD and to other input OR gate, the outputs of these parallel registers connected to respective inputs of the DAC, the first input frequency comparison unit connected to the input device, the second input - to the output of the frequency divider, the output frequency of the comparator is connected to control inputs of the first and second key elements.

Images