RU2188451C2 - Mutual resource allocation system - Google Patents

Abstract

FIELD: information science and computer engineering. SUBSTANCE: resource allocation system hardware used for mutual memory allocation in computer systems includes control unit, first, second, and n-th confined centers, and data transmission bus. EFFECT: enlarged functional capabilities. 8 dwg

Description

 The invention relates to technical means of computer science and computer technology and can be used to solve problems of resource allocation in the economy, memory allocation in computers, computer complexes, in local and global computer networks.

 The well-known "Exchange Controller" (patent N 2032214, 1993, Bull. N9), which allows for the exchange of information between blocks.

 Also known is the "Method of summing numbers" (patent N 2145113, 1998, Bull. N3), which allows the summation of numbers.

 As a prototype, “Device for distributing tasks among processors” (patent N 2017206, 1994, Bull. N14) was selected, which allows automatic conversion of logical addresses of processors into physical ones in multitask mode and processing of arising failures.

The task was as follows:
1) expand the functionality of the system;
2) simplify the control unit algorithm;
3) expand the range of tasks.

 The proposed resource sharing system allows you to significantly expand the functionality, simplify the algorithm of the device, expand the range of tasks, including the tasks of balancing the interaction of executive subsystems in economic and technical systems.

 The solution to the problem is that the resource allocation system containing the control unit is characterized in that it additionally introduces: 1st, 2nd and nth localized centers, data transmission line, the first information output of the control unit being connected to the second information input localized center LC1, the first information input of which is connected to the first information output of the data transmission line, the second information output of which is connected to the first information input of the localized cent RA LC2, the information output of which is connected to the second information input of the data transmission line, the nth information output of which is connected to the first information input of the localized data center, the information output of which is connected to the nth information input of the data transmission line, the first information input of which is connected to information output of the first localized center LC1, the second information input of the localized center LC2 is connected to the second information output of the control unit, the third information whose output is connected to the second information input of the nth localized center of the LC, the first and second control inputs "START" and "RESET" of the control unit are external inputs of the device.

 LC1, LC2, ..., LCn - blocks are used to form an excess resource, which must be distributed among the associative storage devices (AZU) of other blocks, as well as to obtain storage and analysis of a certain amount of resource (product) received from other blocks.

 The data transmission line serves to form a channel for transferring resources between localized centers.

 BU - the unit is used to control the device.

The theoretical platform of this invention is the structural and functional direction of modern systems theory. In the case under consideration, a system is understood to mean many local subsystems (vertices of the graph) and exchange flows (arcs of the graph) or the results of the functioning of these structural components. We define the rate of interaction and functioning of structural components, which we agree to call localized centers (LCs). Each localized center will be presented in the form of a black box with many inputs with power P and many outputs with power S. For each input, we determine the deficit of the corresponding material or information flow, and for each output, the rate of formation of material or information resources of a given localized node. The system of localized nodes functions optimally when the following function is minimized under given constraints:
MINi ≤ Xj, (1)
where MINi is the volume of the resource;
Xj - the amount of "free space" in the localized center;
i - 1, 2, ..., N is the number of random-access memory devices in a localized center (LC);
j - 1, 2, ..., T is the number of associative storage devices in a localized center (LC).

 A binary code that corresponds to the amount of excess resource is pre-recorded in the random-access memory of each LC. Information in the form of a binary code corresponding to the presence of the amount of "free" space is also preliminarily recorded in the associative memory device of the LC. The task of the interchange system is to find a place in the control system of the excess resource system and transfer it for further analysis. If the amount of excess resource is greater than the availability of free space, then the redistribution of the resource does not occur. The process of transferring excess to free space will be possible when condition (1) is satisfied, i.e. the amount of excess resource is equal to or less than the provided amount of "free" space.

 Thus, the purpose of the resource sharing system should provide such a regime for managing material flows or information that ensures optimal balanced functioning of the system of interacting localized nodes (SVLU).

When considering SVLU, it is necessary to solve one of the main problems in the distribution of resources (products) between localized centers (LC). Consider one localized center (LC) separately. LC produces some products (agricultural, industrial, mining, processing, etc.). We introduce the notation PC1, PC2, PC3, ..., PCn. This LC has places for storing these or other resources (products), denoted as CM1, CM2, CM3, ..., CMt. A situation is possible when this LC does not have enough “free” space to store resources (products), i.e. there is a relation
XzPCi> УhCMt, (2)
where X is the amount of excess resource;
Y is a quantitative expression of the amount of free space;
z is the sequence number of the excess resource;
h - serial number of free space.

Над чертой (в числителе) перечисляются, через знак #, все продукты (ресурсы) находящиеся в избытке, а также указано их количество. Под чертой (в знаменателе) перечисляется наличие свободного места в ЛЦ. Определено наличие свободного места и указан его порядковый номер. Такую запись будем называть избыток - свободное место. Представим систему состоящую из 4 локализованных центров. Введем некоторые обозначения и ограничения: каждый локализованный центр (ЛЦ) должен иметь порядковый номер - натуральное число, все продукты (ресурсы) будем считать дискретными, т.е. их количества измеряются натуральными числами, ресурсы (продукты), записанные в числителе одного локализованного центра (избыток), не должны быть записаны в знаменателе (свободное место).We write this situation with products (resources) as follows:

Above the line (in the numerator) are listed, through the # sign, all products (resources) that are in excess, and their quantity is also indicated. Under the line (in the denominator) is listed the availability of free space in the LC. The availability of free space is determined and its serial number is indicated. We will call such a record excess - free space. Imagine a system consisting of 4 localized centers. We introduce some notation and restrictions: each localized center (LC) must have a serial number - a natural number, we will consider all products (resources) to be discrete, i.e. their quantities are measured in natural numbers, resources (products) recorded in the numerator of one localized center (excess) should not be recorded in the denominator (free space).

 Suppose a system consists of 5 localized centers. The number of products (resources) is calculated by the number 10. Let us write down each localized center in terms of the situation, excess - free space indicating the amount of the resource and the amount of free space.

При этой записи происходит однозначное определение избытка ресурса каждого ЛЦ и "свободного" места соответственно.

With this record, an unambiguous determination of the excess resource of each LC and "free" space, respectively, occurs.

 The solution is illustrated by a diagram (see the end of the description), which clearly illustrates the algorithm of the resource allocation system. We write out all the “free” places from the second to the fifth localized center of the LC in a row. The first redundant resource PC1 of the 1st localized center is selected, then the quantitative equivalent of this resource is compared with all the "free" places of the remaining localized centers. In the associative storage device, several types of comparisons are carried out: determining the maximum number, the minimum, the comparison for equality, for more or equal. It is advisable to choose the first comparison mode as an equality search. If equality is established, then the excess PC resource is transferred to the "free" place in the RAM of another localized center. If a negative comparison result is obtained, then the system AZUs perform a comparison operation to the nearest larger value. If a positive comparison result is obtained, then on the adder-subtractor is the difference between the amount of excess resource and the amount of "free" space. In the same AZU, where a positive comparison result is established, the excess resource is recorded and the difference obtained is recorded at a different address. The process of comparison and redistribution continues until all excess resources of all localized centers are reviewed and all possible options for efficient redistribution of resources are identified. If there is no positive result of the comparison in either the first case or the second case, then the excess resource will remain in the same place, redistribution in this case is not performed.

 After all redundant resources of all localized centers are redistributed, new binary information will be written to the system's AZU. In the system analysis unit, it is processed by an arithmetic processor or specialized symbol processing devices.

 In FIG. 1 shows a block diagram of a resource sharing system.

 Figure 2 presents a variant of the technical implementation of the localized center LC1.

 In FIG. Figure 3 presents a technical implementation option for the BP1 memory block - determining the excess resource in the RAM of the block, as well as for storing the resource in the RAM of the block of the localized center.

 Figure 4 presents the structure of the control signal SUP1. This information signal consists of six parts. Each component is also an information signal.

 In FIG. 5, an embodiment of the technical implementation of the blocks is presented: initial installation and formation of addresses for recording information in RAM of the memory block — BNUA1, determining the address for reading and writing to the RAM the received information — BPU1.

 Figure 6 presents the functional diagram of the analysis unit BAN1.

 Figure 7 - substantive GAW device operation.

 On Fig - labeled GAW device operation.

 The resource sharing system (FIG. 1) contains a localized center 1 of LC1, a localized center 2 of LC2, a localized center of 3 LCn, a data transmission line 4, and a control unit 5.

 To describe the operation algorithm of control unit 5, the following identifiers are used.

 List of identifiers.

 1. LC1 is the first localized center.

 2. LC2 is the second localized center.

 3. LCn is an n-localized center.

 4. The data transmission line.

 5. BU - control unit.

 6. ВХ1 - the first information signal.

 7. ВХ2 - the second information signal.

 8. BXn is the nth information signal.

 9. OUT1 - the first output information signal.

 10. OUT2 - the second output information signal.

 11. EXIT n is the nth output information signal.

 12. SUP1 - the first control signal.

 13. SUP2 - the second control signal.

 14. SUPn - n-th control signal.

 15. BXi is the i-th input information signal.

 16. KL1 - the first electronic key.

 17. VHDi - the first information output (output from an electronic key).

 18. SNU1 - the first information signal of the initial installation of the first memory block.

 19. BP1 - the first block of memory.

 20. CC1 - comparison signal (matches or greater than or equal to the BP1 block).

 21. PP1 - information output of the memory block BP1.

 22. SUM-VYCH1 - the first adder-subtractor of the block LC1.

 23. RZ1 - the result of the difference between the i-output information signal VHDi and the information output of the memory unit BP1 PP1.

 24. BNUA - unit for the initial installation and formation of the addresses of rows and columns of RAM memory.

 25. LSA1 - the first information signal of the initial installation and formation of addresses of the BNUA1 block.

 26. RAM - random access memory.

 27. С / З1 - write / read signals.

 28. BK1 - signal chip selection.

 29. SD - data bus of RAM unit BP1.

 30. SHAS - bus address lines of RAM block BP1.

 31. SHAST - bus address of the columns of RAM block BP1.

 32. СУО1 - the first information signal for selecting a chip and reading / writing RAM.

 33. BPU - the block of the initial installation and formation of addresses of rows and columns of the associative storage device of the memory of the memory unit BP1.

 34. SNU1 - information signal for resetting the counters and rectangular pulses of the BPU1 block.

 35. INU - the output information signal of the control unit, consisting of the address bus and data bus.

 36. OR - a logical element OR.

 37. RZ1 - the result of the difference received from the output of the adder-subtractor block LC1.

 38. VIR - output information from the output of the logical element OR.

 39. AZU - associative storage device of the memory unit BP1.

 40. SUA1 - an information signal for masking and controlling the recording and reading of information from AZU.

 41. UPA1 - information signal for controlling the operation of the arithmetic processor ARLP1 analysis unit BAN1.

 42. UPS1 - information signal for controlling the operation of specialized symbol processing devices PRSO1 of the analysis unit BAN1.

 43. SCHUD - binary counter forming the data bus of the BNUA1 block.

 44. TI1 - clock pulses of the SCHUD counter.

 45. УО1 - signal for resetting the СЧУД counter.

 46. SHD1 - data bus, the output signal of the SCHUD counter.

 47. SChSL - a binary counter that generates address lines of RAM block BNUA1.

 48. GI1 - pulse generator of the SChSL counter.

 49. SB1 - signal zeroing counter SCSL.

 50. AST1 - addresses of the RAM lines of the memory block BP1.

 51. SChST - binary counter, forming the addresses of the columns of RAM block BNUA1.

 52. GIM1 - rectangular pulses of the counter SChST.

 53. СРС1 - signal for resetting the counter СЧСТ.

 54. ASTl1 — addresses of RAM columns of the BP1 memory block.

 55. СЧД - a binary counter that forms the data bus of the AZU of the BP1 memory block.

 56. PI1 - rectangular pulses of the counter SCH.

 57. SBO1 - signal zeroing binary counter account.

 58. SDA1 - data bus of the memory block BP1.

 59. SCA - a binary counter that forms the addresses of the RAM of the BP1 memory block.

 60. PIM1 - rectangular pulses of the ACh counter.

 61. SBR1 - signal reset the binary counter NAV.

 62. ШАА1 - address bus of the memory of the BP1 memory block.

 63. ARLP1 - arithmetic processor of the analysis unit BAN1.

 64. PRSO1 - specialized character processing devices.

 65. ARL1 - the output of the arithmetic processor ARLP1.

 66. SIM1 - output of specialized symbol processing devices PRСО1.

 67. Standard output device.

 68. RES1 - the final result of processing the analysis unit BAN1.

 69. PR - a sign of exit from the cycle when loading all storage devices of the system.

 70. APR - a sign of the arithmetic processor.

 71. RAV - comparison of data in the RAM for equality.

 72. W / R - read / write signal of the memory of the BP1 memory block.

 73. M0 - the 0-th input signal of the mask in the RAM of the memory block.

 74. M1 - the first input signal of the mask in the RAM of the memory block.

 75. M2 - the 2nd input signal of the mask in the RAM of the memory block.

 76. M3 - the 3rd input signal of the mask in the RAM of the memory block.

 77. N - a finite number of random-access memory devices in the system.

 78. T - a finite number of associative storage devices in the system.

 79. i - counter of the current value of the number of random-access memory devices in the system.

 80. j - counter of the current value of the number of associative storage devices in the system.

 The work of the resource allocation system algorithm.

 Content GAW control is shown in Fig.7 and reflects the operation of the control unit (Fig.1).

 The signals UOO and RESET: = 1 (blocks 2 and 3 of the algorithm circuit) (Fig. 1), all elements of the device memory are set to zero.

 In block 4 of the algorithm, the START signal is analyzed. On this command, the work of the entire resource sharing system begins.

 In block 5 of the algorithm, the counters i and j are pre-set to the state unit i: = 1, j: = 1. The value of counter i changes from one to the value N and means the number of all random-access memory devices of the system. The value of the counter j varies from unity to the value of T and means the number of all associative storage devices of the system. According to the signals UO: = 1, SB: = 1, SBS: = 1, SBO: = 1, SBR: = 1, all elements of the system memory are reset. The counters of the BNUA1 and BPU1 blocks are reset to zero.

 In blocks 6-10 of the algorithm diagram, a cycle is presented in which information is preliminarily recorded in all random access memory (RAM) and associative memory devices (RAM) of the system.

 In block 6 of the algorithm, the PR attribute is analyzed - all storage devices are loaded or not. If PR takes the value NO, then there is a transition to block 11 of the algorithm and the system begins to work on the allocation of resources. If PR is YES, then the load cycle is not yet completed and the resource values are pre-recorded in RAM and system RAM. The condition PR should be understood as the result of a logical function (i ≤ N and j ≤ T). The exit from the cycle is carried out when all the storage devices of the system are loaded with preliminary (initial) information.

 In block 7 of the algorithm, the signals of rectangular pulses are sent to the inputs of the counters SchUD, SchChL, SchchST, SchCh, SchA of the BNUA1 and BPU1 counters. Binary counters count the number of these pulses: ТИi: = 1; PI i: = 1; GIi: = 1; PIMi: = 1; GIMi: = 1.

 In block 8 of the algorithm, information is recorded in the random access memory (RAM). When applying signals to enable inputs, the zero value VKi: = 0; C / Zi: = 0 there is a permission to write information in RAM. On the input bus of RAM i receives the information signal ШД (data bus) RAM i: = ШД. The address inputs of RAM i are the addresses of rows and columns: RAM i: = SHAS; RAMi: = CHAST.

 In block 9 of the algorithm, recording is allowed and information is recorded in associative storage devices of the system. By the signal WRj: = 0, information is recorded in the AZUj. By the commands: АЗУj: = ШДАj, АЗУj: = ШAAj, АЗУj: = CУAj, the corresponding information: data, addresses and mask signal is supplied to the data bus, address inputs and mask inputs.

 In block 10, the counters i and j change their value by one: i: = i + 1, j: = j + 1. In this case, a transition to block 6 of the algorithm is performed.

 In block 11 of the algorithm, the counters i and j take unit values: i: = 1, j: = 1.

 Blocks 12-22 represent the process of redistributing resources between localized LC centers. Information is read from RAM i and written to the corresponding RAM j systems.

 In block 12 of the algorithm, the sign of PR is analyzed - exit from the cycle. Upon the output NO, there is a transition to block 23 of the algorithm. In this case, all random access memory (RAM) and associative memory devices (RAM) of the system are viewed. YES means that the redistribution of resources between localized centers continues. The sign of exit from the cycle should be understood as the result of a logical conjunction operation PR = (i ≤ N and j ≤ T).

 In block 13 of the algorithm, enabling signals for reading information from the system RAM are supplied to the inputs of the RAM: the read / write signal takes a value of C / Zi: = 1, and the chip selection signal is zero VKi: = 0.

 In block 14 of the algorithm for the commands: RAM i: = SHAS, RAM i: = SHAST, MAG: = EXIT i the addresses of the rows and column addresses from the BNUA block are fed to the inputs of the RAM devices, and also the data transmission line takes the value of the output data from the RAM of the system . The process of reading information from random-access memory devices.

 In block 15 of the algorithm, according to the commands WRj: = 0, АЗУj: = BXi, the authorization signals are fed to write information to the associative storage devices (АЗУ) of the system and the data received on the input bus АЗУj is recorded.

 In block 16 of the algorithm, the analysis of the comparison signal CC. If the comparison signal SS is equal to one, then the transition to block 18 of the algorithm occurs, the system has a match for equality or greater than or equal. If the SS is zero, then this means that a match for equality or for more or equal did not happen.

 In block 17 of the algorithm, by the command j: = j + 1, the counter j — the number of associative storage devices of the system — is increased by one, i.e. transition to the next AZU. According to the algorithm, the transition to block 12.

 In block 18 of the algorithm, the RAV condition is analyzed for equality or for more than or equal to the input data of RAM i and the contents of RAM j. The condition RAV is analyzed only when there is a match for equality or greater than or equal to, the signal SS block 18 of the algorithm is equal to only one. If there was a comparison for equality, the attribute RAB corresponds to the output YES, then the transition to block 21 of the algorithm is carried out. If there was a comparison of more or equal to the data - the output of the conditional vertex 18 is NO, then the transition will be carried out to block 19 of the algorithm.

 In block 19 of the algorithm, according to the command PЗj: = BXДi-PPj, the difference between the input signal VCD i and the contents of the cell АЗУj - information signal PPj is determined. Such an operation is performed in the case of comparing the data by more than or equal to in RAM j, with PPj ≥ BXДi. According to the algorithm of the system, the input information of the input-output device is recorded at the set address, and the resulting difference PЗj is recorded in the same AZUj, but at a different address.

 In block 20 of the algorithm according to the commands: WR: = 0, АЗУj: = ВДДi, АЗУj: = РЗj, permission is made to write information to the АЗУj by applying zero to the input WR, and the input information of the ВДДi and the received difference PЗj in the АЗУj are also recorded. When this is a transition to block 22 of the algorithm.

 In block 21 of the algorithm, according to the WR: = 0 and АЗУj: = BXi commands, permission to write information to the АЗУj occurs, and the input data ВХi are written to the associative storage device (АЗУj) at the set address.

 In block 22 of the algorithm, the counters i and j increase by one: i: = i + 1; j: = j + 1. Thus, the information of the next random access memory and the associative memory device of the system is read. According to the algorithm, the transition to block 12.

 In block 23 of the algorithm, the counter of the number of associative storage devices j is set to the initial state - unit j: = 1.

 In blocks 24-29 of the algorithm, a cycle is organized in which the process of analysis of the redistributed information of the system is carried out. Information is read from associative storage devices (AZU) and processed in the block BAN analysis (6) of the system.

 In block 24, the current value of counter j is compared with the final value of the number of associative storage devices of the system - T. If j> T, then the algorithm proceeds to block 30. This condition is the end of the loop. If j ≤ T, then the information processing process continues with the blocks of the system analysis. This condition is for continuing the work of the cycle and means that not all information from the AZU is processed.

 In block 25 of the algorithm, information is read from the associative storage devices of the system for further processing in the analysis blocks. According to the commands: ПММj: = 1, АЗУj: = ШAAj, rectangular pulses are fed to the counter СчAj of the BPUj block (Fig. 5). At the output of the binary counter, the addresses ШAAj of associative storage devices (АЗУ) are formed. This address reads information from the system AZUj. By the commands WR: = 1, BAHj: = PPj, an enabling signal is supplied for reading information from the RAM and j is transmitted to the analysis block BAHj for further processing (Fig. 6).

 In block 26 of the algorithm, the analysis of the sign of the ARP. This feature corresponds to the operation of the arithmetic processors APLPj or the information from the AZUj is analyzed by the symbol processing processors PPCOj of the analysis unit BAHj (Fig. 6). If the output of this block corresponds to the statement YES, then the output from the AZUj is processed by the arithmetic processor APLPj. If the output matches NO, then the data is processed by the character processor PPCOj.

 In block 27 of the algorithm, control signals are supplied to the input of the arithmetic processor APLPj by the command APLPj: = UPAj from the control unit. At the command APLPj: = PPj, an information signal is input to the arithmetic processor for further processing.

 In block 28 of the algorithm, control signals are supplied to the input of the symbol processing processor PPCOj by the command PPCOj: = UPCj. By the command PPCOj: = PPj, information from the associative storage devices АЗУj of the memory block BPj is supplied to the input of the symbol processor.

 In block 29 of the algorithm, counter j changes its value by one by the command j: = j + 1. In this case, a transition to block 24 of the algorithm is performed.

 Block 30 of the algorithm corresponds to the final vertex of the block diagram of the algorithm.

 The operation of the device search entries is as follows.

 External control signals "Start" and "Reset" are received in the control unit 5. The operation of the system is as follows.

 Each localized center (LC) at the first stage of the system should determine its resources (products). Determine what resources will be in excess and in what quantity. The binary equivalent of the amount of excess resource will be pre-recorded in the random-access memory of each localized center. Each center also forms volumes of "free" seats. This information is recorded in the form of binary code in the associative storage device of each LC.

 The resource sharing system can operate in two modes: priority and priority. Priority-free operation of the system is carried out according to the next order of reallocation of resources. This mode is characterized in that the process of reading and comparing the binary equivalent of the amount of excess product (resource) from the RAM of the localized center will take place from the 1st to the nth in the next order. First, there is a redistribution of resources of the 1st center, then the 2nd, etc. until the last.

 The second mode is determined by priority reading and comparing resources from RAM of localized centers. The control unit can generate control signals for the choice of microcircuit and read / write RAM RAM of the system in priority order. First with highest priority, then descending. Note that the second resource is read first from the 1st RAM of the 1st LC. Then the 3rd resource from the 2nd RAM of the 3rd LC, etc. This is an example of the priority reallocation of resources of the presented system. The operating modes of the system are formed in the control unit. The synthesis of the combination scheme of the priority decoder is not difficult [6, 7].

The localized center LC1 consists (figure 2) of an electronic key, a memory unit and an adder-subtractor. Figure 2 shows the structure of the first localized center LC1. All localized centers of the system consist of the same type of blocks that perform the same functions. At the input of the memory unit BP1 receives an input signal (binary code of the excess resource) - BXi. At the same time, this signal is fed to the input of the electronic key KL1. The other inputs of the PSU memory block receive information inputs from the control unit: SUA1 — information signal for masking and controlling the recording and reading of information from the control system, SNU1 — information signal for resetting the counters and rectangular pulses of the preset BPU1, SUO1 — information signal for selecting the chip and reading / entries from RAM, LSA1 - information signal of the initial installation and formation of addresses of the block BNUA1 of the initial installation and addresses. In the memory unit BP1, a comparison is first made on the equality of the input signal BXi with pre-installed information in the memory of the localized centers of the system. If the comparison result is positive, then the input information is recorded in the memory of this localized center. If the comparison result is negative, then the comparison mode is set in all the system memory for the near future. If the comparison result is positive, then the output signal CCi - comparison is set to the unit of the i-th memory of the j-th localized center. This means that there is more “free” space than is required for the allocation of the excess resource. The electronic key KLi is opened and the input signal VHDi is fed to the input of the adder-subtractor. At the second input of the adder-subtractor comes the binary code PP from the RAM of the memory block BPi (figure 2). Moreover, the following inequality holds:
PP> Bxi. (9)
At the output of the SUM-VITi adder-subtractor, the difference PЗj is formed between the input signals: PPj and BXi. The input information BXi and the resulting difference PЗj are recorded at the corresponding addresses in the АЗУj upon the arrival of a signal from the control unit СУAj of this localized LC center (Fig. 2). If the comparison result is negative, then this means that there is less "free" space than necessary, and the resource is not redistributed in this case. According to the algorithm of the system, reads from the i-th RAM at the next address of the next binary code equivalent to the excess resource.

 The memory block BP1 (Fig. 3) consists of RAM memory, associative memory of the RAM, the block of the BNUA of the initial installation and formation of addresses of rows and columns of the RAM memory of the RAM, the control unit is the block of the initial installation and generation of addresses of rows and columns of associative -memory storage device, logic circuit OR. Before the reallocation of resources, i.e., the main system operation, preliminary information is recorded in RAM and in the RAM. In RAM, information about the excess of the resource (product) is entered. The binary code corresponding to the amount of "free" space in the localized center of the LC is written to the RAM. Upon arrival from the control unit of the information signal LSA1 - the signal of the initial installation and formation of addresses (Fig. 3), at the beginning, the counters forming the addresses for writing information to RAM are reset. The counters of the unit BNUA1: SCHUD1, SChSL2, SChST3 (figure 5) are set to zero. Upon the arrival of signals from the control unit: TI1, GI1, GIM1 of the BNUA1 block, the data bus ШД, the addresses of the RAC lines, as well as the addresses of the columns of the RAC, which are received at the RAM input of the memory unit BP1, are formed at the inputs of the counters СЧУД1, СчСЛ2, СчСТ3. At the addresses of rows and columns, data is recorded in the random access memory of the memory unit. These data correspond to information about the excess resource of a particular localized center of the LC. Writing to RAM occurs when the VC chip selection signals are set to zero, as well as the read / write signal C / Z is equal to zero [5]. Upon the arrival of the information signal SNU1 - zeroing the counters and presetting - at the input of the control unit (Fig. 3), the counters are first reset to zero: RMS and RMS signals SBO1 and SBR1 (figure 5). Then, rectangular pulses PI1 and PIM1 arrive at the input of the above counters, forming a data bus SHDA1 and an address bus ШАА1. The outputs of the counters SCH and SCh of the BPU1 preset block are input to the OR logic circuit (Fig. 3). The output of the logic circuit OR - VIR is fed to the input of the associative storage device of the RAM and is recorded. This is a preliminary stage of the system’s operation, in which binary information is recorded in the automatic data storage system, corresponding to the “free” places in the LC. In other words, it can be said this way: zeroing and recording the corresponding information in the memory elements of the localized centers of the system.

 The next stage of the system’s work is to read information from the RAM of one localized center and compare it with the binary code of the RAM of other LC systems. At the set SHAS and SHAST addresses of the BNUA block and the corresponding VK chip selection signals, equal to zero, and read / write (S / W) equal to the unit selected for RAM operation, information is read from the memory. At the output of RAM, an output information signal OUT1 is generated, which corresponds to an excess of resource (Fig. 3). This signal is fed to the input of the data transmission line (figure 1). Through the trunk, this information goes to the inputs of the memory blocks of other localized centers. Input information ВХi goes to the input of the logic element OR of the memory block of the LC. From the output of the OR circuit, the binary code is fed to the input of the associative storage device of the RAM (Fig. 3). In the system's AZU, the incoming information is compared with the binary code previously recorded in the memory cells. If a comparison for equality is established, then this AZU cell is blocked and is not involved in the further process of reallocation of resources. Information from RAM to the RAM of another LC is not overwritten, because she is the same. If there is no comparison for equality, then the search mode for the nearest larger value is performed. This mode is formed using the information signal SUA1, received at the input of the AZU from the control unit. With a positive result, a comparison signal CC1 equal to one is formed at the output of the AZU. The resulting difference from the output of the adder-subtractor РЗ1 is recorded at a different address in the same AZU, with the further process of comparison, the data of this cell is involved.

 In FIG. 1, the inputs of the localized centers of the LCs come from the control unit by only one information signal СУпn - the control signal. Multiple signal flow between blocks makes reading drawings difficult. In this regard, figure 4 shows the structure of the control signal SUP1 (number 1 taken all the blocks and signals for example). The structure of this information signal also includes information signals: LSA1 - signals for zeroing and generating data and addresses of the initial installation unit BNUA1, SNU1 - signals for zeroing and generating data and addresses for the block BPU1 for preliminary installation, SUA1 - mask signals for associative storage devices, SUO1 - signals chip selection and reading / writing, UPA1 - control of the arithmetic processor, UPS1 - control of the operation of specialized devices of symbolic information. The main task of information signals is the implementation of communications between blocks and reliable transmission of binary code between the control unit and other devices of the system.

 Block BNUA1 - initial installation and generation of addresses of rows and columns of RAM memory consists of binary counters: SCHUD - data settings, SChSL - column address shaper, SChST - line address shaper (Fig. 5). The inputs of the binary counters receive signals from the control unit - set to zero: UO1 - reset the counter SChUD, SB1 - reset the SCHL counter, SBS1 - reset the SCHT counter (Fig. 5). Before loading memory elements, all counters must be reset to zero. Upon arrival of rectangular pulse signals: TI1 - clock pulses, GI1 - pulse generator, GIM1 - rectangular signal generator to the inputs of the corresponding binary counters, the data bus ШД1 is formed from the output of the SChUD counter, the addresses of the AST1 lines from the output of the SChSL counter and the addresses of the ASTl columns from the output of the counter CST (Fig. 5). All output signals of binary counters are fed to the inputs of random-access memory devices (figure 3).

 BPU1 - unit for the initial installation and generation of addresses of rows and columns of the associative memory device of the memory of the BP1 memory block consists of binary counters: СЧД - data counter ШДА1 and СЧА - address counter ШАА1 (Fig. 5). The inputs of the counters receive the signals SBO1 - reset to zero and SBR1 - zero, which set these devices to zero. Upon arrival of the signals PI1 - rectangular pulses and PIM1 - clock rectangular pulses - the inputs of the counters are formed at their outputs: data bus SDA1 of the SCh counter, address bus SHAA1 of the SCh counter (Fig. 5). The output signals of binary counters are fed to the input of the OR logic circuit, the output of which is the data input and address input of the associative storage devices (AZU) of the system.

 The analysis unit BAN1 consists of an arithmetic processor ARLP1, a specialized information processing device PRSO1 and a standard output device. The main task of this unit is to analyze the PP1 information received at the input from the associative storage device (AZU) of the localized LC center. The ARLP1 arithmetic processor is designed to perform all arithmetic operations with PP1 input data. It can be a universal processor, as well as a number of specialized solving devices. The input of this processor receives input data - PP1 from the AZU and control signals UPA1 from the control unit. The output of this processor can be the results of arithmetic operations - ARL1, which are fed to the input of a standard output device. Specialized symbol processing devices PRСО1 are designed to solve search problems, operations related to search and replace functions, sorting operations of input information, etc. As an example, we can cite a number of specialized devices for processing symbolic information [10, 11, 12, 13, 14]. Upon the arrival of the PP1 signal from the LC LC and the control signals UPS1 from the control unit to the input PRSO1, symbolic processing operations are performed depending on the specific task. The output from the specialized SIM1 devices goes to the input of a standard output device. Any peripheral device can be a standard output device: display, printer, streamer, tape drives, etc.

The control unit 5 is synthesized based on the GAW control algorithm (Fig. 7) in a known manner [3]. Marked GAW operation of the control unit 5 is shown in Fig.8, where it is indicated:
Logical conditions:
X1: UOO
X2: "START"
X3: "PR"
X4: "J ≤ T"
X5: "ARP"
X6: "SS"
X7: "RAV"
Operators:
U1: "RESET: = 1"
U2: "i: = 1"
Y3: "j: = 1"
Y4: "YO: = 1"
U5: "Sat: = 1"
U6: "SBS: = 1"
Y7: "SBO: = 1"
Y8: "SBR: = 1"
Y9: "TIi: = 1"
Y10: "PI: = 1"
Y11: "ГИi: = 1"
Y12: "PIMi": = 1 "
Y13: "GIMi: = 1"
Y14: "VKi: = 0"
Y15: "C / Zi: = 0"
U16: "RAMi: = ШД"
Y17: "RAMi: = SHAS"
Y18: "i: = i + 1"
Y19: "j: = j + 1"
U20: "WRj: = 0"
U21: "AZUj: = ШДAj"
U22: "AZUj: = ШAAj"
U23: "AZUj: = CUAj"
Y24: "C / Zi: = 1"
U25: "RAMi: = SHAST"
U26: "MAGICIAN: = EXITi"
Y27: "AZUj: = BXi"
Y28: "PЗj: = BXДi-PPj"
U29: "AZUj: = BXDi"
U30: "AZUj: = PЗj"
U31: "PIJ: = 1"
U32: "WRj: = 1"
Y33: "BAHj: = PPj"
Y34: "APLPj: = UPAj"
Y35: "APLPj: = PPj"
Y36: "PRSOj: = Oopsj"
Y37: "PPCOj: = PPj"
SOURCES OF INFORMATION
1. Maslov S.Yu. The theory of deductive systems and its applications. - M .: Radio and communications, 1986. - 136 p. (Cybernetics).

 2. Markov A.A., Nagorny N.M. Theory of Algorithms - M .: Science. - 432 s. The main edition of the physical and mathematical literature. 1984 year

 3. Assumption V. A., Semenov A. L. Theory of algorithms: basic discoveries and applications. - M .: Science. The main edition of the physical and mathematical literature. 1987 - 210 p.

 4. Black Yu. Computer Networks: Protocols, Standards, Interfaces: Per. from English - M.: Mir, 1990 .-- 506 p., Ill.

 5. Large integrated circuits of storage devices: Reference / A.Yu. Gordonov, N.V. Bekin, V.V. Tsyrkin et al.: Ed. A.Yu. Gordonova and Yu.N. Dyakova. - M.: Radio and Communications, 1990. - 288 p., Ill.

 6. Aleksenko A. G., Shagurin I.I. Microcircuitry: Textbook. manual for universities. - 2nd ed., Revised. and add. - M .: Radio and communications, 1990. - 496 p., Ill.

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 10. Patent N 2150740, Bull. N 16, 06/10/2000.

 11. A.S. N 1667097, Bull. N 28, 07/30/91.

 12. Patent N 1837327, Bull. N 32, 08/30/93.

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 14. Patent N 2067317.

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 17. Patent N 2145113 (analogue).

Claims (1)

 A resource sharing system comprising a control unit, characterized in that the 1st, 2nd and nth localized centers, a data transmission line are further introduced, the first information output of the control unit being connected to the second information input of the localized center LC1, the first information input which is connected to the first information output of the data transmission line, the second information output of which is connected to the first information input of the localized center LC 2, the information output of which is is dined with the second information input of the data transmission line, the nth information output of which is connected to the first information input of the localized data center, the information output of which is connected to the nth information input of the data transmission line, the first information input of which is connected to the information output of the first localized data center , the second information input of the localized center LC2 is connected to the second information output of the control unit, the third information output of which is connected to the second the information input of the nth localized center of the LC, the first and second control inputs "START" and "RESET" of the control unit are the external inputs of the device.

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