RU2187140C2 - Digital device for adaptive correction of quadrature demodulators - Google Patents

Abstract

FIELD: radio engineering devices and systems containing radio components with analog and digital signals. SUBSTANCE: device has a square-wave generator, counter, display unit, precision generator of reference-frequency quadrature harmonic signals, pulse shaper, digital synchronization phase control digital unit, as well as two buffer registers, two digital second-order 22R filters, two arithmetic adder-subtractors, two time division multiplexers and a microprocessor set with input and output data registers, data processing unit, microprogram control unit and a sync generator. The digital 22R filters are realized according to the conveyer-type circuit. EFFECT: expanded functional potentialities consisting in identification of additional parameters and enhanced operativeness of adaptive correction of dynamic characteristics of radio channels with digital phase modulators. 3 dwg

Description

 The invention relates to radio measurement technology and can find application for adaptive correction of dynamic parameters of complex non-linear and non-stationary radio devices and systems containing radio components with both analog and digital signals, for example, a quadrature demodulator with ADC at the output, which is widely used in radar systems direction finders and sonar systems with phased antenna arrays.

 A known method and device for measuring and correcting digital methods in-phase and quadrature radio channel [1, 2, 3, 4].

With the instability of the dynamic characteristics of radar stations, such as frequency response and phase response, into a digital Doppler processing device for quadrature pulsed video signals [5], containing blocks of the direct discrete Fourier transform DFT (FFT) and the block of inverse discrete Fourier transform ODPF (OBPF), an additional digital block was introduced a single-band pulse video signal CFOIVS containing out-of-band phase shifter at an angle of 90 ^o or 270 ^o . CFOIVS forms a spectrum of a single-band signal only within one frequency interval 0-F _p , while the rest of the spectrum remains two-band (F _p - repetition frequency). This device allows you to correct the distortion caused not only by the transmitter, but also introduced by the transmitting and receiving antennas, as well as the receiver circuits. In this case, to calculate the correction signals, it is necessary to find a suitable external signal source relative to the radar. This approach is used in the COBRA DANE radar, working with a broadband 200-MHz signal. To form the reference signal, a satellite combined reflector created in the Lincoln Laboratory in the form of a sphere with an EPO equal to 1 m ^{2 was used} . The signal reflected from the sphere is converted into digital form and processed by the FFT processor to calculate the correction factors for the FIR pulse compression filter.

 The microprocessor implements an automatic procedure for adjusting the amplitude and phase characteristics of one of the quadrature channels relative to the other. The disadvantages of these devices include the complexity of the correction algorithm for the pulse transition function of an adaptive digital filter, which inevitably reduces accuracy and speed.

 A close technical solution to the proposed one is a digital phase shift meter [6], which contains the object of study - a quadrature demodulator, two analog-to-digital converters, two adders-subtracters, two adders-storage, two control units for nonlinear filtering, counters, a computing unit and an indication unit . Synchronization of all blocks, except for the microprocessor computing unit, is carried out from a precision crystal oscillator of the ADC clock signals.

 The disadvantage of this device is to limit the number of identifiable parameters of the quadrature demodulator. In addition, when detecting the inadequacy of the radio channels of the quadrature demodulator, it did not allow for the operational adaptive correction of their dynamic characteristics.

 Closest to the proposed device for determining the cross-correlation functions of the transient characteristics of the quadrature demodulator [7], containing a rectangular pulse generator, counter, display unit, a precision generator of quadrature harmonic signals of the reference reference frequency, a pulse shaper, a digital synchronization phase control unit, the output of which is connected to the input setting the phase of the rectangular pulse generator, the output of which is connected via a key to the signal information input of the quad The output demodulator, which is the object of parametric identification and adaptive correction, the output of the first phase of the reference signal of the reference frequency of the harmonic signal generator is connected via a pulse shaper to the information input of the counter and the first in-phase input of the investigated quadrature demodulator, the second input of which is connected to the orthogonal output of the reference harmonic signal generator, output counter overflow is connected to the information input of a digital phase control unit ui.

 The disadvantages of this device include limitations on the use of measurement results directly for adaptive digital correction of the characteristics of the quadrature demodulator in real time.

 The present invention aims to expand the functionality of the device. The technical result achieved in solving this problem consists in identifying three additional generalized parameters, such as transmission coefficient, low-pass filtering band and the phase response slope, and improving the adaptive correction of the dynamic characteristics of radio channels with digital quadrature modulators.

 This is achieved by the fact that in a known device containing a square-wave pulse generator, counter, display unit, a harmonic signal generator of a reference reference frequency, a pulse shaper, a digital synchronization phase control unit, the output of which is connected to the start input of a square-wave generator, the output of which is connected via a key to the signal information input of the quadrature demodulator, which is the object of adaptive correction of parameters, the first output of the harmonic signal generator soy dinene with the first in-phase input of the quadrature demodulator and through a pulse former with the information input of the counter, the second output of the harmonic signal generator is connected to the second orthogonal input of the quadrature demodulator, the overflow output of the counter is connected to the information input of the digital block for controlling the phase of synchronization, two buffer registers are introduced, the information inputs of which are measuring inputs for connecting to the corresponding outputs of the quadrature demodulator (ADC), two digital B Second-order IIH filters, connected by information inputs in parallel code to the outputs of the first and second buffer register, respectively, two arithmetic adders-subtracters, two digital accumulators-accumulators, two time division multiplexers, inputs connected to the first, second and third outputs of the corresponding digital IIR -filters, and the outputs to the first and second inputs of the corresponding arithmetic adders-subtracters, the outputs of which are connected to the inputs of the first and second digital adders-accumulate For a microprocessor set, respectively, containing input and output data registers, a data processing unit (BOD), a microprogram control unit (MPU) and a clock generator (GSI), the first and second input data registers connected to the outputs of the respective digital storage adders, the first the control output of the microprocessor set is connected to the input of the digital block for controlling the phase of synchronization, and the second control output of the microprocessor set is connected through a digital block of regulation phase synchronization with the start input of the rectangular pulse generator, the output of the pulse shaper is connected to the synchronization input of the microprocessor set, the output of the general synchronization of which is connected to the corresponding synchronization inputs of buffer registers, IIR filters, multiplexers, arithmetic adders-subtracters and digital adders-drives connected in series in parallel code according to the conveyor type scheme, the third, fourth and fifth control outputs of the microprocessor set connected to the first, second and third correction inputs of the first digital IIR filter, and the sixth, seventh and eighth control outputs of the microprocessor set are connected to the corresponding correction inputs of the second digital IIR filter, the fourth outputs of the first and second digital IIR filter are the adjusted outputs of the quadrature demodulator , the first, second and third output registers of the microprocessor set are connected to the display unit, the control input of which is connected to the ninth control conductive yield microprocessor kit.

 At the same time, second-order IIR digital filters are implemented according to the conveyor type scheme and contain in a direct circuit the first arithmetic multiplication unit, the first input of which is the information input of the digital IIR filter, the first arithmetic adder-subtractor, the third arithmetic multiplier, the first digital accumulator-accumulator , the third arithmetic unit of multiplication and the second digital adder-drive, connected in series in parallel code, and the outputs of the second and first digital adder-drive and the first arithmetic adder-subtractor are respectively the first, second and third output of the digital IIR filter, the feedback of which includes the second arithmetic adder-subtractor, connected by the inputs to the first and second outputs of the digital IIR filter, and the output to the second input of the first arithmetic adder-subtractor , the first output of the digital IIR filter is connected to the first input of the third arithmetic adder-subtractor, to the second input of which is connected through the fourth arithmetic unit of multiplication and four the third arithmetic adder-subtracter is the second output of the digital IIR filter, the third output of which is connected to the second input of the fourth arithmetic adder-subtractor through the fifth arithmetic multiplier, the second inputs of the first, fourth, and fifth arithmetic multiplicators are the first, second, and third correcting inputs of the digital The IIR filter is respectively connected to the corresponding control outputs of the microprocessor set, and the output of the third arithmetic adder-subtractor of each The digital IIR filter is the corresponding output of the quadrature demodulator.

 Figure 1 presents the structural diagram of the device; figure 2 is a diagram of a digital IIR filter; figure 3 - experimental results of the study of the error of the BCD when assessing the phase of the radio pulse in the case of parametric disturbances and operational adaptive correction.

A digital device for adaptive correction of quadrature demodulators (Fig. 1) contains a harmonic signal generator 1 (thermostabilized, quartz, reference frequency) shifted by 90 ^o (reference generator), a synchronization pulse generator 2, counter 3, a rectangular pulse generator 4, key 5 , a quadrature demodulator block 6 (radio engineering object), containing two analog-to-digital converters (ADCs) 8, 9 of the signals at the respective outputs of the analog low-pass filters in digital form, a digital phase control unit timing 7, two buffer registers 10, 11, the information inputs of which are measuring inputs for connecting the corresponding outputs of the quadrature demodulator (ADC), two multiplexers with time division of switched channels 12 and 13, two digital IIR filters of the second order 14 and 15, two arithmetic the adder-subtractor 16 and 17, two arithmetic accumulator-adders 18 and 19, a microprocessor kit 20 containing input and output data registers, a data processing unit (AML), a microprogram control device (MPU) a clock generator (GSI), which synchronizes the operation of the MPU, AML, registers, time-division multiplexers, and the indicating unit 21. The microprogram control device operates in a pipelined mode, which improves the speed due to the parallel organization of the operation of the buffer registers 10, 11, digital IIR -filters 14 and 15, multiplexers 12, 13, arithmetic adders-subtractors 16, 17, digital adders-drives 18, 19 and a microprocessor set 20. Each digital IIR filter 14 and 15 (figure 2) contains the first 22, the second 23 and the third 24 arithmetic multiplication blocks, four arithmetic adders-subtractors 25, 26, 27 and 28 and two digital adders-accumulators 29, 30, as well as the fourth 31 and fifth 32 arithmetic multiplication blocks.

Digital IIR filters 14, 15 operate in a pipelined mode. Synchronization of data recording from the buffer registers 10, 11 is carried out by the general synchronization signal from the microprocessor kit (MPU). The harmonic reference frequency signal generated by the generator 1 is fed to the input of the shaper 2 and then the counter 3, dividing the reference frequency signal, for example, by 10 ³ by one output of the counter 3 and by (10 ³ -1) by the other output (shift by one discharge). Counter 3 synchronizes the start coherently with the reference reference signal of the generator of 4 rectangular pulses with a frequency f _g = f _0/10 ³ . Generator 4 generates a sequence of short pulses coherently shifted relative to the clock pulses by the value τ (i) specified by the digital phase 7 control unit, which is controlled in parallel code from the microprocessor set 20. The output of the generator 4 is connected via key 5 to the first signal input of the quadrature demodulator under study 6, and its second and third inputs receive harmonic quadrature reference signals from two outputs of the generator 1 of harmonic signals. The outputs of the investigated quadrature demodulator 6 through the buffer registers 10, 11 are connected to the corresponding inputs of the digital IIR filters 14, 15, the first, second and third outputs of which through the multiplexers 12 and 13 are switched in parallel code with the corresponding inputs of the arithmetic adders-subtractors 16 and 17, the outputs of which are connected to the information inputs of the digital adders-drives 18 and 19. Evaluations of the identified generalized parameters of the studied radio engineering object (BCD) or their deviations from the reference output are sequentially in time through the corresponding output data register to the indicating device 21. The synchronization of all units operating in the conveyor mode is carried out from the harmonic signal generator 1 (reference frequency) through a pulse shaper 2 by a microprocessor set (GPS) 20, which is via a digital control unit synchronization phase 7 starts the rectangular pulse generator 4.

где

Групповое время запаздывания ±τ₃ в каналах квадратурного демодулятора, обусловленное аппаратной реализацией радиотехнического канала, не влияет на оценку (2), так как находится внутри интервала усреднения.The device operates as follows. The harmonic signal of the reference frequency generated by the generator 1, is fed to the input of the pulse shaper 2 and then the counter 3, dividing the signal of the reference frequency, for example, by 10 ³ on one output of the counter 3 and on (10 ³ -1) on the other output (shift one bit). The microprocessor set starts 4 rectangular pulses with a lower frequency f _g = f _0/10 ³ coherently with the reference reference signal. Generator 4 generates a sequence of rectangular pulses coherently shifted relative to the clock pulses by a value of τ [i], which is set by a digital phase 7 control unit controlled by microprocessor set 20. These broadband pulses are fed through key 5 to the first signal input of the quadrature demodulator under study 6, and to the second and its third inputs harmonic quadrature reference signals from two corresponding outputs of the harmonic generator 1. The pulse responses of the channels of the quadrature demodulator 6, corresponding to the IAP (pulse transition function) of the radio channels w ₁ (φ ₁ , t) and w ₂ (φ ₂ , t) from the outputs of the ADC 8, 9 are fed to the information inputs of the first and second buffer register 10, 11. The pulse transition function w _j (φ _j , t) corresponds to the transfer function [7] of one channel of the quadrature demodulator for changing the input amplitude at a constant value of φ (i)

Where

The group delay time ± τ ₃ in the channels of the quadrature demodulator, due to the hardware implementation of the radio channel, does not affect estimate (2), since it is inside the averaging interval.

где j=1, 2;
i - соответствует какому-то шагу измерения.

where j = 1, 2;
i - corresponds to some measurement step.

Unlike the known device [7], in this device, integration over the averaging interval from t _bv [1] to t _bv [1000] is performed in arithmetic accumulators-accumulators 18 and 19, respectively, by the approximate “forward” rectangle method, which, unlike all others methods of numerical integration does not introduce an additional phase shift into the digital IIR filter, in the structure of which there are two discrete integrators 29, 30 (see figure 2), which does not lead to loss of stability of the second-order digital filter, even if the coefficient nt damping ξ filter is made equal to zero, which corresponds to the structure of an auto-oscillating link. At the first step of identifying the parameters, the transmission coefficients of the in-phase and quadrature channels of the demodulator 6 are estimated. Using the digital block for controlling the phase 7 of the shift of the exciting pulse, φ = 45 ^{o is set} , in this case sin [φ] = cos [φ] = 1/2. The microprogram control device, which is part of the microprocessor kit 20, using multiplexers 12 and 13, commutes the first outputs of the corresponding IIR filters through adders-subtractors 16, 17 with the first and second digital adders-drives 18 and 19. The sample size, which is set at the beginning measurement, controlled by microprocessor kit 20.

Поскольку интегрирование сигналов с выходов цифровых БИХ-фильтров осуществляется на всем протяжении ИПФ каналов квадратурного демодулятора, влияние двух других обобщенных параметров ξ_кд и Т_кд в этом режиме измерения не сказывается, так как интеграл от первой и второй производной ИПФ на этом интервале равен нулю. Используя полученную оценку К*, можно произвести соответствующую коррекцию цифрового БИХ-фильтра, изменяя параметр масштабного блока 22 (см. фиг. 2). В этом режиме можно оценить смещение ΔS^* в каналах БКР, обусловленное дрейфом активных усилителей ПТ.The mismatch of the channels of the quadrature demodulator 6 according to the transmission coefficient K $\genfrac{}{}{0ex}{}{\text{*}}{\text{j}}$
ΔK ^* = 1-SC ₁₁ / SC ₂₁ , (3)
Where

Since the integration of the signals from the outputs of the digital IIR filters is carried out throughout the IPF channels of the quadrature demodulator, the influence of two other generalized parameters ξ _cd and T _cd in this measurement mode does not affect, since the integral of the first and second derivatives of the IPF in this interval is equal to zero. Using the obtained estimate of K *, it is possible to make the corresponding correction of the digital IIR filter by changing the parameter of the scale block 22 (see Fig. 2). In this mode, it is possible to estimate the shift ΔS ^* in the BCR channels, due to the drift of active PT amplifiers.

ΔS $\genfrac{}{}{0ex}{}{\text{*}}{\text{j}}$ = ∑C _j1 [n _k T] / 1000,
where C _i1 - signals at the first output of IIR filters with open key 5.

где Т - шаг квантования, во времени единый для АЦП и БИХ-фильтров, работающих в конвейерном режиме;
n=1, 2, 3, 4,...At the second stage, the second parameter, characterizing the error of the phase shift between the channels, is sequentially evaluated in accordance with the algorithm: 1) the signals of the first outputs of the IIR filters C ₁₁ (nT) and C ₂₁ are taken as the signals X (nT) and Y (nT) (nT); 2) the delay operator τ _{3 is} approximated by a second-order Padé series, which corresponds to a linear differential equation:

where T is the quantization step, uniform in time for the ADC and IIR filters operating in the conveyor mode;
n = 1, 2, 3, 4, ...

From equation (4) we can go to equation
DF ² Z ₃ (nT) + 6 DFZ ₂ (nT) -12Z ₁ (nT) = 0 (5)
where DF is an unknown parameter characterizing the sign and magnitude of the phase shift in the channels of the quadrature demodulator, including ADC and digital IIR filters. With a fixed duration of IPF and periodic excitation of the object of study
Z ₁ (nT) = C ₂₁ (nT) -C ₁₁ (nT),
Z ₂ (nT) = C ₂₂ (nT) + C ₁₂ (nT),
Z ₃ (nT) = C ₂₃ (nT) -C ₁₃ (nT),
The variable Z ₁ (nT) at discrete points (nT) is generated at the output of the arithmetic adder-subtractor 16 and synchronously fed to the information input of the digital adder-accumulator 18. The signal Z ₂ (nT) is generated at the output of the arithmetic adder-subtractor 17. Signals With _ji (nT) are removed from the first, second and third outputs of the digital IIR filters 14, 15, respectively, and
C _j2 (nT) = dC _jl (nT) / dt,
and C _j3 (nT) = dC _j2 (nT) / dt = d ² C _jl (nT) / dt ² .

S'Z₃=-S'Z₁
Микропроцессорный комплект 20 вычисляет значение
DF₁=(3•SZ₂+D)/SZ₁,
DF₂=(3•SZ₂-D)/SZ₁,
где D - дискриминант уравнения (6), вычисляется по формуле

Результатом цифрового измерения сдвига фаз DF является меньший по модулю из двух DF₁ и DF₂. Знак и величина DF* так же, как и ΔK^*, выводится на блок индикации 21.The accuracy of the estimation of the phase shift in the channels of the quadrature demodulator 6 can be improved by statistically accumulating information on the digital adders-drives 18 and 19, while simultaneously controlling the GPS. The sample size is controlled by the MPU firmware. The integration of the signals included in equation (5) on specially formed time intervals n _i Т and n _{i + k} Т was replaced by numerical integration by the rectangle method. The microprocessor set of blocks 20 solves the generated quadratic equation with respect to the unknown parameter DF in the BOD:
DF ² (-SZ ₁ ) + 6DFSZ ₂ -12SZ ₁ = 0, (6)
Where

S'Z ₃ = -S'Z ₁
Microprocessor Kit 20 calculates the value
DF ₁ = (3 • SZ ₂ + D) / SZ ₁ ,
DF ₂ = (3 • SZ ₂ -D) / SZ ₁ ,
where D is the discriminant of equation (6), is calculated by the formula

The result of a digital measurement of the phase shift DF is the smaller in modulus of the two DF ₁ and DF ₂ . The sign and value of DF * as well as ΔK ^* , is displayed on the display unit 21.

 Estimation of DF * corresponds to the mismatch in the group delay time in the BCR channels according to expression (1).

If the transport delay e ^-τ in the first and second channels of the quadrature demodulator is the same, then in the second stage we can estimate the deviation of the parameter (2ζ _ld T _cd ) = b $\genfrac{}{}{0ex}{}{\text{*}}{\text{1/}}$ from the "reference" and make the appropriate correction.

The microprocessor set (MPU) 20 using multiplexers 12 and 13 commutes the second outputs of the corresponding digital IIR filters through the first inputs of the arithmetic adders-subtractors 16, 17 to the first and second digital adder-drive 18, 19, respectively. Channel mismatch of quadrature demodulator 6 by parameter b $\genfrac{}{}{0ex}{}{\text{*}}{\text{j1}}$
Δb $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ = 1-S _M C ₁₂ / S _M C ₂₂ , (7)
where S _M C _j2 = ∑ | C _j2 | (nT);
C _j2 (nT) • SIGN [Cj2 (nT)] = | Cj2 | (nT).
Since the integration of the signals C _jl (nT) • SIGN [C _j2 (nT)] and C _j3 (nT) • SIGN [C _j2 (nT)] on the IPF duration interval in the equation of the form (4) is equal to zero.

Using the multiplication unit 31 in the structure of the IIR filter, the microprocessor set 20 corrects the second parameter ± Δb ₁ characterizing the phase mismatch between the channels of the BCD. On figa shows the experimental waveforms of narrow-band BKD (Δf = 15 kHz) at Δφ = ± 5 ^° . At the third stage of the identification procedure, an estimate of ΔT $\genfrac{}{}{0ex}{}{\text{* 2}}{\text{cd}}$ = Δb $\genfrac{}{}{0ex}{}{\text{*}}{\text{2}}$ . Multiplexers 12 and 13 respectively connect the third outputs of the IIR filters through arithmetic adders-subtractors 16, 17 to the first and second digital adder-drive 18 and 19.

Уравнение (8) можно получить, если сдвиг по фазе в каналах БКД равен 45^o. В этом случае sin(φ₁) = cos(φ₁) = 1/2, так как к третьему этапу параметрической идентификации каналы БКР по первым двум параметрам ΔK^* и Δb $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ адаптивно откорректированы.Δb $\genfrac{}{}{0ex}{}{\text{*}}{\text{2}}$ = 1-S _M C ₁₃ / S _M C ₂₃ , (8)
Where

Equation (8) can be obtained if the phase shift in the channels of the BCD is equal to 45 ^o . In this case, sin (φ ₁ ) = cos (φ ₁ ) = 1/2, since by the third stage of parametric identification the BKR channels according to the first two parameters ΔK ^* and Δb $\genfrac{}{}{0ex}{}{\text{*}}{\text{1}}$ adaptively adjusted.

The operation of taking the module from the numerical samples from the third output of the IIR filters is implemented in the microprocessor set in the BOD: the sign of the samples C _j3 [n _k T] at the corresponding outputs of the digital IIR filters is not taken into account.

Using the estimate Δb $\genfrac{}{}{0ex}{}{\text{*}}{\text{j2}}$ (mismatch in the passband of the low-pass filter in the BKD), the microprocessor kit 20 adaptively corrects the IIR filters using the multiplication unit 32. In FIG. Figure 3 shows the experimental results of verifying the operation of a digital identifier using an example of a narrowband BCD with a modulation frequency f ₀ = 30 MHz and a passband Δf = 15 kHz. As shown by experimental studies, to suppress interference by 25 dB, the mismatch of the BCR channels should not exceed about 0.5 dB in amplitude and 2.8 ^o in phase. The experimental results confirmed the promise of a digital device for adaptive correction of BKR channels of radio engineering systems in real time, which significantly increases the efficiency of technical diagnostics and commissioning of complex radio engineering systems.

Literature
1. US patent 4484194, IPC G 01 G 7/40 from 11.27.84.

 2. S. J. Rabinovitz et al. "Digital methods in radar", TIIER, Volume 73, 2, 1985, p. 182-199.

 3. Int. PCT application, 86/01001, IPC G 01 B, 52, 7/29 of 02/13/86.

 4. US patent 5717619, IPC G 06 F 17/10 from 02/10/98.

5. RF application for invention, 97109368/09, IPC ⁶ G 06 F 17/00, G 01 S 13/00, "Digital device for Doppler processing of quadrature pulsed video signals." RU BI 15 05/27/99, p. 260.

 6. A.S. USSR 1292492 (NP), IPC G 06 F 15/336, "Device for determining the correlation functions of the characteristics of the quadrature demodulator." Publ. 02/28/85.

 7. A.S. USSR 1609328 (NP), IPC G 06 G 7/19, G 01 R 25/00, "Digital phase shift meter." Publ. 12/23/88.

Claims (1)

 A digital device for adaptive correction of quadrature demodulators with analog-to-digital converters (ADC), containing a rectangular pulse generator, a counter, an indication unit, a harmonic signal generator of a reference reference frequency, a pulse shaper, a digital synchronization phase control unit, the output of which is connected to the generator phase input rectangular pulses, the output of which through the key is connected to the signal information input of the quadrature demodulator with ADC, the first output of the generator of the reference frequency harmonic signals is connected to the first in-phase input of the quadrature demodulator with an ADC and a shaper, of pulses connected to the counter information input, while the second output of the reference harmonic signal generator receives harmonic quadrature reference signals to the second input of the quadrature demodulator with ADC, counter overflow output connected to the information input of the digital synchronization phase regulation block, the information inputs of the two buffer registers are measure inputs for connecting to the corresponding outputs of the quadrature demodulator with ADC, two second-order digital IIR filters are connected to the first and second buffer registers respectively, the inputs of two time division multiplexers are connected to the first, second and third outputs of the corresponding second-order IIR digital filters, and the outputs of two multiplexers - to the inputs of the corresponding arithmetic adders-subtracters, the outputs of which are connected to the inputs of the first and second digital adders-drives respectively Accordingly, the microprocessor set is connected to the outputs of the respective digital storage adders, the first control output of the microprocessor set is connected to the reset input to the initial state of the digital synchronization phase control unit, and the second control output of the microprocessor set is connected to the digital synchronization phase control unit, the output of the pulse shaper is connected to the input of the microprocessor kit, the output of which is connected to the corresponding inputs of the synchronization buffer histories, second-order IIR filters, time division multiplexers, arithmetic adders-subtracters and digital storage adders, the third, fourth and fifth control outputs of the microprocessor set are connected to the correction inputs of the first second-order IIR digital filter, and the sixth, seventh and eighth control the outputs of the microprocessor set are connected to the corresponding corrective inputs of the second digital IIR filter of the second order, the fourth outputs of the first and second digital IIR fi second-order liters are the corrected outputs of the quadrature demodulator with ADC, the microprocessor set is connected to the display unit, the control input of which is connected to the ninth control output of the microprocessor set.

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