RU2115165C1 - Device for information search - Google Patents

Abstract

FIELD: electric communication. SUBSTANCE: given device is inserted with commutator, former of reset signals, register of search strategy ensuring feed of input signal to various networks of logic elements. Selection units perform preselection of input digital stream by type of command frames and decoders select input stream by type of answer. With passage of signals through particular networks of logic elements indication unit forms information messages on results of search. With such design of device there are achieved possibility of operation under real time mode, zero possibility of skip ( in case of availability of a priori authentic information on protocol ), simplicity of realization and modification for any commutation protocol of dialog type. Probability of false alarms depends on success of establishment of communication session in monitored channel and is proportional to probability of transmission of complete set of corrected frames during communication session by stations subject to correct identification of form and type of frames. EFFECT: increased validity of detection and identification of information. 2 cl, 23 dwg

Description

 The invention relates to telecommunications and can be used to search for information and identification used in digital communication systems and, in particular, in data transmission networks (SPD) of the communication signal-oriented protocol DDCMP developed by DEC.

 A known analogue of the proposed device is described in ed. St. USSR N 1621049 class. G 06 F 15/40, 1989, contains boundary registers, summing and calculating counters of the comparison scheme, memory blocks, calculation blocks and a number of other elements that allow you to search for information.

 However, information search is implemented in it with the probability of a correct solution being less than 0.6, since recognition is performed in a statistical way, requiring a certain sample size, and each communication session in the DDCMP data link procedure is unique.

 Closest in technical essence to the claimed is a known information retrieval device (prototype) by ed. St. USSR N 1711185 class. G 06 F 15/40, 1989. This invention describes an information retrieval device comprising upper and lower bound registers, an adder-calculator, a search strategy register subtracting and adding up counters, comparison circuits, a memory block, a key register, an output register, a group AND and OR elements, trigger, trigger input, upper and lower border address inputs, search strategy change code input, key input, address output, output of a sign of lack of information and a pulse distributor.

 The disadvantage of this device is the impossibility of obtaining an unambiguous solution (the probability of a search with the correct identification of information of the order of 0.7), since the prototype implements the search for information blocks in the array using the dichotomous method without taking into account the presence of several possible variants of the sequences of allowed signals.

 The aim of the invention is the development of a binary sequence search device formed according to the rules of the DDCMP data transfer protocol, which improves the reliability of the search and identifies information by obtaining a unique solution.

 This goal is achieved by the fact that in the known information retrieval device containing the first, second totalizing counters and the search strategy register, the following elements are additionally introduced: switch, reset driver, first, second, third selection blocks, first, second, third decoder blocks , third totalizing counter, pulse generator, display unit. The first, second, third, fourth information outputs of the switch are connected respectively to the first, second, third, fourth information inputs of the first selection block. The fifth, sixth, seventh and eighth information outputs of the switch are connected respectively to the first, second, third, fourth information inputs of the second block selection. The ninth, tenth, eleventh, twelfth information outputs of the switch are connected respectively to the first, second, third, fourth information inputs of the third selection block. The first control output of the reset signal generator is connected to the first control input of the first selection block, the second control input of the first selection block is an input of cyclic synchronization, the second control output of the reset signal generator is connected to the first control input of the second selection block, the second control input of the second selection block is a cyclic input synchronization, and the third control output of the reset signal generator is connected to the first control input of the third selection block, the second unit ulation input of the third selection unit is input to the frame synchronization. The first, second, third, fourth information inputs of the first selection block are connected to the corresponding information inputs of the first decoder block. The control outputs of the first, second selection block and the second control output of the third selection block are combined with the third control output of the first and second decoders, the second control output of the third decoder, the control output of the third totalizing counter and connected to the second control input of the display unit.

 The first, second, third, fourth information outputs of the second selection block are connected to the corresponding information inputs of the second decoder.

 The first, second, third, fourth information outputs of the third selection block are connected to the corresponding information inputs of the third decoder. The first control output of the third selection block and the third output of the third decoder block are combined and connected to the second control input of the third totalizing counter.

 The first control output of the first decoder block is connected to the second control input of the search strategy register, the second control output of the first decoder block is combined with the second control output of the second decoder block, the control output of the display unit and connected to the first control input of the search strategy register.

 The first control output of the second decoder unit is combined with the first control output of the third decoder unit and connected simultaneously with the third control input of the search strategy register, with the first control input of the third totalizing counter.

 The control output of the first totalizing counter is connected to the first control input of the display unit. The control output of the second totalizing counter is connected to the third control input of the display unit.

 The first, second control outputs of the search strategy register are connected respectively to the first, second control inputs of the first and second totalizing counter, reset signal generator, the first and second control inputs of the switch.

 The control output of the generator is connected to the third control input of the first totalizing counter and the third control input of the second totalizing counter.

 The first, second, third, fourth information inputs of the switch are the input of the device.

 The first selection block consists of a key, a comparison block, a totalizing counter. The first, second, third, fourth information inputs of the key are respectively the first, second, third, fourth information inputs of the first selection block. The first, second, third, fourth information inputs of the key are respectively the first, second, third, fourth information outputs of the first selection block. The second control output of the comparison unit is the control output of the first selection block. The fifth, sixth, seventh, eighth information outputs of the key are connected respectively to the first, second, third, fourth information inputs of the comparison unit. The second control input of the totalizing counter is the first control input of the first selection block. The third control input of the totalizing counter is a loop synchronization input and the second control input of the first selection block. The first control output of the comparison unit is connected to the first control input of the totalizing counter, the first, second control outputs of which are connected respectively to the first, second control inputs of the key.

 Unlike known devices that provide correct recognition of information with some probability depending on various conditions, the proposed device either gives an unambiguous solution (with sufficient information), or generates a denial of the solution (if the amount of information is below the threshold). A useful effect is to obtain an unambiguous decision on the presence (or absence) of messages of a certain type in the general information flow.

In FIG. 1 shows the electrical functional diagram of the proposed device; in FIG. 2 - electrical functional diagram of the switch 1; in FIG. 3 is an electrical functional diagram of a reset driver 2; in FIG. 4 is an electrical functional diagram of a first selection block 3; in FIG. 5 is an electrical functional diagram of a key 3.1; in FIG. 6 is an electrical functional diagram of a comparison block 3.2; in FIG. 7 is an electrical functional diagram of a summing counter 3.3; in FIG. 8 is an electrical functional diagram of a second selection unit 4; in FIG. 9 is an electrical functional diagram of a key 4.1; in FIG. 10 is an electrical functional diagram of a comparison unit 4.2; in FIG. 11 is an electrical functional diagram of a summing counter 4.3; in FIG. 12 is an electrical functional diagram of a third selection block 5; in FIG. 13 is an electrical functional diagram of a key 5.1; in FIG. 14 is an electrical functional diagram of a comparison unit 5.2; in FIG. 15 is an electrical functional diagram of a summing counter 5.3; in FIG. 16 is an electrical functional diagram of a decoder unit 6; in FIG. 17 is an electrical functional diagram of a decoder unit 7; in FIG. 18 is an electrical functional diagram of a decoder 8; in FIG. 19 is an electrical functional diagram of a summing counter 9; in FIG. 20 is an electrical functional diagram of a summing counter 10; in FIG. 21 is an electrical functional diagram of a summing counter 11; in FIG. 22 - an algorithm for the operation of the communication protocol DDCMP; in FIG. 23 is a syntax recognition algorithm for a communication protocol DDCMP;
The claimed device, a structural diagram of which is shown in FIG. 1, consists of a switch 1, a shaper of reset signals (FSS) 2, the first 3, the second 4, the third 5 blocks of selection (BS), the first 6, the second 7, the third 8 blocks-decoders (BDS), the first 9, second 10, third 11 totalizing counter (SS), generator (G) 12, search strategy register (RSP) 13, display unit (BI) 14.

 The first, second, third, fourth information outputs of the switch 1 are connected respectively to the first, second, third, fourth information inputs of the first selection block 3. The fifth, sixth, seventh, eighth information outputs of the switch 1 are connected respectively to the first, second, third, fourth information the inputs of the second selection block 4. The ninth, tenth, eleventh, twelfth information outputs of the switch 1 are connected respectively to the first, second, third, fourth information inputs of the third block breeding 5.

 The first control output of the reset signal generator 2 is connected to the first control input of the first selection block 3, the second control output of the reset signal generator 2 is connected to the first control input of the second selection block 4, and the third control output of the reset signal generator 2 is connected to the first control input of the third selection block 5. The second control inputs of the first 3, second 4, third 5 selection blocks are inputs of cyclic synchronization. The first, second, third, fourth information outputs of the first selection block 3 are connected to the corresponding information inputs of the first decoder unit 6. The control outputs of the first 3, second 4 selection blocks and the second control output of the third selection block 5 are combined with the third control output of the first 6 and second 7 of the decoder unit, the second control output of the third decoder unit 8, the control output of the third totalizing counter 11 and connected to the second control input of the display unit 14.

 The first, second, third, fourth information outputs of the second block of selection 4 are connected to the corresponding information inputs of the second block-decoder 7.

 The first, second, third, fourth information outputs of the third block of selection 5 are connected to the corresponding information inputs of the third block-decoder 8, the first control output of the third block of selection 5 and the third output of the third block-decoder 8 are combined and connected to the second control input of the third totalizing counter 11 .

 The first control output of the first decoder unit 6 is connected to the second control input of the search strategy register 13, the second control output of the first decoder unit 6 is combined with the second control output of the second decoder unit 7, the control output of display unit 14 and connected to the first control input of the strategy register search 13.

 The first control output of the second decoder unit 7 is combined with the first control output of the third decoder unit 8 and is connected simultaneously with the third control input of the search strategy register 13, with the first control input of the third totalizing counter 11.

 The control output of the first totalizing counter 9 is connected to the first control input of the display unit 14. The control output of the second totalizing counter is connected to the third control input of the display unit 14.

 The first, second control outputs of the search strategy register 13 are connected respectively to the first, second control inputs of the first 9 and second 10 of the totalizing counter, reset signal generator 2, and the first, second control inputs of switch 1.

 The control output of the generator 12 is connected to the third control input of the first totalizing counter 9 and the third control input of the second totalizing counter 10.

 The first, second, third, fourth information inputs of the switch 1 are the input of the device.

 The switch 1 shown in FIG. 2, is designed to transmit the received signal in one of three selected directions, depending on the control signal received at its input. It consists of four-bit bus drivers (hereinafter referred to simply as the “driver”) 1.8, 1.9, 1.10, inverters 1.1, 1.2, 1.3, 1.4, logical elements (LE) OR 1.5, 1.6, 1.7. The first, second, third, fourth information inputs of drivers 1.8, 1.9, 1.10 are combined and are the first, second, third, fourth information inputs of switch 1. The control input of driver 1.8 is connected to the control output of LE OR 1.5, the control input of driver 1.9 is connected to the control the output of the LE OR 1.6, the control input of the driver 1.10 is connected to the control output of the LE OR 1.7. The control inverse output of the inverter 1.1 is connected to the second control input LE LE 1.5. The control inverse output of the inverter 1.2 is connected to the first control input of the LE OR 1.6. The control inverse output of the inverter 1.3 is connected to the first control input of the LE OR 1.7, the control inverse output of the inverter 1.4 is connected to the second control input of the LE OR 1.7. The first control input of LE OR 1.5, the control input of inverter 1.2, the control input of inverter 1.3 are combined and are the first control input of switch 1, the control input of inverter 1.1, the second control input of LE OR 1.6, the control input of inverter 1.4 are combined and are the second control input of switch 1. The first, second, third, fourth information outputs of the driver 1.8 are respectively the first, second, third, fourth information outputs of the switch 1. The first, second, third, fourth information outputs of the drive RA 1.9 are respectively the fifth, sixth, seventh, eighth information outputs of switch 1. The first, second, third, fourth information outputs of driver 1.10 are respectively the ninth, tenth, eleventh, twelfth information outputs of switch 1.

 The scheme of the four-digit bus driver 1.8-1.10 is known and described in the manual Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994, 240 pp., ill. on p. 87 images 2.74.

 The reset signal generator 2 shown in FIG. 3, is designed to generate control commands that control keys 3.1, 4.1, 5.1, setting them to their initial state, as a result of which the input data stream goes along the path in accordance with a given algorithm. It consists of LE OR 2.1 and a binary decoder 2.2 (hereinafter simply a decoder). The first, second control inputs of the decoder 2.2 are combined respectively with the first, second control inputs of the LE OR 2.1 and is the first, second control inputs of the driver of the reset signals 2. The third control input of the decoder 2.2 is connected to the control output of the LE OR 2.1. The first, second, third control outputs of the decoder 2.2 are the first, second, third control outputs of the shaper of the reset signals 2.

 The scheme of the decoder 2.2 is known and described in the manual Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994, 240 pp., ill. on p. 43, fig. 2.26.

 The first selection unit 3 shown in FIG. 4, is designed to select the input stream according to the type of command. It consists of a key 3.1, a comparison block 3.2, a totalizing counter 3.3. In this case, the first, second, third, fourth information inputs of the key 3.1 are respectively the first, second, third, fourth information inputs of the first block of selection 3. The first, second, third, fourth information outputs of the key 3.1 are respectively the first, second, third, fourth information the outputs of the first selection block 3. The second control output of the comparison block 3.2 is the control output of the first selection block 3. The fifth, sixth, seventh, eighth information outputs of the key 3.1 are connected respectively to the first, second, third, fourth information inputs of the comparison unit 3.2. The second control input of the totalizer 3.3 is the first control input of the first selection unit 3. The third control input of the totalizer 3.3 is an input of cyclic synchronization and the second control input of the selection unit 3. The first control output of the comparison unit 3.2 is connected to the first control input of the totalizer 3.3, the first, the second control output of which is connected respectively to the first, second input of the key 3.1.

 The key 3.1 shown in FIG. 5, is intended to select an input stream processing path in accordance with the algorithm of the protocol used. It consists of inverters 3.1.1 and 3.1.2, LE OR 3.1.3, 3.1.4, drivers 3.1.5 and 3.1.6. The first control input of the LE OR 3.1.3 is combined with the control input of the inverter 3.1.2, and their combination is the first control input of the key 3.1. The control input of the inverter 3.1.1 is combined with the first control input of the LE OR 3.1.4, and their combination is the second control input of the key 3.1, the control inverse output of the inverter 3.1.1 is connected to the second control input of the LE OR 3.1.3, the control output of which is connected to control input of the driver 3.1.5., the control inverse output of the inverter 3.1.2 is connected to the second control input of the LE OR 3.1.4, the control output of which is connected to the control input of the driver 3.1.6. The first, second, third, fourth information inputs of drivers 3.1.5 and 3.1.6 are combined and are respectively the first, second, third, fourth information inputs of key 3.1. The first, second, third, fourth information outputs of the driver 3.1.5 are respectively the first, second, third, fourth information outputs of the key 3.1. The first, second, third, fourth information outputs of the driver 3.1.6 are the fifth, sixth, seventh, eighth information outputs of the key 3.1, respectively.

 The comparison block 3.2 shown in FIG. 6, is designed to extract the received information from the input data stream and generate, depending on the result of the corresponding code at the output. It consists of a scheme for comparing two four-digit numbers 3.2.1. The first, second, third, fourth information inputs of the comparison circuit 3.2.1 are, respectively, the first, second, third, fourth information inputs of the comparison block 3.2. The first, second, third, fourth inputs of the comparison circuit 3.2.1 are installation inputs for recording the source data. The first, third control outputs of the comparison circuit 3.2.1 are combined, their combination is the second control output of the comparison block 3.2. The second control output of the comparison circuit 3.2.1 is the first control output of the comparison unit 3.2.

 Summing counter 3.3 shown in FIG. 7, is intended to control the key 3.1, depending on the control commands received at its input. It consists of trigger 3.3.1. The first, second control inputs of trigger 3.3.1 are, respectively, the first, second control inputs of the totalizing counter 3.3. The first, second control outputs of trigger 3.3.1 are, respectively, the first, second control inputs of the totalizing counter 3.3.

 The four-bit bus driver circuit 3.1.5, 3.1.6 is known and described in the reference book by Maltseva P.P., Dolidze N.S., Kritenko M.I., et al. -M.: Radio and Communications, 1994, -240 S .: ill. on p. 87, fig. 2.74.

 The comparison scheme of two four-digit numbers 3.2.1 is known and described in the reference book Maltseva P.P., Dolidze N.S., Kritenko M.I. et al., M.: Radio and Communications, 1994.240 s.: ill. on p. 83, fig. 2.71.

 The trigger circuit 3.3.1 is known and described in the reference book of Maltsev P.P., Dolidze N.S., Kritenko M.I. et al., Moscow: Radio and Communications, 1994.240 pp., ill. on p. 49, fig. 2.32.

 The second selection unit 4 shown in FIG. 8, is designed to select the input stream according to the type of command. It consists of a key 4.1, a comparison unit 4.2, a totalizing counter 4.3. The first, second, third, fourth information inputs of the key 4.1 are respectively the first, second, third, fourth information inputs of the second block of selection 4. The first, second, third, fourth information outputs of the key 4.1 are respectively the first, second, third, fourth information the outputs of the second selection unit 4. The second control output of the comparison unit 4.2 is the control output of the second selection unit 4. The fifth, sixth, seventh, eighth information outputs of the key 4.1 are connected respectively to the first, second, third, fourth information inputs of the comparison unit 4.2. The second control input of the totalizing counter 4.3 is the first control input of the second selection unit 4. The third control input of the totalizing counter 4.3 is an input of cyclic synchronization and the second control input of the selection unit 4. The first control output of the comparison unit 4.2 is connected to the first control input of the totalizing counter 4.3, the first, the second control outputs of which are connected respectively with the first, second control inputs of the key 4.1.

 The key 4.1 shown in FIG. 9, is intended to select an input stream processing path in accordance with the algorithm of the protocol used. It consists of inverters 4.1.1 and 4.1.2, LE OR 4.1.3, 4.1.4, drivers 4.1.5 and 4.1.6. The first control input LE OR 4.1.3 is combined with the control input of the inverter 4.1.2, and their combination is the first control input of the key 4.1. The control input of the inverter 4.1.1 is combined with the first control input of the LE OR 4.1.4, and their combination is the second control input of the key 4.1, the control inverse output of the inverter 4.1.1 is connected to the second control input of the LE OR 4.1.3, the control output of which is connected to control input of the driver 4.1.5, the control inverse output of the inverter 4.1.2 is connected to the second control input of the LE OR 4.1.4, the control output of which is connected to the control input of the driver 4.1.6. The first, second, third, fourth information inputs of drivers 4.1.5 and 4.1.6 are combined and are respectively the first, second, third, fourth information inputs of the key 4.1. The first, second, third, fourth information outputs of the driver 4.1.5 are respectively the first, second, third, fourth information outputs of the key 4.1. The first, second, third, fourth information outputs of the driver 4.1.6 are respectively the fifth, sixth, seventh, eighth information outputs of the key 4.1.

 The comparison block 4.2 shown in FIG. 10, is designed to extract the received information from the input data stream and generate, depending on the result, the corresponding output code. It consists of a scheme for comparing two four-digit numbers 4.2.1. The first, second, third, fourth information inputs of the comparison circuit 4.2.1 are, respectively, the first, second, third, fourth information inputs of the comparison block 4.2. The first, second, third, fourth inputs of the comparison circuit 4.2.1 are installation inputs for recording the source data. The first, third control outputs of the comparison circuit 4.2.1 are combined, their combination is the second control output of the comparison block 4.2. The second control output of the comparison circuit 4.2.1 is the first control output of the comparison unit 4.2.

 Summing counter 4.3 shown in FIG. 11, is designed to control the key 4.1, depending on the control commands received at its input. It consists of trigger 4.3.1. The first, second control inputs of the trigger 4.3.1 are respectively the first, second control inputs of the totalizing counter 4.3. The first, second control outputs of the trigger 4.3.1 are respectively the first, second control outputs of the totalizing counter 4.3.

 The driver circuit 4.1.5, 4.1.6 is known and described in the manual Maltseva P.P., Dolidze N.S., Kritenko M.I. et al., Moscow: Radio and Communications, 194. -240 pp., ill. on p. 87, fig. 2.74.

 A comparison scheme for two four-digit numbers 4.2.1 is known and described in the reference book by Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.240 s.: ill. on page 83, fig. 2.71.

 The trigger diagram 4.3.1 is known and described in the reference book of Maltsev P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994, -240 pp., ill. on p. 49, fig. 2.32.

 The third selection block 5 shown in FIG. 12, is designed to select the input stream according to the type of command. It consists of a key 5.1, a comparison unit 5.2, a totalizing counter 5.3. The first, second, third, fourth information inputs of the key 5.1. are respectively the first, second, third, fourth, information inputs of the third block of selection 5. The first, second, third, fourth information outputs of the key 5.1 are respectively the first, second, third, fourth information outputs of the third block of selection 5. Fifth, sixth, seventh, the eighth information outputs of the key are respectively the first, second, third, fourth information inputs of the comparison unit 5.2. The second control input of the totalizing counter 5.3 is the first control input of the selection block 5. The third control input of the totalizing counter 5.3. is the input of cyclic synchronization and the second control input of the selection block 5.3. The first control output of the comparison unit 5.2 is connected to the first control input of the totalizing counter 5.3. and at the same time is the first control output of the third selection block 5. The second control output of the comparison unit 5.2 is the second control output of the selection block 5. The first, second control outputs of the totalizing counter 5.3 are connected respectively to the first, second control inputs of the key 5.1.

 The key 5.1 shown in FIG. 13, is intended to select an input stream processing path in accordance with the algorithm of the protocol used. It consists of inverters 5.1.1 and 5.1.2, LE OR 5.1.3 and 5.1.4, drivers 5.1.5 and 5.1.6. The first control input LE OR 5.1.3 is combined with the control input of the inverter 5.1.2, and their combination is the first control input of the key 5.1. The control input of the inverter 5.1.1 is combined with the first control input of the LE OR 5.1.4, and their combination is the second control input of the key 5.1, the control inverse output of the inverter 5.1.1 is connected to the second control input of the LE OR 5.1.3, the control output of which is connected to control input of the driver 5.1.5, the control inverse output of the inverter 5.1.2 is connected to the second control input of the LE OR 5.1.4, the control output of which is connected to the control input of the driver 5.1.6. The first, second, third, fourth information inputs of the drivers 5.1.5 and 5.1.6 are combined and are respectively the first, second, third, fourth information inputs of the key 5.1. The first, second, third, fourth information outputs of the driver 5.1.5 are respectively the first, second, third, fourth information outputs of the key 5.1. The first, second, third, fourth information outputs of the driver 5.1.6 are, respectively, the fifth, sixth, seventh, eighth information outputs of the key 5.1.

 The comparison block 5.2 shown in FIG. 14, is designed to extract the received information from the input data stream and generate, depending on the result of the corresponding code at the output. It consists of a scheme for comparing two four-digit numbers 5.2.1. The first, second, third, fourth information inputs of the comparison circuit 5.2.1 are respectively the first, second, third, fourth information inputs of the comparison block 5.2. The first, second, third, fourth inputs of the comparison circuit 5.2.1 are installation inputs for recording the source data. The first, third control outputs of the comparison circuit 5.2.1 are combined, their combination is the second control output of the comparison unit 5.2. The second control output of the comparison circuit 5.2.1 is the first control output of the comparison unit 5.2.

 Summing counter 5.3 shown in FIG. 15, is designed to control the key 5.1, depending on the control commands received at its input. It consists of trigger 5.3.1. The first, second control inputs of trigger 5.3.1 are respectively the first, second control inputs of the totalizing counter 5.3. The first, second control outputs of trigger 5.3.1 are, respectively, the first, second control outputs of the totalizing counter 5.3.

 The driver circuit 5.1.5, 5.1.6 is known and described in the manual of Maltsev P.P. Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 87, fig. 2.74.

 A comparison scheme for two four-digit numbers 5.2.1 is known and described in the reference book by Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 83, fig. 2.71.

 The trigger circuit 5.3.1 is known and described in the reference book by Maltsev P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 49, fig. 2.32.

 The first decryptor unit 6 shown in FIG. 16, is intended to select the input stream by the type of response frames. Depending on the type of incoming response signal, it generates a control signal at one of its outputs. It consists of a decoder 6.1, inverters 6.2 and 6.3, LE I 6.4. The first, second, third, fourth information inputs of the decoder 6.1 are respectively the first, second, third, fourth information inputs of the decoder unit 6. The first control output of the decoder 6.1 is connected simultaneously to the control input of the inverter 6.2 and to the second control input of the LE And 6.4. The second control output of the decoder 6.1 is connected simultaneously to the control input of the inverter 6.3 and to the first control input of the LE AND 6.4. The control inverse output of the inverter 6.2 is the first control output of the decoder unit 6, the control inverse output of the inverter 6.3 is the second control output of the decoder unit 6, the control output of LE AND 6.4 is the third control output of the decoder unit 6.

 The scheme of such a decoder 6.1 is known and described in the reference book of Maltsev P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 42, fig. 2.25.

 The second decoding unit 7 shown in FIG. 17, has the same purpose as the block decoder 6 and consists of a decoder 7.1, inverters 7.2 and 7.3, LE AND 7.4. The first, second, third, fourth information inputs of the decoder 7.1 are the first, second, third, fourth information inputs of the decoder unit 7. The first control output of the decoder 7.1 is connected simultaneously to the control input of the inverter 7.2 and to the second control input of the LE AND 7.4. The second control output of the decoder 7.1. connected simultaneously to the control input of the second inverter 7.3 and to the first control input of the LE "I" 7.4. The control inverse output of the inverter 7.2 is the first control output of the decoder unit 7, the control inverse output of the inverter 7.3 is the second control output of the decoder unit 7, the control output of LE AND 7.4 is the third control output of the decoder unit 7.

 The third decoding unit 8 shown in FIG. 18, has the same purpose as the decoder units 6 and 7. It consists of the decoder 8.1, LE OR NOT 8.2, LE AND 8.3., Inverter 8.4. The first, second, third, fourth information inputs of the decoder 8.1 are the first, second, third, fourth information inputs of the decoder unit 8. The first control output of the decoder 8.1 is connected simultaneously to the first control input of the LE OR NOT 8.2 and to the first control input of the LE AND 8.3. The second control output of the decoder 8.1 is connected simultaneously to the second control input of the LE OR NOT 8.2 and to the second control input of the LE And 8.3. The third control output of the decoder 8.1 is connected simultaneously to the third control input of the LE OR NOT 8.2 and to the third control input of the LE "AND" 8.3, the fourth control output of the decoder 8.1 is connected simultaneously to the fourth control input of the LE OR NOT 8.2 and the fourth control input of LE AND 8.3. The fifth control output of the decoder 8.1 is connected to the control input of the inverter 8.4. The control inverse output of the LE OR NOT 8.2 is the first control output of the decoder unit 8, the control output of the LE AND 8.3 is the second control output of the decoder unit 8, the control inverse output of the inverter 8.4 is the third control output of the decoder unit 8.

 The schemes of decoders 7.1, 8.1 are known and described in the reference book of Maltsev P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 42, fig. 2.25.

 The totalizing counter 9 shown in FIG. 19, is intended for counting a predetermined time interval determined by the rules of organizing a data transfer protocol between the command and the response to it, and in case of exceeding its formation of the control signal. It consists of LE OR 9.1, one-shot 9.2, binary-decimal counter 9.3. The first, second control inputs of the LE OR 9.1 are respectively the first, second control inputs of the summing counter 9. The control output of the LE OR 9.1 is connected to the control input of the single-shot 9.2, the control output of the single-vibrator 9.2 is connected to the first control input of the binary decimal counter 9.3. The second control output of the binary decimal counter 9.3 is the third control output of the summing counter 9. The control output of the binary decimal counter 9.3 is the control output of the summing counter 9.

 The binary-decimal counter and one-shot used are known, see the Reference Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 65, fig. 2.52 and p. 90, fig. 2.79.

 The totalizing counter 10 shown in FIG. 20, is intended for counting a predetermined time interval determined by the rules of organizing a data transfer protocol, during which the exchange was carried out according to the protocol rules, and there were no failures. In this case, the summing counter generates a control signal. It consists of an inverter 10.1, LE OR 10.2, a binary-decimal counter 103. The control input of the inverter 10.1 is the second control input of the totalizing counter 10, the control inverse output of the inverter 10.1 is connected to the second control input of the LE OR 10.2. The first control input of the LE OR 10.2 is the first control input of the summing counter 10, the control output of the LE OR 10.2 is connected to the first control input of the counter 10.3. The control output of the counter 10.3 is the control output of the totalizing counter 10. The second control input of the counter 10.3 is the third control input of the totalizing counter 10.

 The scheme of such a counter 10.3 is known, see the reference book Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. from. 65, fig. 2.52.

 The totalizing counter 11 shown in FIG. 21, is designed to track the number of SOH * frames transmitted without confirmation (no more than 256), otherwise it generates a control signal. It consists of an asynchronous counter 11.1, the first, second control inputs of which are respectively the first, second control inputs of the totalizing counter 11. The control output of the asynchronous counter 11.1 is the control output of the totalizing counter 11.

 The counter circuit 11.1 is known, see Shilo V.L. Popular Digital Chips: A Guide. - M.: Radio and communications, 1987. - 352 p.: Ill. - Massive radio library. Issue 1111, p. 241, fig. 2.46.

 The search strategy register 13 is a decoder designed to select the necessary algorithm for the operation of the entire information retrieval device. The scheme of such decoders is known and described in the reference book Maltseva P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994. - 240 pp., ill. on p. 42, fig. 2.25.

 The display unit 14 is used to display the decision on the type of protocol used. It can be performed using a decoder. The schemes of such decoders are known and described in the reference book by Maltsev P.P., Dolidze N.S., Kritenko M.I. et al. - M.: Radio and Communications, 1994.-240 pp., ill. on p. 42, fig. 2.25.

 The generator used is known and described (Shilo V.L. Popular digital microcircuits: Reference book. - M.: Radio and communications, 1987. - 352 pp .: - Mass radio library. Issue 1111, p. 213, Fig. 2.20, a )

 The specified device operates as follows. The information retrieval device is designed to detect in the digital stream transmitted in the communication channel messages corresponding to a protocol of the DDCMP type.

The DDCMP procedure is designed for synchronous operation over duplex and half-duplex connections established over dial-up and dedicated duplex channels, as well as point-to-point or multipoint networks. The main thing for the DDCMP procedure is that in the frame format intended for the transfer of information, two areas are allocated: the control area and the information area. The protocol contains three types of frames: information, control, serving. In the control area of each type of frame there is a position reserved for the transmission of one control byte used to indicate and recognize the type of frame (information, control, serving). The next two bytes of the control area of the information frame are used to indicate the length (in bytes) of the information area of the frame (14 first bits) and control the communication channel (last 2 bits). The two subsequent bytes of the control frame of the control frame (hereinafter, for the control frame, we will only talk about the control area, since there is simply no information area in it) are used for the reason code for the failure, if any (the first 8 bits) and for indicating the type of control frame ( last 8 bits). Following them, 3 bytes respectively carry information on the returned number of the information received from the remote station (this number is a confirmation signal for the receipt of the corresponding frame by the given station), the serial number of the transmitted information frame and the address of the station to which this information frame is sent (in a multipoint connection). In the control frame, 3 bytes denotes the number of the confirmed or requested frame, 4 bytes are zero (not used), 5 bytes are used similarly with the information frame. Following the header bytes and the two verification bytes corresponding to them, information bytes are located in the information area, followed by two verification bytes corresponding to this area. The DDCMP procedure is responsible for maintaining synchronization across frames and messages (placed in a single frame). For this, 2 synchronization bytes (SYN) are used, sent at the beginning of each frame. The receiver, having accepted two characters of frame synchronization (SYN), expects one of the three opening characters of the frame - SOH, ENQ, DLE ASCII code, indicating the type of frame format - information, control, serving, respectively. The signs of the ASCII code, DDCMP protocol, used to organize the search procedure in the claimed information retrieval device, indicate the following:
SOH, ENQ, DLE - ASCII code characters indicating the type of frame format;
TYP - type of control frame (ACK, NAK, REP, STRT, STACK);
ACK - positive receipt for the received frame;
NAK - negative receipt for the received frame;
REP - receipt of the request for the last transmitted frame;
STRT - receipt of the beginning of the establishment of the connection;
STSCK - receipt of confirmation of the transition of the initiating station to the working phase;
ANY - any frame not defined by the exchange procedure.

 In the family of communication protocols, the DDCMP protocol is used to transmit data in computer networks. In total there are more than two hundred varieties of protocols, one of which is the DDCMP protocol, which differs from other protocols in a specific set of service and information messages (frames) and the rules for exchanging them with corresponding stations during a data transfer session.

 In a number of technical problems in the field of telecommunications, the problem of finding information of a certain type in the general information flow arises, which can be solved by static (analog), logical (prototype) methods or methods of the theory of pattern recognition (the proposed device implements the principles of the theory of parsing), described in the book of J. Tu. , R. Gonzalez. Pattern recognition principles. Per. from English - M.:, 1978, p. 411.

 The essence of the theory of syntactic analysis is as follows: the described object is represented as a composition of simpler submanifolds. To represent the structural information contained in each image, i.e. to describe the image using simpler submanifolds, each of which is in turn described using even simpler submanifolds, etc., and a syntactic approach was proposed. This approach reveals an analogy between the structure of images and the syntax of languages. Images are defined as a construction, connected in various ways from sub-images in the same way that phases and sentences are built using a combination of words, and words are built using a combination of letters. In order for this approach to be useful, the selected simplest sub-images, called "image primitives", should be recognized much more easily than the images themselves. A "language" that provides a structural description of images in the terminals of a set of image primitives and operations for combining them is sometimes called the "image description language". The rules governing the union of primitives in images are usually set by the so-called "grammar" of the image description language. After each image primitive is identified, the recognition process is completed by performing parsing, i.e. parsing a “sentence” describing an object. This procedure determines whether or not it is syntactically (or grammatically) correct with respect to a given grammar.

 A linguistic pattern recognition system can be considered as consisting of three main parts, namely, a pre-processing unit, an object description or presentation unit, and a parsing unit. The preprocessing unit performs, firstly, encoding and approximation of the object, and secondly, filtering, restoration and amplification. The source object is initially encoded or approximated so that it is convenient for further processing. Then, to improve the quality of encoded (or approximated) objects, filtering, restoration, and / or amplification methods are used. It is usually assumed that at the output of the pre-processing unit, objects of sufficiently "good quality" are obtained. Then each pre-processed object is presented in the form of a language-like structure (for example, in the form of a line or graph). This process of representing an object consists, firstly, of its segmentation and, secondly, of the allocation of primitives (attributes). To represent an object through its subobjects, it is necessary to segment this object and at the same time identify (or highlight) its primitives and relations between them. In other words, each pre-processed object is segmented into subobjects and object primitives based on predetermined syntax operations or union operations; in turn, each subobject is identified using this set of primitives. Now each object is represented by a set of primitives with certain syntactic operations. The decision on whether the (object) representation is syntactically correct, i.e. whether it belongs to the class of objects described by this syntax (or grammar) will be accepted by the "syntax analyzer" or "parser". By performing parsing, the analyzer can usually produce a complete syntactic description of the object in terms of parsing, if only the representation of the object is syntactically correct. Otherwise, the object is either rejected or analyzed already on the basis of other given grammars, which, upon proposal, describe other possible classes of the objects in question. The conceptually simplest way of recognition is probably the “match-to-standard" method. A string of primitives representing the source object is compared to a string of primitives representing each prototype, or a reference object. Based on the selected “match” or “similarity” criterion, the source object is credited to the same class as the prototype object, which “best” corresponds to the source object. To obtain a grammar describing information about the structure of the studied class of objects, you need a grammar input device that can output a grammar based on a given set of training objects in a language-like representation. This is an analogue of the “learning” process. Currently, this part of the work is carried out by the designer.

 Unlike known devices that provide correct recognition of information with some probability, depending on various conditions, the proposed device either gives an unambiguous solution (with sufficient information), or generates a denial of the solution (if there is insufficient information). A useful effect is to obtain an unambiguous decision on the presence (or absence) of messages of a certain type in the general information flow.

 The recognized protocol is described in the book Protocols of computer networks. Directory. Ed. Mizina I.A., Kuleshova A.P. - M.: Radio and Communications, 1990, 503 p. A frame is understood to mean a protocol data unit containing control information (header) and actually transmitted data.

 The actual algorithm for the operation of the DDCBMP protocol is as follows: FIG. 21: a station wishing to initiate a data transmission channel (Efficiency) transmits a command (frame) STRT * to the channel (the symbol * denotes commands, the symbol # denotes responses); if the remote station is ready to enter information exchange mode, then it transmits a response (frame) STRT #. After that, the initiating station enters the working phase and transmits the STACK * command to the remote station. If the remote station is ready to enter the working phase, then it sends the ACK # command. When a command is received with an error, the response is NAK # (incorrect frame) and the connection establishment process is repeated.

 After establishing the connection mode, the stations switch to the exchange of information, which is transmitted in the SOH * information frames. Each subsequent information frame is transmitted only after receiving an ACK # response (information frame is received correctly), if a NAK # response (incorrectly received frame) is received, a SOH # frame is retransmitted until an ACK # response is received. A transmission mode of up to 256 SOH * frames is possible without receiving an ASK # response (NAK #).

 At the end of the transmission of information frames, the last flag is set (the bit in the frame header) SELECT to "1" - this indicates the end of the transmission of one station and the invitation to transmit the correspondent, which in turn confirms the correct ACK # command and, if it has nothing, then in the frame in which the confirmation is transmitted, the SELECT flag will be set to "1". The conclusion about the end of the transfer will be made after the timeout is not received at the input of the message switch.

Search (recognition) of information is carried out using the characteristics of two groups:
qualitative features inherent in both DDCMP and a number of other types of communication protocols, which are used commands and responses;
structural features inherent only to DDCMP, which is an exhaustive finite set of sequences of allowed commands and responses.

 The proposed device that implements a method of searching for information on the indicated grounds consists in analyzing communication sessions in data transmission networks (SPD) and comparing their structure with a priori known rules for organizing data transmission using the specified protocol type. If they coincide, a decision is made that the communication session is carried out using the desired protocol type.

 The DDDCMP protocol syntax recognition method implemented in the proposed device (Fig. 22) is based on the protocol identification operation by signals of the form (ACK #, NAK #, STRT *, STRT *, STACK *, REP *, SOH *, SOH #) and type ( command, response) transmitted over the frame channel.

The protocol specification is described by the following regular grammar:
G = (V _n , V _t , P, S),
where V _n = (STRT *, STRT #, ACK #, NAK #, REP *, STACK *, SOH #, ANY #) - the set of frames provided by the protocol.

- множество правил использования команд и ответов;
V_t - (S, A, B, C, D, E, F, H) - множество возможных состояний звена управления каналом;
S - исходное состояние звена управления каналом связи.P -

- many rules for using commands and answers;
V _t - (S, A, B, C, D, E, F, H) - the set of possible states of the channel control link;
S is the initial state of the communication link control link.

The input of the information retrieval device (Fig. 1) is the first, second, third, fourth information inputs of the switch 1, to which the four-element code corresponding to the received frame (for example: STRT * - 0001, STRT # - 0010 etc.)
The switch 1 shown in FIG. 2, is designed to transmit the received signal in one of three selected directions, depending on the control signals of the search strategy register 13 received at the first, second control inputs of switch 1, connect the input stream to the information inputs of the first 3, second 4 and third 5 selection blocks .

 The reset signal generator 2 shown in FIG. 3, depending on the type of control code that arrives at its first and second control inputs from the search strategy register 13, generates reset commands that are sent to the first 3, second 4, and third 5 selection blocks.

 The first 3, second 4, third 5 blocks of selection pre-select the input stream according to the type of command.

 The first selection block 3 (Fig. 4) works as follows.

 The key 3.1 upon receipt of a control signal at its first control input connects the first, second, third, fourth information inputs, respectively, with the fifth, sixth, seventh, eighth information outputs, when a control signal arrives at the second control input of the key 3.1, its first, second, third, the fourth information inputs are connected to the first, second, third, fourth information outputs.

 Comparison block 3.2 compares the received code with the signal image STRT * stored in its memory. If the incoming code and the image of the signal match, a control signal is generated at the first control output, and when they differ, a control signal is generated at the second control output.

 The summing counter 3.3, at each signal input to its first control input, generates a control signal at the second control output, and when a control signal arrives at the second control input of the summing counter, a control signal is generated at its first control output.

 The second block selection 4 (Fig. 8) works as follows.

 The key 4.1 upon receipt of its first or second control inputs of control signals connects the first, second, third, fourth information inputs, respectively, with the fifth, sixth, seventh, eighth or first, second, third, fourth information outputs.

 The first comparison block 4.2 compares the incoming code with the STACK * signal image stored in its memory. If the incoming code and the signal image match, a control signal is generated at the first control output of the first comparison unit 4.2, and when they differ, a control signal is generated at its second control output.

 The summing counter 4.3, at each signal input to its first control output, generates a control signal at the second control output, and when the control signal arrives at the second control input of the summing counter, a control signal is generated at its first control output.

 The third block of selection 5 (Fig. 12) works as follows.

 The key 5.1 upon receipt of its first or second control inputs of control signals connects the first, second, third, fourth information inputs, respectively, with the fifth, sixth, seventh, eighth or with the first, second, third, fourth information outputs.

 Comparison block 5.2 compares the incoming code with the signal image SOH *, REP * stored in its memory. If the incoming code and the image of the signal correspond to the first control output of the comparison unit 5.2, a control signal is generated, and when they differ, the signal enters its second control output.

 The summing counter 5.3, at each signal input to its first control input, generates a control signal at the second control output, and when a control signal arrives at the second control input of the summing counter, a control signal is generated at its first control output.

 Blocks-decoders 6 - 8, which selects the input stream according to the type of response frames, depending on the type of incoming response signal form a control signal at one of its outputs, which is fed to the corresponding control input of the search strategy register 13.

 The first decoder unit 6, upon entering the first, second, third and fourth information inputs of a code corresponding to the signal STRT #, generates a control signal at its first control output, which is fed to the second control input of the search strategy register 13 when a code corresponding to the signal NAK #, a control signal is generated at the second control output, which is fed to the first control input of the search strategy register 13, when any other code is received, a control signal is generated at the third m control output to the second control input of the display unit 14.

 The second decoder unit 7, upon entering the first, second, third, fourth information outputs of the code corresponding to the ACK # signal, generates a control signal at the first control output, which is fed to the third control input of the search strategy register 13 when a code corresponding to the NAK signal is received #, a control signal is generated at the second control output, which is fed to the first control input of the search strategy register 13, and upon receipt of any other, a control signal is generated at the third control output it is the output coming to the second control input of the display unit 14.

 The third block-decoder 8 upon receipt of its first, second, third, fourth information inputs of the code corresponding to the signals ACK #, NAK #, REP #, SOH #, generates a control signal at the first control output, which is fed to the first control input of the third summing counter 11 and the third control input of the search strategy register 13, upon receipt of any other code, generates a control signal at the second output, which is fed to the second control input of the display unit 14. Upon receipt of a signal corresponding to the code SOH *, a control signal is generated at the third control output, which is fed to the second control input of the sum counter 11.

 The first totalizing counter 9 when exceeding a predetermined time defined by the rules for organizing data transmission, generates a signal fed to the first control input of the display unit 14, which generates a message about insufficient data to decide on the type of protocol. Resetting the totalizing counter occurs upon receipt of its first, second control inputs of any code combination.

 The second totalizing counter 10 at the expiration of a predetermined time determined by the rules of the organization of data transmission, generates a signal fed to the third control input of the display unit 14, which generates a message that this communication session is carried out using the DDCMP protocol. Resetting of the totalizing counter occurs only upon receipt of the first, second control inputs of the code combination (01).

 The third totalizing counter 11 ensures that the number of SOH * frames transmitted without confirmation does not exceed 256, otherwise it generates a control signal supplied to the second control input of the display unit 14.

 The register of the search strategy 13, which is a decoder, serves to select the necessary algorithm for the functioning of the entire information retrieval device. Depending on which of its control inputs a control signal has arrived, it generates a two-element code of type (01), which is fed to the first, second control inputs of summing counters 9, 10, reset signal generator 2, and the first, second control inputs of switch 1. If there is a control signal at the first control input of the search strategy register 13, code 01 is generated at its output, while the first, second, third, fourth information inputs of switch 1 are connected to its first, second, third, fourth information output, the block of the shaper of signals of reset 2 generates a control signal supplied to the control input of the first 4 block selection, the summing counters 9, 10 are reset. If there is a control signal at the second control input of the search strategy register 13, a code (10) is generated at its output, while the first, second, third, fourth information inputs of the switch 1 are connected to its fourth, fifth, sixth, seventh information outputs, the signal conditioning unit reset 2 generates a control signal supplied to the control input of the second 3 selection block, the first totalizing counter 9 is reset, and the second totalizing counter 10 continues to work. If there is a control signal at the third control input of the search strategy register 13, a code (11) is generated at its outputs, while the first, second, third, fourth information inputs of the switch 1 are connected to its ninth, tenth, eleventh, twelfth information outputs, the signal conditioning unit reset 2 generates a control signal supplied to the control input of the third 5 selection block, the first totalizing counter 9 is reset, and the second totalizing counter 10 continues to work.

 The totalizing counter 11, which serves to count information frames (up to 256) transmitted without confirmation, is reset to zero when it receives a control signal at its first control input, and when it receives a control signal to its second input, it stores it in memory and generates a control signal when it is full at its output, which is fed to the second control input of the display unit 14.

 The display unit 14, which serves to display the decision made on the type of protocol used, when a signal is received at the first control input, generates a message about insufficient data for deciding on the type of protocol, when a signal arrives at its second control input, it generates a message that this session is carried out with using a protocol other than DDCMP, when a signal arrives at the third control input, it generates a message stating that this communication session is using the DDCMP protocol. When a signal is received at any of the control inputs of the display unit 14, a control signal is generated at its output, which arrives at the first control input of the search strategy register 13.

 Clock pulses for the operation of the summing counters 9, 10 come from the clock generator 12.

 Pulses of cyclic synchronization come from the device determining the type of frame.

 Thus, the advantages of this device are the possibility of real-time operation, close to zero probability of skipping (in the case of a priori reliable information about the protocol), ease of implementation and modification for any dialog-type communication protocol. The probability of false alarms depends on the degree of similarity of the rules of the desired protocol type with the rules of other protocols, the operation of which is possible in the observed channel and is proportional to the likelihood that the correspondents during the session, according to the rules of another protocol, identical to the rules of the desired protocol, have a full set of correct frames subject to the correct recognition of the type and type of frames.

Claims (2)

 1. An information retrieval device containing first, second, third totalizing counters and a search strategy register, characterized in that a switch, a reset signal generator, first, second and third selection blocks, first, second and third decoders, a pulse generator, a block are additionally introduced indications, the first, second, third and fourth information outputs of the switch are connected respectively to the first, second, third and fourth information inputs of the first block of selection, the fifth, sixth, seventh, eighth information the switch outputs are connected respectively to the first, second, third, fourth information inputs of the second selection block, the ninth, tenth, eleventh and twelfth information outputs of the switch are connected respectively to the first, second, third, fourth information inputs of the third selection block, the first, second, third control the outputs of the reset signal generator are connected to the first control inputs of the first, second, third selection blocks, respectively, the second control inputs of the first, second, third its selection blocks are cyclic synchronization inputs, the first, second, third and fourth information outputs of the first selection block are connected to the corresponding information inputs of the first decoder, the control outputs of the first and second selection blocks are combined with the second control output of the third selection block, the third control output of the first and second decoders, the second control output of the third decoder, the control output of the third totalizing counter and are connected to the second control input display unit, the first, second, third, fourth information outputs of the second selection block are connected to the corresponding information inputs of the second decoder, the first, second, third, fourth information outputs of the third selection block are connected to the corresponding information inputs of the third decoder, the first control output of the third selection block is combined with the third control output of the third decoder and connected to the second control input of the third totalizing counter, the first control output p the first decoder is connected to the second control input of the search strategy register, the second control output of the first decoder is combined with the second control output of the second decoder, with the control output of the display unit and connected to the first control input of the search strategy register, the first control output of the second decoder and the first control output of the third decoder combined and connected to the first control input of the third totalizing counter and the third control input of the search strategy register the output output of the first totalizing counter is connected to the first control input of the display unit, the control output of the second totalizing counter is connected to the third control input of the display unit, the generator output is connected simultaneously to the third control input of the first totalizing counter and the third control input of the second totalizing counter, the first and second control outputs register search strategies are connected respectively with the first, second control inputs of the first, second totalizing counter, form I reset signals and the first, second switch control inputs, first, second, third, fourth information inputs of the switch are input devices.  2. The device according to claim 1, characterized in that the first selection block consists of a key, a comparison unit, a totalizing counter, the first, second, third, fourth information inputs of the key are respectively the first, second, third, fourth information inputs of the first selection block, the first, second, third, fourth information outputs of the key are respectively the first, second, third, fourth information outputs of the first selection block, the second control output of the comparison unit is the control output of the first block and the selection, the fifth, sixth, seventh, eighth information outputs of the key are connected respectively to the first, second, third, fourth information inputs of the comparison unit, the first control output of the comparison unit is connected to the first control input of the totalizing counter, the first, second control outputs of which are connected respectively to the first, second control inputs of the key, the second control input of the summing counter is the first control input of the selection block, the third control input of the summing counter is tsya second control input selection unit - input frame synchronization.

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