RU21102U1 - RELATIVE SELECTOR - Google Patents

Abstract

A relator selector containing n relators, each of which is made in the form of a differential comparator, the non-inverting and inverting inputs of which form the first and second comparator inputs of the relator, the first comparator inputs of the first, ..., n-th relators are respectively the first, ... ., the n-th information inputs of the relator selector, the (n + 1) -th information input of which is the second comparator input of the first relator, characterized in that n adders are introduced into it, and the first and third are in each relator These are the keys made by the closing, the second and fourth keys made by the opening, and the Boolean element is EXCLUSIVE OR, the first input of which is connected to the output of the differential comparator, the second input is the control input of the relator, and the output is connected to the control input of four keys, the key inputs are the corresponding switching inputs of a relator, the first and second outputs of which are formed respectively by the combined outputs of the first, second and combined outputs of the third, fourth keys, the first and second the first comparator inputs of each relator are connected respectively to its first and second switching inputs, the first relay output is connected to the second switching input of the (i + 1) th relay, and the first output of the n-th relay is the information output of the relator selector, the first input and output i- of the adder are connected respectively to the second output of the i-th and fourth switching input of the (i + 1) -th relator, and the first input and output of the nth adder are connected respectively to the second output of the nth relator and the identifying output of the relator

Description

RELATIVE SELECTOR

The utility model relates to automation and analog computing and can be used to build functional units of analog computers, automatic regulation and control tools, analog processors, etc.

Relative selectors are known (see, for example, Fig. 4 in the book Volgin LI. Complementary algebra and modeling of neural structures. Tallinn: Academy of Sciences of Estonia, 1993. 48c.), Which contain both relators and perform selection and address identification of the largest of several analog signals X, ..., X „+1.

the reason that impedes the achievement of the technical result indicated below when using well-known relevant selectors is limited functionality due to the fact that, for tuning to perform selection and address identification of the smallest of the signals i, ..., l; „+ 1 requires a change selector circuits.

The closest device of the same purpose to the claimed utility model in terms of features is the prototype, the relator selector (A.S. USSR 1262531, class G06G7 / 25, 1986), performing the selection and address identification of the largest of the analog signals l; 1, ..., l: „+ 1 and containing; n relators, each of which is made in the form of a differential comparator, non-inverting and inverting inputs of which form the first and second comparator inputs of the relator, respectively.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality, due to the fact that to configure the selection and address identification of the smallest of the signals X1, ..., a change in the selector circuit is required (interchange of the comparator inputs of the relators), as well as the fact that +1 identifying signals are required to provide an identifying property.

The technical result of the utility model is the expansion of functionality by ensuring the selection and address identification of the largest or smallest of several analog signals without changing the selector circuit, as well as by providing an identifying property using a single identifying signal.

The specified technical result in the implementation of the utility model is achieved by the fact that in a relator selector containing n relators, each of which is made in the form of a differential comparator, the non-inverting and inverting inputs of which form the first and second comparator inputs of the relator, the first comparator inputs of the first, ... , “- GO relators are respectively the first, ..., i-th information inputs of the relator selector, (+ 1) -th information input of which is the second comparator input of the first a relator, the peculiarity lies in the fact that n adders are introduced into it, and in each relator - the first and third keys made by closing, the second and fourth keys made by disconnecting, and the Boolean element excludes OR, the first input of which is connected to the output of the differential comparator, the second input is the relator control input, and the output is connected to the control input of four keys, the key inputs are the corresponding switching inputs of the relator, the first and second outputs of which are formed respectively union of outputs of the first, second, and outputs the combined third, fourth key, the first and second inputs of each comparator relator respectively connected with its first and second the switching

/. ::

inputs, the first output of the 1st relay 1, and -11 of the relator is connected to the second switching input of the (/ + 1) -th relay, and the first output of the "-th relay is the information output of the relator selector, the first input and output of the / -th adder are connected respectively, with the second exit of r and

the fourth switching input of the (/ + 1) -th relator, and the first input and output of the ith adder are connected respectively to the second output of the «relay and the identifying output of the relator selector, the identifying input and control input of which are formed by the combined fourth switching input of the first relay , the second inputs of all adders and the combined control inputs of all relators, the third switching inputs of which are connected to the bus of zero potential.

The analysis of the prior art by the applicant, including a search by patent and scientific and technical sources of information, and the identification of sources containing information about analogues of the claimed utility model, allowed to establish that the applicant did not find an analogue characterized by features identical to all the essential features of the claimed utility model. The definition from the list of identified analogues of the prototype, as the closest in the set of essential features of the analogue, allowed us to identify the set of essential distinguishing features in relation to the applicant’s technical result in the claimed device, set forth in the utility model formula. Therefore, the claimed utility model meets the condition of novelty.

The drawing shows a diagram of the proposed relator selector.

The relator selector contains n relators 1, ..., „and n adders 21 ,, .., 2„. Each relator contains a comparator 3, connected to the first input of the Boolean element by exclusive OR 4, the second input of which is the input of the relator control, and the output is connected to the control input of the first key 5i, made closing, the second key 52, made disconnecting, the third key 5h, made closing, and the fourth key 64, made disconnecting, the inputs of the keys 5, ..., 54 are the corresponding switching inputs of the relator, the first and second outputs of which are formed respectively by the combined outputs 5.52 key odes and combined key outputs

5h, 54, the non-inverting and inverting inputs of the comparator 3 are respectively the first and second comparator inputs of the relator. The first comparator inputs of the relators 11, ..., 1 „are respectively the first, ..., w-th information inputs of the relator selector, the (" +1) -th information input of which is the second comparator input of the relator 1, the first and second comparator inputs of each the relator are connected respectively to its first and second switching inputs, the first output of the relator 1, (zl, n-lj is connected to the second switching input of the relator l, + i, and the first output of the relator 1 „is the information output Z | of the relator selector, the first input and total output a 2 are connected respectively to the second output of the relator 1 / and the fourth switching input of the relator l, + i, and the first input and output of the adder 2 „are connected respectively to the second output of the relator 1“ and the identifying output 2 of the relational selector, which identifies the input and control input of which are formed respectively by the combined fourth switching input of the relay 1 second inputs of all adders and the combined control inputs of all relators, the third switching inputs of which are connected to the zero sweat bus tial.

The work of the proposed relational selector is as follows. The first, ..., ith and (and + 1) th information inputs of the selector are fed respectively analog information signals (voltages) d: „, ..., l; 1 and l;„ + 1, and on it the identifying input records the identifying analog signal (voltage) y, When / О (/ еl0, l | -signal at the input of the selector control) and (a and b are signals

respectively, at the first and second comparator inputs of the relator) or at / 1 and the keys 5i and 5з are closed, the keys 52 and 64 are open, and at f 1 and or at / О and (we have the opposite picture, that is, the signal / changes the switching logic of the switching inputs In the prototype, a similar change is achieved by rebuilding its circuit

(interchange of comparator inputs of relators). Thus, the operations reproduced by the proposed relational selector are determined by the expressions:

x for (x, ...,

Z,, (1)

x „+ for d:„ + 1 ext (xi, .. ,, x „)

y for (x, .. ,, x) 2y for (x, ...,

(u + V) y for x „+ 1 ext (xi, ...,) where for / 0; at / 1. According to (1), at / 0, the largest is selected, and at / 1, the smallest of the signals Xi, ..., while, according to (2), the signal level at the output Zi is proportional to the address k of the selected signal x .

The above information allows us to conclude that the proposed relator selector has a wider functionality compared to the prototype, as it provides selection and address identification of the largest or smallest of several analog signals without any circuit changes, and also provides its own identifying property using one identifying signal.

Thus, the above information indicates the following conditions are met when using the claimed device:

-a tool embodying the claimed device in its implementation, is intended for use in industry, namely in the field of automation and analog computing as a functional unit of analog depiction machines, automatic regulation and control, analog processors, etc .;

the possibility of its implementation using the means and methods described in the application or known up to the priority date;

- a tool that embodies the claimed utility model in its implementation, is able to ensure the achievement of the perceived by the applicant technical result.

Therefore, the claimed utility model meets the condition of industrial applicability.

Claims (1)

A relator selector containing n relators, each of which is made in the form of a differential comparator, the non-inverting and inverting inputs of which form the first and second comparator inputs of the relator, the first comparator inputs of the first, ..., n-th relators are respectively the first, ... ., the n-th information inputs of the relator selector, the (n + 1) -th information input of which is the second comparator input of the first relator, characterized in that n adders are introduced into it, and the first and third are in each relator These are the keys made by the closing, the second and fourth keys made by the opening, and the Boolean element is EXCLUSIVE OR, the first input of which is connected to the output of the differential comparator, the second input is the input of the relator control, and the output is connected to the control input of the four keys, the key inputs are the corresponding switching inputs of a relator, the first and second outputs of which are formed respectively by the combined outputs of the first, second and combined outputs of the third, fourth keys, the first and second minutes relator comparator inputs each respectively connected with its first and second switch input, a first output

the relay is connected to the second switching input of the (i + 1) -th relay, and the first output of the nth relay is the information output of the relator selector, the first input and output of the i-th adder are connected respectively to the second output of the i-th and fourth switching input (i +1) th relators, and the first input and output of the nth adder are connected respectively to the second output of the nth relator and the identifying output of the relator selector, the identifying input and control input of which are formed respectively by the combined fourth switch lnym relator input of the first, the second inputs of the adders and the combined control inputs of all relators, third switching inputs of which are connected to zero potential bus.