RU2073225C1 - Device for checking shaft of internal combustion engine for uniform rotation - Google Patents

Abstract

FIELD: mechanical engineering; testing of internal combustion engines. SUBSTANCE: device has speed pickup 1, synchronization pickup 2, pulse generator 3, shapers 4,5,6,7,8, frequency dividers 9, control unit 10, counters 11,12,13,14,15,16,17 and 18, switches 19 and 20, on-line storages 21 and 22, registers 23 and 24, comparators 25 and 26, calculator 27 and indicators 28 and 29. Device provides continuous measurement of time intervals during which engine crankshaft turns through known discrete angle within the limits of engine operation cycle with synchronization of beginning of measurement with working stroke in definite engine cylinder simultaneously recording measurands in on-line storages and calculating shaft rotation nonuniformity coefficient within engine operating cycle and torque variation period coefficient. Device can be used for checking speed of engine. EFFECT: enhanced reliability of checking. 9 cl, 10 dwg

Description

 The invention relates to measuring equipment and can be used in the process of diagnosing the technical condition of internal combustion engines, their refinement and testing.

 A device for measuring the unevenness of the shaft speed, comprising a speed sensor, amplifiers, an ignition pulse generator (injection moment) of a specific engine cylinder, a unit for comparing the actual and predetermined shaft speed, coincidence triggers, coincidence elements, start trigger, inhibit trigger, reference generator frequencies, synchronization trigger, operating mode selection block, buffer counters, reset and write signal generator, switch, address counter, storage device and bl indicating to [1] It can measure up to 256 time interval values between adjacent pulses of the speed sensor shaft with subsequent recording the measurement results into the RAM.

 The disadvantage of this device is the great complexity of determining the unevenness of rotation due to the need to output the measurement results from the random access memory, determining the maximum, minimum and average values of the rotational speed of the crankshaft of the engine within one or more cycles of its operation and calculating the average value of the coefficient of unevenness of rotation.

 The closest technical solution, selected as a prototype, is a device for monitoring the uneven rotation of the shaft of an internal combustion engine, comprising a speed sensor, shapers, counter, registers, comparison elements, a pulse generator, a computer, an indicator, and "And" elements [2] Device allows you to sequentially measure the repetition periods of the pulses of the speed sensor with simultaneous selection and storing of their maximum and minimum values, calculate from these values and the period Personally indicate the value of the coefficient of unevenness of rotation, as well as the values of the maximum and minimum speeds of rotation within a given number of angular intervals of rotation of the crankshaft.

 The disadvantages of the known device are the low accuracy of the control of uneven rotation and its lack of functionality. The low accuracy of monitoring the unevenness of rotation is explained by the distortion of the measured information due to the use of a single counter in the device to form the equivalent of the shaft rotation time by a certain angle. The temporary equivalents of the shaft rotation formed by the known discrete angle formed in this case will differ from their actual values, since the beginning of the measurement of the time interval occurs with a delay by the value of the duration of the zeroing pulse from the output of the second shaper. The average value of the speed required to calculate the coefficient of unevenness of rotation is determined by the half-sum of the maximum and minimum values of the speed, which does not correspond to its actual average value, which should be determined as the arithmetic mean of the speed for a certain number of angular intervals. In addition, the process of measuring the repetition periods of pulses from a speed sensor is not synchronized with the working stroke of a specific engine cylinder, and the entire array of current values of these periods is not recorded anywhere, which does not allow determining the coefficient of uneven rotation sequentially for individual cylinders within one or several operation cycles engine and, consequently, evaluate their technical condition. The control of rotation unevenness is carried out without simultaneous control of the engine speed mode, although rotation unevenness also changes with its change. All this narrows the functionality of the device.

 The objective of the invention is to improve the accuracy of monitoring the unevenness of rotation and expanding the functionality of the device by more accurately determining the average value of the rotational speed, the ability to determine the unevenness of rotation of individual cylinders and control the speed of the engine.

 This object is achieved by the fact that in the known device for controlling uneven rotation of the shaft of an internal combustion engine, comprising a speed sensor, first and second formers, a first counter, first and second registers, first and second comparison elements, a pulse generator, a calculator and a first indicator, moreover, the first output of the speed sensor is connected to the input of the first driver, the direct information output of the first register is connected to the first input of the calculator and the first input of the first element comparison, and the direct information output of the second register is connected to the second input of the calculator and the first input of the second comparison element, the output of the calculator is connected to the input of the first indicator, the synchronization sensor, the third, fourth and fifth drivers, the frequency divider, the control unit, the second, third, fourth , fifth, sixth, seventh and eighth counters, first and second switches, first and second random access memory and a second indicator, and the output of the synchronization sensor is connected to the input of the third form the generator, the output of which is connected to the first input of the control unit, the second output of the speed sensor is connected to the input of the second driver, the output of which is connected to the second input of the control unit, the output of the first driver is connected to the third input of the control unit and the first input of the fifth driver, the output of the pulse generator is connected with the fourth input of the control unit and the input of the frequency divider, the first output of which is connected to the second input of the fifth driver, the second output to the fifth input of the control unit and the first ode of the fourth driver, the first output of the control unit is connected to the counting input of the fifth counter, the second output of the control unit is connected to the counting input of the first counter, the information output of which is connected to the first input of the first switch, the third output of the control unit is connected to the second input of the first switch, the fourth output of the block the control is connected to the counting input of the second counter, the information output of which is connected to the third input of the first switch, the fifth output of the control unit is connected to the second the input of the fourth shaper, the first and second outputs of which are connected to the zeroing inputs of the first and second counters, the third and fourth outputs to the first inputs of the first and second random access memory, respectively, and the fifth and sixth outputs to the zeroing inputs of the third and fourth counters, respectively, the sixth output the control unit is connected to the counting input of the third counter, the information output of which is connected to the first input of the second switch, the seventh output of the control unit is connected to the second input of the second switch, the eighth output of the control unit is connected to the counting input of the fourth counter, the information output of which is connected to the third input of the second switch, the ninth and tenth outputs of the control unit are connected to the counting inputs of the sixth and seventh counters respectively, the information outputs of the first and second switches are connected to the second inputs of the first and second random access memory, respectively, the third inputs of which are connected to the information outputs respectively and sixth counters, the first and second outputs of the fifth shaper are connected respectively to the counting input and the zeroing input of the eighth counter, the output of which is connected to the input of the second indicator, the information output of the first random access memory is connected to the information outputs of the first and second registers and second inputs of the first and second elements comparisons, the outputs of which are connected to the synchronizing inputs of the first and second registers, respectively, and the information outputs of the seventh counter and the second perativnogo storage device respectively to third and fourth inputs of the calculator.

 The pulse generator contains the first, second and third logic elements “2I-NOT”, resistors, a capacitor and a quartz resonator, the inputs and outputs of the first and second logic elements are interconnected via resistors, the output of the first logic element is connected through the capacitor to the inputs of the second logic element the output of which is connected to the inputs of the third logic element and through a quartz resonator with the inputs of the first logic element, and the output of the third logic element is the output of the pulse generator.

 The first and second shapers contain each first, second and third capacitors, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh resistors, the first, second and third operational amplifiers, the first, second and third diodes , a zener diode and an inverter, and the direct input of the first operational amplifier is connected through a series-connected first resistor and first capacitor to a source of zero potential, and the point of their connection is the input of each driver, the inverse input of the first operation The amplifier is connected through a second resistor to a source of zero potential, the first power input of the first operational amplifier is connected to a positive voltage source, the second power input to a negative voltage source, and the output through a third resistor is connected to its inverse input and through a sixth resistor with a direct input of the second operating amplifier, series-connected fourth and fifth resistors are connected respectively to a source of positive voltage and a source of zero potential, and then the connection point is connected through the seventh resistor to the inverse input of the second operational amplifier, the first power input of which is connected to a positive voltage source, the second power input to a source of zero potential, and the output of the second operational amplifier is connected through the eighth resistor to its direct input, which is connected to the cathode the first diode, the anode of which is connected to a source of zero potential, the output of the second operational amplifier through series-connected second capacitor, the ninth and tens the resistors are connected to the inverse input of the third operational amplifier, the connection point of the ninth and tenth resistors is connected through the second and third diodes and the third capacitor to the zero potential source, the cathode of the second diode connected to the anode of the third diode, the direct input and the correction input of the third operational amplifier are connected to a source of zero potential, the first power input of the third operational amplifier is connected to a positive voltage source, the second power input to a source ICOM negative voltage, and output through the eleventh resistor connected to the input of the inverter, which is connected to the cathode of the zener diode, the anode of which is connected to the zero potential source and the output of the inverter output of each driver.

 The third shaper contains the first, second, third, fourth, fifth, sixth, seventh tuning, eighth, ninth, tenth, eleventh, twelfth and thirteenth resistors, first, second and third operational amplifiers, first, second and third diodes, first and second capacitors , a zener diode and an inverter, and the direct input of the first operational amplifier is connected through the first resistor to a source of zero potential, the inverse input through the second resistor is the input of the third driver, the first power input is the first operational force The device is connected to the positive voltage source, the second power input to the negative voltage source, and the output through the fourth resistor is connected to its inverse input, which is connected through the third resistor to the zero potential source, the output of the first operational amplifier through the ninth resistor is connected to the direct input of the second operational amplifier the fifth, sixth and seventh tuning resistors connected in series are connected by the fifth resistor to the positive voltage source and the seventh tuning resistor a resistor to the source of zero potential, and the connection point of the fifth and sixth resistors is connected through the eighth resistor to the inverse input of the operational amplifier, the output of which is connected through the tenth resistor to the direct input of the second operational amplifier, which is connected to the cathode of the first diode, the anode of which is connected to the source of zero potential , the output of the second operational amplifier through a series-connected first capacitor, the eleventh and twelfth resistors is connected to the inverse input of the third opera of the amplifier, the connection point of the eleventh and twelfth resistors is connected to the zero potential source through the second and third diodes and the second capacitor connected in parallel, the cathode of the second diode connected to the anode of the third diode, the direct input and the correction input of the third operational amplifier connected to the zero potential source, the first the power input of the third operational amplifier is connected to a positive voltage source, the second power input to a negative voltage source, and the output is black of the thirteenth resistor connected to the input of the inverter, which is connected to the cathode of the zener diode, the anode of which is connected to the zero potential source and the output of the inverter output of the third driver.

 The fourth driver includes a frequency divider, first and second inverters, first and second matching circuits, first, second, third and fourth signal generating channels, each of which contains first and second matching circuits, first, second, third, fourth, fifth and sixth D -triggers, inverter, inhibit trigger and capacitor, moreover, the first inputs of the first coincidence circuit of the first, second, third and fourth channels of signal formation are connected in parallel, the first input of the fourth driver, connected in parallel q of the first inverter, the first synchronization input of the frequency divider, the second input of the first matching circuit of the first signal conditioning channel, the first and second inputs of the inverter of the first signal conditioning channel and the first input of the second matching circuit of the first signal conditioning channel, the second input of the fourth driver, the output of the first inverter is connected to the second the input of the first matching circuit of the second signal conditioning channel, the first output of the frequency divider is connected to its second synchronization input, the second output is connected to the second mu input of the first matching circuit of the third signal conditioning channel and the input of the second inverter, the output of which is connected to the second input of the first matching circuit of the fourth signal conditioning channel, the inverter output in each signal conditioning channel is connected through a capacitor to the source of zero potential and the second input of the second matching circuit, output which is connected to the R-inputs of the first, second, third, fourth, fifth, sixth D-flip-flops and a ban trigger, the inverse of which is connected to the third input of the first coincidence circuit, the output of which is connected to the synchronization input of the first D-trigger, the inverse output of which is connected to the synchronization inputs of the second, third, fourth, fifth and sixth D-triggers and the D-input of the first D-trigger, the inverse output of the second D-trigger is connected to D-input of the third D-flip-flop, the direct output of which is connected to the D-input of the fourth D-flip-flop, the output of which is connected to the D-input of the fifth D-flip-flop, the output of which is connected to the D-input of the sixth D-flip-flop, whose inverse output is connected to D-input of the second D-trigger and S-input m inhibition trigger, the inverse outputs of the fifth D-flip-flops of the first and second signal conditioning channels, respectively, the first and second outputs of the fourth driver, the inverse outputs of the third D-triggers of the first and second signal conditioning channels are connected respectively to the first and second inputs of the first matching circuit of the fourth driver which the third output of the fourth driver, the inverse outputs of the third D-flip-flops of the third and fourth channels of signal formation are connected respectively to the first and second The first inputs of the second matching circuit of the fourth driver, the output of which is the fourth output of the fourth driver, the inverse outputs of the fifth D-flip-flops of the third and fourth channels of signal generation are the fifth and sixth outputs of the fourth driver, respectively.

 The fifth driver includes a D-trigger, a capacitor, a resistor, a diode and a matching element, the first input of the matching element being the first input of the fifth driver, the synchronization input of the D-trigger is the second input of the fifth driver, the direct output of the D-trigger is connected to the second input of the matching element, the output of which the first output of the fifth driver, the inverse output of the D-trigger is connected to its D-input and connected to a positive voltage source through a capacitor and parallel connected resistor and diode, and to a positive About the voltage, the cathode of the diode is connected, and the connection point of the capacitor, resistor and diode is the second output of the fifth driver.

 The control unit contains the first, second, third, fourth, fifth and sixth frequency dividers, the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth and fourteenth coincidence elements, the first, second , third, fourth, fifth, sixth and seventh triggers, operating mode trigger, synchronization trigger, inverter, first and second OR elements, first and second push-button switches, the first input of the first matching element the first input of the control unit, the second input of the first electronic coincidence is connected through the first push-button switch to a source of zero potential, and the output with the S-input of the first trigger, the direct output of which is connected to the first input of the second coincidence element, the second input of which is the second input of the control unit, the output of the second coincidence element is connected to the S-input of the second a trigger whose direct output is connected to the first input of the fifth coincidence element, the first synchronization input of the first frequency divider, the third input of the control unit, the first and second R-inputs of the first frequency divider are connected to the source of zero potential, the first output is connected to its second synchronization input, and the second output is connected to the second input of the fifth coincidence element, the first synchronization input of the second frequency divider is connected in parallel, the first inputs of the seventh and eighth coincidence elements are the fourth input of the control unit, and the first input the fourth element of coincidence, the fifth input of the control unit, the first and second R-inputs of the second and third frequency dividers are connected to a source of zero potential, the first output of the second divider the cell is connected to its second synchronization input, and the second output to the first inputs of the thirteenth and fourteenth coincidence elements and the first synchronization input of the third frequency divider, the first output of which is connected to its second synchronization input, and the second output to the first input of the third coincidence element, the output of the fifth element coincidence is connected to the first inputs of the tenth, eleventh and twelfth elements of coincidence, the first and second synchronization inputs of the fifth frequency divider and the synchronization trigger input sync onization, the inverse output of which is connected to its D-input, the second input of the eighth match element and the synchronization input of the fifth trigger, the direct output of which is connected to the first input of the ninth match element, the output of which is connected to the second input of the eleventh match element and the synchronization input of the sixth trigger, direct the output of which is connected to the second input of the twelfth coincidence element, the output of which is connected to the first input of the first OR element, the direct output of the synchronization trigger is connected to the second one of the ninth coincidence element, the second input of the seventh coincidence element and the synchronization input of the third trigger, the output of the fifth frequency divider is connected to the synchronization input of the seventh trigger, the direct output of which is connected to the second input of the thirteenth coincidence element, the first input of the second OR element and the first synchronization input of the sixth frequency divider, inverse output of the seventh trigger to its D-input and second input of the fourteenth coincidence element, the first output of the sixth frequency divider is connected to its second input m of synchronization, and the second output with the second input of the tenth coincidence element, the output of which is connected to the S-input of the operating mode trigger, the direct output of which is connected to the second input of the fourth coincidence element, and the inverse output to the third inputs of the fifth, seventh, eighth, thirteenth and fourteenth matching elements and the D and R inputs of the third trigger, the direct output of which is connected to the second input of the third matching element, the output of the fourth matching element is connected to the first input of the sixth matching element, the output to which is connected to the first synchronization input of the fourth frequency divider and the inverter input, the output of which is connected to the second input of the first OR element, the output of which is the first output of the control unit, the first output of the fourth frequency divider is connected to its second synchronization input, the second output to the second input of the second the "OR" element and the D- and R-inputs of the fourth trigger, the C-input of which through the second push-button switch is connected to the source of zero potential, and the direct output to the second input of the sixth coincidence element, the output is the seventh of the second coincidence element, the second output of the control unit, the direct output of the synchronization trigger, the third output of the control unit, the outputs of the eighth, eleventh and thirteenth coincidence elements, respectively, the fourth, fifth and sixth outputs of the control unit, the direct output of the seventh trigger, the seventh output of the control unit, the outputs of the fourteenth coincidence element element "OR" and the third element of coincidence, respectively, the eighth, ninth and tenth outputs of the control unit.

 The first and second switches contain each first, second, third, fourth, fifth, sixth, seventh and eighth two-digit multiplexers, the first information inputs of each bit of all multiplexers - the first input of each switch, the second information inputs of each bit of all multiplexers the second input of each switch, parallel connected first address inputs of all multiplexers the third input of each switch, parallel connected second address inputs of all multiplexers are connected to the source zero potential, and the first and second outputs of all multiplexers output of each switch.

 The first and second elements of comparison contain each first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth single-digit adders, the first, second, third and fourth elements of coincidence , the first, second, third, fourth and fifth inverters, the first and second elements "OR, a trigger and a push button switch, the first input of the first adder connected to a source of zero potential, the first inputs of the second, third, fourth, fifth, the sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth adders are connected to the transfer outputs of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, respectively , thirteenth, fourteenth and fifteenth adders, the second inputs of all adders the first input of each element of comparison, the transfer inputs of all adders the second input of each element of comparison, the outputs of the sum of the first, second the third, fourth, fourth, fifth, sixth, seventh and eighth adders are connected respectively to the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of the first coincidence element, the outputs of the sum of the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth , fifteenth and sixteenth adders, respectively, to the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of the second match element, the outputs of the first and second match elements are connected to the inputs and, respectively, the first and second inverters, the outputs of which are connected respectively to the first and second inputs of the third coincidence element, the output of which is connected to the first input of the fourth element of coincidence and through the third inverter with the first input of the first element "OR", the transfer output of the sixteenth adder is connected to the input of the fourth inverter and the second input of the fourth coincidence element, the output of which through the fifth inverter is connected to the second input of the first OR element, the output of the fourth inverter is connected to the third input an ode of the first “OR” element, the output of which is connected to the S-input of the trigger, the R-input of which is connected via a push-button switch to a source of zero potential, the inverse output of the trigger is connected to the first input of the second “OR” element, while for the first comparison element the second input the second OR element is connected to the output of the fifth inverter, for the second comparison element, the second input of the second OR element is to the output of the fourth inverter, and the output of the second OR element is the output of each comparison element.

 Comparative analysis with the prototype shows that the inventive device differs from the known one by the presence of new elements: a synchronization sensor, a third, fourth and fifth formers, a frequency divider, a control unit, a second, third, fourth, fifth, sixth, seventh and eighth counters, the first and second switches, the first and second random access memory, the second indicator, the connections between them and the remaining elements of the device, as well as the design of the pulse generator, the first, the second, third, fourth and fifth formers, the control unit, the first and second switches, the first and second comparison elements.

 Thus, the claimed device meets the criterion of "novelty."

 Introduction to the proposed device, the synchronization sensor, the third, fourth and fifth formers, frequency divider, control unit, the second, third, fourth, fifth, sixth, seventh and eighth counters, the first and second switches, the first and second random access memory, the second indicator and connections between them and with the other elements of the device, as well as the corresponding implementation of the pulse generator, the first, second, third, fourth and fifth formers, control unit, the first and second mutators, first and second comparison elements can measure time intervals of the crankshaft rotation at known discrete angle within the engine cycle synchronization with the start of measurement with a certain stroke of the engine cylinder and the results are written in the random access memory. As a result of this, it becomes possible to determine the coefficient of rotation unevenness both within the engine cycle and the periods of change in the torque of the same cycle and, due to this, evaluate the technical condition of individual engine cylinders. In this case, the average value of the rotational speed is defined as the duration of rotation of the crankshaft by an angle corresponding to the cycle of the engine or the period of change of torque, which increases the accuracy of determining the rotational speed, and hence the coefficient of uneven rotation. The presence of two counters for generating equivalents of the crankshaft rotation time by a certain angle eliminates the distortion of the measured information due to the coincidence of the beginning of filling the counters with pulses of the reference frequency generator with the leading edges of the main pulses of the speed sensor, which also increases the accuracy of determining the coefficient of rotation unevenness. The control of uneven rotation is carried out with simultaneous control of the engine speed mode.

 In FIG. 1 shows a block diagram of a device; in FIG. 2 is a timing diagram of the voltages at the outputs of its main nodes; in FIG. 3 -principal circuit of the pulse generator; figure 4 is a schematic diagram of the first and second formers; in FIG. 5 schematic diagram of the third shaper; in FIG. 6 is a schematic diagram of a fourth former; in FIG. 7 is a schematic diagram of a fifth shaper; in FIG. 8 is a schematic diagram of a control unit; in FIG. 9 is a schematic diagram of the first and second switches; in FIG. 10 is a schematic diagram of the first and second comparison elements (the connection between the second OR element and the fifth inverter as a solid line for the first comparison element, and the connection between the second OR elements and the fourth inverter as a dashed line for the second comparison element).

 A device for monitoring uneven rotation of the shaft of an internal combustion engine comprises a rotation speed sensor 1 (Fig. 1), a synchronization sensor 2, a pulse generator 3, a first 4, a second 5, a third 6, a fourth 7 and a fifth 8 formers, a frequency divider 9, block 10 control, first 11, second 12, third 13, fourth 14, fifth 15, sixth 16, seventh 17 and eighth 18 counters, first 19 and second 20 switches, first 21 and second 22 random access memory devices, first 23 and second 24 registers, first 25 and second 26 comparison items, calculator 27, first 28 second 29 indicators.

The output of the synchronization sensor 2 is connected to the input of the third driver 6, the output of which is connected to the first input of the control unit 10. The first output of the speed sensor 1 is connected to the input of the first driver 4, and the second output to the input of the second driver 5, the output of which is connected to the second input of the control unit 10. The output of the first driver 4 is connected to the third input of the control unit 10 and the first input of the fifth driver 8. The output of the pulse generator 3 is connected to the fourth input of the control unit 10 and the input of the frequency divider 9, the first output of which is connected to the second input of the fifth driver 8, and the second output to the fifth input of the control unit 10 and the first input of the fourth driver 7. The first output of the control unit 10 is connected to the counting input of the fifth counter 15, the second output of the control unit 10 is connected to the counting input of the first counter 11, information the output of which is connected to the first input of the first switch 19. The third output of the control unit 10 is connected to the second input of the first switch 19, the fourth output of the control unit 10 is connected to the counting input of the second counter 12, the information output of which is connected to the third input of the first switch 19, fifth the output of the control unit 10 is connected to the second input of the fourth shaper 7, the first and second outputs of which are connected to the zeroing inputs of the first 11 and second 12 counters, respectively, the third and fourth outputs
to the first inputs, respectively, of the first 21 and second 22 random access memory, and the fifth and sixth output to the inputs of zeroing, respectively, of the third 13 and fourth 14 counters. The sixth output of the control unit 10 is connected to the counting input of the third counter 13, the information output of which is connected to the first input of the second switch 20. The seventh output of the control unit 10 is connected to the second input of the second switch 20, the eighth output of the control unit 10 is connected to the counting input of the fourth counter 14, the information output of which is connected to the third input of the second switch 20. The ninth and tenth outputs of the control unit 10 are connected to the counting inputs of the sixth 16 and seventh 17 counters, respectively. The information outputs of the first 19 and second 20 switches are connected to the second inputs of the first 21 and second 22 random access memory, respectively, the third inputs of which are connected to the information outputs of the fifth 15 and sixth 16 counters, respectively. The first and second outputs of the fifth shaper 8 are connected respectively to the counting input and the zeroing input of the counter 18, the output of which is connected to the input of the second indicator 29. The direct information output of the first register 23 is connected to the first input of the calculator 27 and the first input of the first comparison element 25, and the direct information the output of the second register 24 to the second input of the calculator 27 and the first input of the second comparison element 26. The information output of the first random access memory 21 is connected to the information inputs of the first 23 and second 24 registers and the second inputs of the first 25 and second 26 comparison elements, the outputs of which are connected to the synchronizing inputs of the first 23 and second 24 registers, and the information outputs of the seventh counter 17 and second random access memory 22, respectively, to the third and fourth inputs of the calculator 27, the output of which is connected to the input of the first indicator 28.

 The shaft speed sensor 1 is designed to receive pulsed signals at the output, the frequency of which is proportional to the shaft speed. The magneto-induction type sensor has two outputs, one of which emits several pulses within one revolution of the shaft at equal angular intervals (main pulses), and the second one pulse per revolution, corresponding to the top dead center of a certain engine cylinder (reference pulse).

 The synchronization sensor 2 is used to receive pulsed signals at the output corresponding to the moments of the start of fuel injection (ignition times) in a specific engine cylinder. It is made in the form of a piezoelectric type pressure sensor.

 The 3 pulse generator is designed to produce stable frequency pulses. It contains the first D1.1 (Fig. 3), the second D1.2 and the third D1.3 gates "2I-NOT", resistors R1 and R2, capacitor C1 and quartz resonator B1, the inputs and outputs of the first D1.1 and the second D1.2 logic elements are interconnected via resistors R1 and R2, the output of the first logical element D1.1 is connected through the capacitor C1 to the inputs of the second logical element D1.2, the output of which is connected to the inputs of the third logical element D1.3 and through a quartz resonator B1 with the inputs of the first logical element D1.1, and the output of the third logical element D1.3 output generator 3 (Fig. 1) pulses. The 3 pulse generator is based on the K155LAZ chip.

 The first 4 and second 5 shapers are used to obtain rectangular pulses with steep fronts upon receipt of the main and reference signals with the output of the speed sensors 1 respectively. They contain every first C1 (Fig. 4), second C2 and third C3 capacitors, first R1, second R2, third R3, fourth R5, sixth R6, seventh R7, eighth R8, ninth R9, tenth R10 and eleventh R11 resistors, the first A1, second A2 and third A3 operational amplifiers, the first V1, second V2 and third V3 diodes, a Zener diode V4 and an inverter D1, and the direct output of the first operational amplifier A1 is connected through a series connection of the first resistor R1 and the first capacitor C1 to a source of zero potential, and the point of their connection is the input of each shaper. The inverse input of the first operational amplifier A1 is connected through a second resistor R2 to a source of zero potential, the first input of the operational amplifier A1 is connected to a positive voltage source, the second input to a negative voltage source, and the output through a third resistor R3 is connected to its inverse input through the sixth resistor R6 with direct input of the second operational amplifier A2. The fourth R4 and fifth R5 resistors connected in series are connected respectively to the positive voltage source and the zero potential source, and their connection point is connected through the seventh resistor R7 to the inverse input of the second operational amplifier A2. The first power input of the second operational amplifier A2 is connected to a positive voltage source, the second power input to a source of zero potential, and the output of the second operational amplifier A2 is connected through the eighth resistor R8 with its direct input, which is connected to the cathode of the first diode V1, the anode of which is connected to the source zero potential. The output of the second operational amplifier A2 through series-connected second capacitor C2, the ninth R9 and tenth R10 resistors is connected to the inverse input of the third operational amplifier A3. The connection point of the ninth R9 and tenth R10 resistors through parallel connected second V2 and third V3 diodes and a third capacitor C3 is connected to a source of zero potential, and the cathode of the second diode V2 is connected to the anode of the third diode V3. The direct input and correction input of the third operational amplifier A3 is connected to a source of zero potential, the first power input of the third operational amplifier A3 is connected to a positive voltage source, the second power input to a negative voltage source, and the output through the eleventh resistor R11 is connected to the input of the inverter D1, which is connected to the cathode of the Zener diode V4, the anode of which is connected to a source of zero potential, and the output of the inverter D1 is the output of each shaper. Both shapers are made according to the same schemes based on K140UD1B microcircuits.

 The third driver 6 (Fig. 1) is designed to amplify, limit the amplitude and the formation of the duration of the pulses arriving at its input from the sensor 2 synchronization (fuel injection or ignition). It contains the first R1 (Fig. 5), second R2, third R3, fourth R4, fifth R5, sixth R6, seventh R7 trimming, eighth R8, ninth R9, tenth R10, eleventh R11, twelfth R12 and thirteenth R13 resistors, first A1 , the second A2 and third A3 operational amplifiers, the first V1, second V2 and third V3 diodes, the first C1 and second C2 capacitors, the Zener diode V4 and the inverter D1, and the direct input of the first operational amplifier A1 is connected through the first resistor R1 to a source of zero potential, inverse input through the second resistor R2 input of the third shaper. The first power input of the first operational amplifier A1 is connected to a positive voltage source, the second power input to a negative voltage source, and the output through the fourth resistor R4 is connected to its inverse input, which is connected through a third resistor R3 to a source of zero potential. The output of the first operational amplifier A1 through the ninth resistor R9 is connected to the direct input of the second operational amplifier A2. The fifth R5, sixth R6, and seventh R7 trimming resistors are connected in series with the fifth resistor R5 connected to a positive voltage source and the seventh R7 trimming resistor with a zero potential source, and the connection point of the fifth R5 and sixth R6 resistors is connected through the eighth resistor R8 to the inverse input of the second operational amplifier A2, the output of which is connected through the tenth resistor R10 to the direct input of the second operational amplifier A2, which is connected to the cathode of the first diode V1, the anode of which is connected to the source zero potential. The output of the second operational amplifier A 2 through series-connected first capacitor C1, the eleventh R11 and the twelfth R12 resistors is connected to the inverse input of the third operational amplifier A3. The connection point of the eleventh R11 and twelfth R12 resistors through parallel connected second V2 and third V3 diodes and a second capacitor C2 is connected to a source of zero potential, and the cathode of the second diode V2 is connected to the anode of the third diode V3. The direct input and the correction input of the third operational amplifier A3 are connected to a source of zero potential. The first power input of the third operational amplifier A3 is connected to a positive voltage source, the second power input to a negative voltage source, and the output through the thirteenth resistor R13 is connected to the input of the inverter D1, which is connected to the cathode of the Zener diode V4, the anode of which is connected to a source of zero potential, and the output inverter D1 output of the third shaper. It is based on K14OUD1B microcircuits.

 The fourth shaper 7 (Fig. 1) serves to generate reset pulses of the counters 11, 12 and 13, 14 after overwriting the information recorded in them during the measurement process and the resolution pulses for recording this information in random access memory devices 21 and 22, respectively, at the end of the measurement process by any of two counters 11 or 12 and 13 or 14. It contains a frequency divider D1 (Fig. 6), the first D2 and second D3 inverters, the first D4 and second D5 matching circuits, the first F7.1, the second F7.2, the third F7. 3 and fourth F7.4 signal conditioning channels, each and of which contains the first D6 and second D7 matching circuits, the first D8, second D9, third D10, fourth D11, fifth D12 and sixth D13 D-flip-flops, inverter D14, inhibition trigger D15 and capacitor C1, with the first inputs of the first matching circuits being connected in parallel the first F7.1, the second F7.2, the third F7.3 and the fourth F7.4 signal conditioning channels the first input of the fourth driver. Parallel connected to the input of the first inverter D2, the first synchronization input of the frequency divider D1, the second input of the first matching circuit D6 of the first signal generating channel F7.1, the first and second inputs of inverter D14 of the first channel F7.1 and the first input of the second matching circuit D7 of the first channel F7. 1 signal generation second input of the fourth shaper. The output of the first inverter D2 is connected to the second input of the first matching circuit of the second signal generating channel F7.2. The first output of the frequency divider D1 is connected to its second synchronization input, the second output is connected to the second input of the first matching circuit of the third signal generating channel F3 and the input of the second inverter D3, the output of which is connected to the second input of the first matching circuit of the fourth signal generating channel F7.4. The output of the inverter D14 in each signal conditioning channel is connected through a capacitor C1 to a source of zero potential and the second input of the second coincidence circuit D7, the output of which is connected to the R-inputs of the first D8, second D9, third D10, fourth D11, fifth D12, sixth D13 D- Triggers and trigger D15 ban. The inverse output of the inhibit trigger D15 is connected to the third input of the first coincidence circuit D6, the output of which is connected to the synchronization input of the first D8 D-trigger, the inverse output of which is connected to the synchronization inputs of the second D9, third D10, fourth D11, fifth D12 and sixth D13 D-flip-flops and the D input of the first D8 D trigger. The inverse output of the second D9 D-flip-flop is connected to the D-input of the third D10 D-flip-flop, the direct output of which is connected to the D-input of the fourth D11 D-flip-flop, the output of which is connected to the D-input of the fifth D12 D-flip-flop, the output of which is connected to D - the input of the sixth D13 D-flip-flop, whose inverse output is connected to the D-input of the second D9 D-flip-flop and the S-input of the D15 flip-flop. The inverse outputs of the fifth D-flip-flops of the first F7.1 and second F7.2 channels of signal generation are the first and second outputs of the fourth driver, respectively. The inverse outputs of the third D-flip-flops of the first F7.1 and second F7.2 signal conditioning channels are connected respectively to the first and second inputs of the first coincidence circuit D4 of the fourth driver, the output of which is the third output of the fourth driver. The inverse outputs of the third D-flip-flops of the third F7.3 and fourth F7.4 signal conditioning channels are connected respectively to the first and second inputs of the second matching circuit D5 of the fourth driver, the output of which is the fourth output of the fourth driver. The inverse outputs of the fifth D-flip-flops of the third F7.3 and fourth F7.4 signal conditioning channels are the fifth and sixth outputs of the fourth driver, respectively. The fourth shaper is based on K155LAZ, K155TM2, K155LA4 and K155IE5 microcircuits.

 The fifth shaper 8 (Fig. 1) is designed to form packs of counting pulses of the speed sensor 1 during the time determined by the frequency divider 9, as well as reset pulses of the counter 17. It contains a D-trigger D1 (Fig. 7), a capacitor C1, a resistor R1 , the diode V1 and the coincidence element D2, wherein the first input of the coincidence element D2 is the first input of the fifth driver, the synchronization input of the D-flip-flop D1 is the second input of the fifth driver. The direct output of the D-flip-flop D1 is connected to the second input of the coincidence element D2, the output of which is the first output of the fifth driver. The inverse output of the D-flip-flop D1 is connected to its D-input and through the capacitor C1 and the resistor R1 and the diode V1 connected in parallel are connected to the positive voltage source, and the cathode of the diode V1 is connected to the positive voltage source, and the connection point of the capacitor C1, the resistor R1 and the diode V1 is the second output of the fifth shaper. The fifth driver is based on K155TM2 K155LAZ microcircuits.

 The frequency divider 9 (Fig. 1) is used to form time intervals for measuring the rotational speed, as well as to generate clock pulses that determine the duration of the write and reset pulses of the shaper 7 and the duration of the information processing cycle recorded in random access memory 21 and 22. It is made in the form binary decimal counter with a variable division coefficient based on K155IE2 and K155IE5 microcircuits and has two outputs.

 The control unit 10 is designed to synchronize the start of measurement by the signals of the shapers 5 and 6, the distribution of control pulses in the measurement mode and recording the source information in random access memory 21 and 22 and control the process of its processing. It contains the first D1 (FIG. 8), second D2, third D3, fourth D4, fifth D5 and sixth D6 frequency dividers, first D7, second D8. third D9, fourth D10, fifth D11, sixth D12, seventh D13, eighth D14, ninth D15, tenth D16, eleventh D17, twelfth D18, thirteenth D19 and fourteenth D20 matching elements, first D21, second D22, third D23, fourth D24, fifth D25, sixth D26 and seventh D27 flip-flops, trigger d28 of an operating mode, synchronization flip-flop D29, inverter D30, first D31 and second D32 “OR” elements, first S1 and second S2 push-button switches, with the first input of the first element D7 matching the first input of the block management. The second input of the first coincidence element D7 is connected through the first push-button switch S1 to a source of zero potential, and the output is from the S-input of the first trigger D21, the direct output of which is connected to the first input of the second coincidence element D8, the second input of which is the second input of the control unit. The output of the second coincidence element D8 is connected to the S-input of the second trigger d22, the direct output of which is connected to the first input of the fifth coincidence element D11, the first synchronization input of the first frequency divider D1 is the third input of the control unit, the first and second R-inputs of the first frequency divider D1 are connected to to the source of zero potential, the first output is connected to its second synchronization input, and the second output is connected to the second input of the fifth coincidence element D11. In parallel, the first synchronization input of the second frequency divider D2, the first inputs of the seventh D13 and eighth D14 matching elements are the fourth input of the control unit, and the first input of the fourth matching element D10 is the fifth input of the control unit, the first and second R inputs of the second D2 and third D3 frequency dividers connected to a source of zero potential. The first output of the second frequency divider D2 is connected to its second synchronization input, and the second output to the first inputs of the thirteenth D19 and fourteenth D20 matching elements and the first synchronization input of the third frequency divider D3, the first output of which is connected to its second synchronization input, and the second output to the first the input of the third element D3 matches. The output of the fifth coincidence element D11 is connected to the first inputs of the tenth D16, eleventh D17, and twelfth D18 coincidence elements, the first and second synchronization inputs of the fifth frequency divider D5, and the synchronization input of the synchronization trigger D29, whose inverse output is connected to its D input, the second input of the eighth element D14 matches and synchronization input of the fifth trigger D25. The direct output of the fifth trigger D25 is connected to the first input of the ninth match element D15, the output of which is connected to the second input of the eleventh match element D17 and the synchronization input of the sixth trigger D26, the direct output of which is connected to the second input of the twelfth match element D18, the output of which is connected to the first input of the first element D31 "OR". The direct output of the trigger synchronization D29 is connected to the second input of the ninth match element D15, the second input of the seventh match element D13 and the synchronization input of the third trigger d23. The output of the fifth frequency divider D5 is connected to the synchronization input of the seventh trigger D27, the direct output of which is connected to the second input of the thirteenth coincidence element D19, the first input of the second OR element D32 and the first synchronization input of the sixth frequency divider D6, the inverse output of the seventh trigger d27 to its D the input and second input of the fourteenth element D20 matches. The first output of the sixth frequency divider D6 is connected to its second synchronization input, and the second output to the second input of the tenth coincidence element D16, the output of which is connected to the S-input of the trigger D28 of the operating mode. The direct output of the operating mode trigger D28 is connected to the second input of the fourth coincidence element D10, and the inverse output is to the third inputs of the fifth D11, seventh D13, eighth D14, thirteenth D19 and fourteenth D20 matching elements and the D and R inputs of the third trigger D23, direct output which is connected to the second input of the third element D9 matches. The output of the fourth coincidence element D10 is connected to the first input of the sixth coincidence D12, the output of which is connected to the first synchronization input of the fourth frequency divider D4 and the inverter D30, the output of which is connected to the second input of the first OR element D31, the output of which is the first output of the control unit. The first output of the fourth frequency divider D4 is connected to its second synchronization input, the second output to the second input of the second OR element D32 and the D and R inputs of the fourth trigger D24, the C-input of which is connected to the zero potential source through the second push-button switch S2, and direct output to the second input of the sixth coincidence element D12. The output of the seventh element D13 matches the second output of the control unit. Direct output trigger D29 synchronization third output of the control unit. The outputs of the eighth D14, eleventh D17 and thirteenth D19 coincidence elements are the fourth, fifth and sixth outputs of the control unit, respectively. Direct output of the seventh trigger D27 seventh output of the control unit. The outputs of the fourteenth coincidence element D20, the second OR element D32, and the third coincidence element D9 are the eighth, ninth, and tenth outputs of the control unit, respectively. The control unit is based on K155IE2, K155IE5, K155LA3, K155LA4, K155TM2, K155LL1 and K155IR1 microcircuits.

 The first 11 (Fig. 1) and second 12 counters are used to measure the time intervals between adjacent pulses of the rotational speed sensor 1 by alternately filling them with stable frequency pulses from the output of the 3 pulse generator.

 The third 13 and fourth 14 counters are designed to measure time intervals corresponding to the rotation of the crankshaft by an angle equal to the period of change in engine torque by alternately filling these intervals with pulses whose frequency is n times less than the frequency of the 3 pulse generator, where N is the number of measured sensor intervals 1 rotational speed within the period of change of torque.

 All counters are based on K155IE2 microcircuits in the form of sixteen-digit binary decimal counters with information and installation inputs.

 Fifth 15 and sixth 16 counters are designed to generate addresses recorded in random access memory, respectively, 21 and 22 equivalents of the crankshaft rotation time at a certain angle in binary code. They are based on K155IE2 microcircuits in the form of eight-bit binary counters with information and installation inputs.

 The seventh counter 17 is designed to measure the duration of the kinematic cycle of the engine by filling it with pulses whose frequency is kN times less than the frequency of the 3 pulse generator, where k is the number of engine cylinders. The counter is based on K155IE2 chips.

 The eighth counter 18 is used to periodically measure the number of pulses of the speed sensor 1 over a time period formed by the frequency divider 9. It is based on K155IE2 microcircuits in the form of a sixteen-bit binary-decimal counter with information and installation inputs.

 The first 19 and second 20 switches are used to alternately connect the information outputs of the counters of the first 11, second 12 and third 13, fourth 14 to the information inputs of random access memory, respectively, of the first 21 and second 22. They contain each first D1 (Fig. 9), second D2 , the third D3, the fourth D4, the fifth D5, the sixth D6, the seventh D7 and the eighth D8 are two-digit multiplexers, the first information inputs of each bit of all multiplexers the first input of each switch, the second information inputs of each bit of all mu tipleksorov second input of each switch connected in parallel to first address inputs of multiplexers each entree third switch connected parallel to the second address inputs of multiplexers are connected to the zero potential source and the first and second outputs of all the output of each multiplexer switch. They are based on K155KP2 microcircuits.

 The first 21 (Fig. 1) and second 22 random access memory devices are designed for recording, storage and multiple issuance for further processing of equivalents of the repetition periods of the pulses of the speed sensor 1 in binary decimal code. They are implemented as a matrix of semiconductor memory elements based on K155RU5 microcircuits and have a memory capacity of 256 sixteen-bit words.

 The first 23 and second 24 registers are used to record and store the maximum and minimum values of time intervals from a sequence of numbers recorded in the first random access memory 21. The maximum value of the time interval corresponds to the minimum speed of the crankshaft, and the minimum value to the maximum speed. Each of the registers is made on sixteen parallel-connected D-flip-flops based on K155TM5 microcircuits.

 The first 25 and second 26 comparison elements are used to compare the values of time intervals coming from the outputs of the first random access memory 21 and the registers of the first 23 and second 24, respectively, presented in binary decimal code. They are made according to similar schemes (Fig. 10) and contain each first D1, second D2, third D3, fourth D4, fifth D5, sixth D6, seventh D7, eighth D8, ninth D9, tenth D10, eleventh D11, twelfth D12, thirteenth D13, fourteenth D14, fifteenth D15 and sixteenth D16 single-digit combiners, first D17, second D18, third D19 and fourth D20 matching elements, first D21, second D22, third D23, fourth D24 and fifth D25 inverters, first D26 and second D27 elements OR, trigger D28 and push-button switch S1, and the first input of the first adder D1 is connected to the source well The first inputs of the second D2, third D3, fourth D4, fifth D5, sixth D6, seventh D7, eighth D8, ninth D9, tenth D10, eleventh D11, twelfth D12, thirteenth D13, fourteenth D14, fifteenth D15 and sixteenth D16 adders connected to the transfer outputs respectively of the first D1, second D2, third D3, fourth D4, fifth D5, sixth D6, seventh D7, eighth D8, ninth D9, tenth D10, eleventh D11, twelfth D12, thirteenth D13, fourteenth D14 and fifteenth D15 adders . The second inputs of all adders are the first input of each element of comparison. The transfer inputs of all adders is the second input of each comparison element. The outputs of the sum of the first D1, second D2, third D3, fourth D4, fifth D5, sixth D6, seventh D7 and eighth D8 adders are connected respectively to the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of the first matching element D17. The outputs of the sum of the ninth D9, tenth D10, eleventh D11, twelfth D12, thirteenth D13, fourteenth D14, fifteenth D15 and sixteenth D16 adders respectively to the first, second, third, fourth, fourth, fifth, sixth, seventh and eighth inputs of the second match element D18. The outputs of the first D17 and second D18 matching elements are connected to the inputs of the first D21 and second D22 inverters respectively, the outputs of which are connected respectively to the first and second inputs of the third matching element D19, the output of which is connected to the first input of the fourth matching element D20 and through the third inverter D23 to the first the input of the first element D26 "OR". The transfer output of the sixteenth adder D16 is connected to the input of the fourth inverter D24 and the second input of the fourth match element D230, the output of which through the fifth inverter D25 is connected to the second input of the first OR element D26. The output of the fourth inverter D24 is connected to the third input of the first OR26 element D26, the output of which is connected to the S-input of trigger D28, whose R-input is connected via push-button switch S1 to a source of zero potential. The inverted output of trigger D28 is connected to the first input of the second OR element D27, while for the first comparison element 25 (Fig. 1), the second input of the second OR element D27 (Fig. 10) is connected to the output of the fifth inverter D25, for the second element 26 (FIG. 1), the second input of the second OR element D27 (FIG. 10) to the output of the fourth inverter D24, and the output of the second OR element D27 is the output of each comparison element. Both comparison elements are based on K155IM1, K155LA2, K155LA3, K155LA4 and K155TM2 microcircuits.

 The calculator 27 (Fig. 1) is used to calculate the maximum, minimum and average values of the crankshaft speed within the engine cycle and the period of change of torque, followed by calculation of the coefficient of uneven rotation for the engine cycle and successive periods of change of torque. The arithmetic-logic device of the B3-18 type microcalculator is used as a calculator. It operates on a rigid program in conjunction with the input switch. The calculator also uses K155KP1 microcircuits.

 The first indicator 28 is intended to indicate the calculation results and is made in the form of seven-segment indicators of the type IV-4.

The second indicator 29 is used for decryption and periodic display on digital indicators of the average rotational speed of the crankshaft, expressed in min ^-1 . It consists of a binary decimal sixteen-digit code decoder in series with a four-digit decimal code and four indicator lamps of the IV-4 type.

 The device operates as follows.

 Previously, a speed sensor 1 and a synchronization sensor 2 are installed on the engine and connected to the device. After starting the engine, applying the voltage supplying the device and the “Reset” signal, all elements of the device are set to their initial state. In this case, the signals from the output of the speed sensor 1 and the synchronization sensor 2, having passed the first 4, second 5 and third 6 shapers, are fed to the inputs of the control unit 10. The pulse generator 3 continuously generates pulses of a stable frequency, which simultaneously arrive at the inputs of the control unit 10 and the frequency divider 9. The main pulses from the output of the first driver 4, the frequency of which is proportional to the rotational speed of the engine crankshaft, is fed to the first input of the fifth driver 8. The second input of the fifth driver 8 receives pulses from the first output of the frequency divider 9, the period of which is determined by the measurement speed. From the first output of the fifth shaper 8, the counting input of the eighth counter 18 receives the sequence of the main pulses of the rotation speed sensor 1, determined by the pulse repetition period from the first output of the frequency divider 9. The number of pulses contained in each of the sequences is equal to the number of revolutions of the engine crankshaft per minute. The number of these pulses is counted by the eighth counter 18 and digitally indicated on the second indicator 29. With the appearance of the next pulse frequency divider 9 at the first output, the fifth driver 8 generates a reset signal at its second output, which is fed to the input of zeroing the eighth counter 18. Last zeroed and again begins to count the pulses arriving at its counting input. Thus, a periodic measurement and indication of the engine speed is performed.

 When the Start signal is applied, the next pulses with the output of the third driver 6 (Fig. 2a) of the synchronization sensor 2 and the second driver 5 (Fig. 2b) of the rotation speed sensor 1 open the input logic circuit of the control unit 10 and the main pulses start from the output of the first driver 4 arrive at the counting input of the synchronization trigger of the control unit 10. The first main pulse from the output of the first driver 4 (Fig. 2B) throws the synchronization trigger of the control unit 10 to a single state, as a result of which the "And" circuit of the control unit 10 opens. The pulses from the output of the generator 3 pulses are fed to the counting input of the first counter 11 (Fig. 2e). At the same time, pulses from the second output of the frequency divider 9 through the control unit 10 are supplied to the counting input of the third counter 13 (Fig. 2i), and from the output of the frequency divider of the control unit 10 to the counting input of the seventh counter 17 (Fig. 2n).

The second main pulse (Fig. 2c) again changes the state of the synchronization trigger of the control unit 10, which directly closes the counting input of the first counter 11 (Fig. 2e), and opens the counting input of the second counter 12 with an inverse output (Fig. 2c, f). In this case, the first counter 11 captures the time between two adjacent main pulses of the speed sensor 1. The output of the first counter 11 through the first switch 19 is connected to the information (second) input of the first random access memory 21. The fourth shaper 7 generates with a delay t ₁ (Fig. 2l) a time pulse that is transmitted to the first input of the first random access memory 21 and the contents of the first counter 11 corresponds to the first random access memory 21 to zero address counter 15. after the fifth time t ₂ (FIG. 2k) after rewriting fourth information generator 7 outputs to its first in During the reset pulse input to reset the first counter 11 and resets it.

 At the time of the action of the write pulse at the first input of the first random access memory 21, a code of the number written to the zero address of the fifth counter 15 appears at its output. This code simultaneously arrives at the information inputs of the first 23 and second 24 registers and the second inputs of the first 25 and second 26 elements comparisons. RS-flip-flops of the first 25 and second 26 comparison elements are thrown and signals are generated at their outputs, according to which the specified code is written in the first 23 and second 24 registers as the number B. At the same time, RS-flip-flops translate the output OR circuits of the first 25 and second 26 elements comparisons in working condition.

 The third main pulse (Fig. 2B), having passed the input logic circuit of the control unit 10, is fed to the counting input of the fifth counter 15, as a result of which the first address code is generated at its output. At the same time, the same pulse again changes the state of the synchronization trigger of the control unit 10, which with its direct output opens the counting input of the first counter 11 (Fig. 2e), and closes the counting input of the second counter 12 with an inverse output (fixing in the last time between the following two adjacent main pulses of the speed sensor 1. According to the recording pulse from the third output of the fourth shaper 7 (Fig. 2L), the contents of the second counter 12 are copied to the first random access memory 21 at the first address of the fifth counter 15, after which the second counter 12 is reset from the second output of the fourth shaper 7 (Fig. 2k) zeroed out. At the output of the first random access memory 21, the code of number A appears and the first 25 and second 26 comparison elements begin comparing the code of number A with the code of number B recorded in the first 23 and second 24 registers. If A> B, then the number A is written in the first register 23 as the new number B. In the second register 24, the number does not change, since the condition A <B is not satisfied. If condition A <B is fulfilled, the code of number A is written in the second register 24, and the contents of the first register 23 remains unchanged, because condition A> B is not fulfilled.

 With the arrival of subsequent main pulses from the output of the first shaper 4, the measurement of time intervals, their recording in the first random access memory 21 and comparison of the codes of numbers at its output with the codes of numbers recorded in the first 23 and second 24 registers, occurs similarly.

When the crankshaft is rotated by an angle corresponding to the period of the change in torque, the pulse divider of the speed sensor 1 generates a signal that, through the "AND" circuit of the control unit 10, closes the counting input of the third counter 13 (Fig. 2g) and opens the counting input of the fourth counter 14 (Fig. 2h). In this case, the fourth counter 14 begins to summarize the pulses arriving at its counting input from the second output of the frequency divider 9, and the third counter 13 captures the equivalent of the rotation time of the engine crankshaft, corresponding to the period of change in torque, the output of the third counter 13 through the second switch 20 is connected to the information ( the second) input of the second random access memory 22, the fourth driver 7 at its fourth output generates with the same delay t ₁ a write pulse (Fig. 2m), which arrives at and the first input of the second random access memory 22 and the contents of the third counter 13 are copied to the second random access memory 22 at the zero address of the sixth counter 16. After a time t ₂ (Fig. 2n) after the information has been rewritten, the fourth driver 7 emits a reset pulse at its fifth output, which resets the third counter 13. With the arrival of the next pulse from the output of the frequency divider of the main pulses of the control unit 10, the counting input of the fourth counter 14 is closed (Fig. 2h) and the information recorded in it is copied by the recording pulse from the fourth output of the fourth shaper 7 (Fig. 2m) to the second random access memory 22 at the first address of the sixth counter 16. After that, the reset pulse from the sixth output of the fourth shaper 7 (Fig. 2o) zeroes the fourth counter 14 and the described process is repeated until the completion of the engine cycle. At the same time, at the output of the frequency divider of the main pulses of the control unit 10, a signal is released that changes the state of the trigger of the operating mode of the control unit 10, which closes the input logic circuit and the counting inputs of the first 11, second 12, third 13, fourth 14, and seventh 17 counters. In the first random access memory 21, the equivalents of the rotation time of the engine crankshaft by the angle between the main adjacent pulses of the speed sensor 1 are recorded, in the second random access memory 22 the equivalents of the rotation time of the crankshaft by the angle corresponding to the period of change in torque. In the seventh counter 17, the equivalent of the crankshaft rotation time by an angle corresponding to the engine operation cycle (two turns) is fixed. In the first register 23, the maximum value of the temporary equivalent from the array of numbers recorded in the first random access memory 21 is fixed, which corresponds to the minimum speed, and in the second register 24 is the minimum value of the temporary equivalent from the same array of numbers, which corresponds to the maximum speed.

где ω_{ц max},ω_{ц min} и ω_{ц cp} соответственно максимальное, минимальное и среднее значения частоты вращения в пределах цикла работы двигателя;
Φ₁ угол поворота коленчатого вала, определяемый дискретностью датчика 1 частоты вращения;
ν₁ частота импульсов генератора 3;
f_цmin и f_цmax соответственно минимальное и максимальное значение эквивалентов времени поворота коленчатого вала из массива чисел, записанных в первом оперативном запоминающем устройстве 21 в пределах цикла работы двигателя;
Φ₂ угол поворота коленчатого вала, соответствующий циклу работы двигателя, Φ₂=4π;;
ν₂ частота импульсов генератора 3, уменьшенная в kN раз;
f_пср эквивалент времени поворота коленчатого вала, соответствующий длительности цикла работы двигателя;
δ_ц коэффициент неравномерности вращения в пределах цикла работы двигателя.The codes of the numbers recorded in the first 23 and second 24 registers, the seventh counter 17 and the second random access memory 22 are supplied to the inputs of the switch 27 of the calculator, which sequentially calculates the actual values of the maximum, minimum, average speed and uneven rotation coefficient within the engine cycle according to the formulas

where ω _{c max,} ω _p and ω _{y min cp} respectively maximum, minimum and average values of the rotational speed within the engine cycle;
Φ ₁ angle of rotation of the crankshaft, determined by the resolution of the sensor 1 speed;
ν ₁ pulse frequency of the generator 3;
f _Cmin and f _{C max,} respectively, the minimum and maximum value of the equivalent time of rotation of the crankshaft from an array of numbers recorded in the first random access memory 21 within the engine cycle;
Φ _{2 the} angle of rotation of the crankshaft corresponding to the cycle of the engine, Φ ₂ = 4π ;;
ν _{2 the} frequency of the pulses of the generator 3, reduced kN times;
f _psr equivalent time of rotation of the crankshaft corresponding to the duration of the cycle of the engine;
δ _{C the} coefficient of uneven rotation within the cycle of the engine.

 The value of the coefficient of rotation unevenness is displayed on the first indicator 28.

 Next, the device is transferred to the mode of determining the maximum, minimum, average speed and coefficient of uneven rotation within successive periods of change in torque. In this case, the fourth driver 7 is blocked and the input logic circuit of the control unit 10 is opened for passing pulses through it from the second output of the frequency divider 9. These pulses are fed in series of N pulses to the counting input of the fifth counter 15 through the frequency divider of the main pulses of the speed sensor 1 of the control unit 10, one pulse per series to the counting input of the sixth counter 16. The value of N corresponds to the number of angular intervals within the period of change in torque . As a result of this, at the output of the fifth counter 15 codes of addresses of temporary equivalents recorded in the first random access memory 21 appear. At these addresses, sequences of N temporary equivalents are output to the output of the first random access memory 21, within each of which it is determined using the first 23, second 24 registers and the first 25 and second 26 elements of comparison their maximum and minimum values.

где f_пmin и f_пmax соответственно минимальное и максимальное значения эквивалентов времени поворота коленчатого вала в пределах периода изменения крутящего момента;
Φ₃ угол поворота коленчатого вала, соответствующий периоду изменения крутящего момента, Φ₃= 4π/K;;
Φ₃ частота импульсов генератора 3, уменьшенная в N раз;
f_пср эквивалент времени поворота коленчатого вала, соответствующий периоду изменения крутящего момента;
ω_{п max},ω_{п min},ω_{п cp} соответственно максимальное, минимальное и среднее значения частоты вращения в пределах периода изменения крутящего момента;
δ_п коэффициент неравномерности вращения в пределах периода изменения крутящего момента.The codes of the maximum and minimum values of time equivalents in each series of pulses are fed to the inputs of the switch of the calculator 27, which simultaneously receives the codes of the average values of time equivalents for each series from the output of the second random access memory 22. The calculator 27 sequentially calculates the actual values of the maximum, minimum, average frequency of rotation and coefficient of non-uniformity of rotation within the period of change of torque according to similar formulas

where f _pmin and f _pmax respectively the minimum and maximum values of the equivalents of the crankshaft rotation time within the period of change of torque;
Φ _{3 the} angle of rotation of the crankshaft corresponding to the period of change of torque, Φ ₃ = 4π / K ;;
Φ _{3 the} pulse frequency of the generator 3, reduced by N times;
f _psr equivalent time of rotation of the crankshaft corresponding to the period of change of torque;
ω _{p max} , ω _{p min} , ω _{p cp,} respectively, the maximum, minimum and average values of the rotational speed within the period of change of torque;
δ _{p the} coefficient of uneven rotation within the period of change of torque.

Hardware-based calculation of the rotational speed within the selected angular intervals is performed according to the universal formula
ω = A / f,
where f is the maximum, minimum or average equivalents of the crankshaft rotation time by a certain angle;
A constant coefficient.

The value of coefficient A is determined from the expression
A = Φ • ν,
where Φ] the angle of rotation of the crankshaft, within which the speed is measured;
n the corresponding pulse frequency of the generator 3.

 The obtained values of the coefficients of rotation unevenness as they are calculated are displayed on the first indicator 28.

 This cycle of measurement and processing of primary information within one cycle of the engine ends.

 The following are explanations of the operation of individual components of the device.

 The first 4 and second 5 shapers work as follows. The signal from the output of the (first or second) speed sensor 1 through the first resistor R1 (Fig. 4) is fed to the direct input of the first operational amplifier A1. The first capacitor C1 is designed to suppress high-frequency interference in the communication line of the sensor with the shaper. The gain of the first operational amplifier A1 is determined by the third resistor R3 included in the negative feedback circuit and is about 200. The amplified signal from the output of the first operational amplifier A1 is fed through the sixth resistor R6 to the direct input of the second operational amplifier A2, connected according to the Schmitt trigger circuit. The trigger threshold is determined by the voltage drop on the fourth R4 and fifth R5 resistors of the divider connected through the seventh resistor R7 to the inverse input of the second operational amplifier A2. From the output of the second operational amplifier A2, pulses with steep fronts, passing the second capacitor C2, are freed from the constant component, are amplitude-limited by the second V2 and third V3 diodes, and fed through the tenth resistor R10 to the input of the third operational amplifier A3. The latter is included in the comparator circuit. When the signal level at its input passes through zero at the output, a sharp change in the polarity of the output voltage with a large amplitude occurs. Next, the signal from the output of the third operational amplifier A3 is again limited in amplitude, converted into a pulse of positive polarity with the help of the eleventh resistor R11 and the zener diode V4, and fed to the input of the logical inverter D1. Due to this, the comparator output signal is matched with the inverter input D1, the input signal level of which should not exceed 4 V.

 The scheme of the third shaper 6 (Fig. 1) is similar to the schemes of the fourth 4 and fifth 5 shapers. The difference lies in the implementation of the first stage of the shaper, implemented on the first operational amplifier A1 (Fig. 5). The signal from the output of the synchronization sensor through the second resistor R2 is fed to the inverting input of the first operational amplifier A1, which has a small gain (k 2) and has a large input impedance (several MOhms) to match the large output impedance of the sensor. The trigger threshold of the Schmitt trigger, the function of which is performed by the second operational amplifier A2, is determined by the voltage drop at the sixth R6 and seventh R7 resistors included in the divider R5-R6-R7. The second A2 and third A3 operational amplifiers work similarly to the same amplifiers in the circuits of the first 4 (Fig. 1) and second 5 shapers of the speed sensor 1.

 The fourth shaper 7 operates as follows. The first input of the first circuit D6 (Fig. 6) matches each channel of the formation of signals constantly receives pulses from the second output of the frequency divider 9 (Fig. 1). With the arrival of a positive voltage drop from the fifth output of the control unit 10 to the second input of the first matching circuit D6 (Fig. 6) and the inputs of the inverter D14 of the "Reset" signal conditioning circuit of the first signal conditioning channel F7.1, the second matching circuit D7 of this chain is pulsed at its output resets the D-triggers D8-D13 of the ring counter and the trigger D15 of the ban. In this case, the inhibit trigger D15 opens the first coincidence circuit D6 for passing pulses through it to the input of the ring counter D8-D13. As the ring pulse counter arrives at the input, pulse “Record” from the output of the third trigger D10 and “Reset” from the output of the fifth trigger D12 appear sequentially at its outputs. With the appearance of a pulse at the inverse output of the sixth trigger D13, the inhibit trigger D15 goes into a single state and closes the first coincidence circuit D6 with an inverse output for further passage of pulses through it from the second output of the frequency divider 9 (Fig. 1). This completes the cycle of generating the “Write” pulse for the random access memory, for example, the first 21, and the “Reset” pulse for the counter, for example the first 11, from which the information on the “Write” pulse was recorded in the first random access memory 21.

 The second channel of signal generation F7.2 works similarly to the first, but the control pulses to its input from the second output of the control unit 10 come through the first inverter D2 (Fig. 6), thereby providing a sequential reset of the first 11 (Fig. 1) and second 12 counters after rewriting in the first random access memory 21 recorded in them information. For this, the “Write” pulses of the first F7.1 (Fig. 6) and the second F7.2 signal conditioning channels are combined using the first coincidence circuit D4.

 Similarly, the third F7.3 and fourth F7.4 signal generation channels work, which generate Reset pulses for the third 13 (Fig. 1) and fourth 14 counters after copying to the second random access memory 22 the values of time intervals fixed in them corresponding to periods changes in torque, and pulses "Record" for this random access memory, on which the rewriting of information occurs. In contrast to the first F7.1 (FIG. 6) and second F7.2 channels of signal generation, the frequency of pulses arriving at the second inputs of the input matching circuits of the third F7.3 and fourth F7.4 channel of signal generation from the fifth output of block 10 (FIG. 1) control, reduced by eight times using the divider D1 (Fig. 6).

 The fifth driver 8 (Fig. 1) works as follows. Pulses from the first output of the frequency divider 9 with a repetition period equal to the time of measuring the rotation frequency (0.60606 s) are fed to the synchronization input of the D-trigger D1 (Fig. 7). The latter generates rectangular pulses at the output that control the operation of the coincidence element D2 and form through the differentiating chain C1-R1-V1 reset pulses of the eighth counter 18 (Fig. 1).

With the arrival of the first pulse at the input of the D-trigger D1 (Fig. 7), it changes its state and a negative voltage drop appears on its inverse output, which is differentiated by the C1-R1-V1 chain and resets the eighth counter 18 (Fig. 1). At the same time, a positive voltage drop from the direct output of the D-flip-flop D1 (Fig. 7) opens coincidence element D2, as a result of which the filling of the eighth counter 18 (Fig. 1) begins with pulses from the output of the first driver 4 of the crankshaft speed sensor 1
With the appearance of the second pulse at the input of the D-flip-flop D1 (Fig. 7), it again changes its state, closing the coincidence element D2. At the same time, the number dialed by the eighth counter 18 (Fig. 1) is displayed on the second indicator 29.

 With the arrival of the third pulse at the input of the D-flip-flop D1 (Fig. 7), the cycle of measuring and indicating the speed is repeated.

 Block 10 (Fig. 1) control works as follows. Pre-signal "Reset" all the elements of the control unit 10 are set to their original state. When a signal is supplied using the first switch S1 (Fig. 8), the first coincidence element D7 opens and the next pulse arriving at the first input of the control unit 10 (Fig. 1) from the output of the third driver 6 of the synchronization sensor 2 (fuel injection pulse) sets the first trigger D21 (Fig.8) in a single state. By its direct output, this trigger opens the second coincidence element D8 for passing through it another pulse received at the second input of the control unit 10 (Fig. 1) from the output of the second driver 5 of the rotation speed sensor 1 (TDC pulse). In this case, the second trigger D22 (Fig. 8) goes into a single state and opens the fifth coincidence element D11 for passing through it the main pulses from the second output of the first frequency divider D1, which reduces the frequency of pulses received at its input by 4 times.

 The first main pulse from the output of the fifth coincidence element D11 is supplied simultaneously to the synchronization input of the synchronization trigger D29, the first and second synchronization inputs of the fifth frequency divider D5 and the first inputs of the tenth D16, eleventh D17 and twelfth D18 coincidence elements. The trigger D29 synchronization goes into a single state and with its direct output opens the seventh D13 and ninth D15 matching elements and puts the third trigger D23 in a single state. In this case, the pulses from the output of the generator 3 (Fig. 1) of the reference frequency (fourth input of the control unit 10) begin to flow through the second output of the control unit 10 to the counting input of the first counter 11. Simultaneously, the pulses from the output of the generator 3 of the reference frequency, passing the second D2 (Fig. .8) and the third D3 frequency dividers, come through the third coincidence element D9 and the tenth output of the control unit 10 (Fig. 1) to the input of the seventh counter 17 with the pulse frequency of the reference generator, reduced by 56 times. The pulse from the output of the fifth frequency divider D5 (Fig. 8) puts the seventh trigger D27 into a single state and opens its thirteenth coincidence element D19 through which pulses from the second output of the second divider D2 are fed through the sixth output to the counting input of the third counter 13 (Fig. . 1). At the same time, the positive voltage drop at the direct output of the seventh flip-flop D27 is supplied (Fig. 8) to the seventh output of the control unit 10 (Fig. 1) and then to the second (control) input of the second switch 20, to the first input of the sixth frequency divider D6 (Fig. 8) ) and through the second element D32 "OR" and output 9 to the input of the sixth counter 16 of the address (Fig. 1). The pulses from the output of the reference frequency generator 3, having passed the second frequency divider D2 (Fig. 8) and having reduced their frequency by 7 times, pass through the output 6 to the counting input of the third counter 13 (Fig. 1). The first main pulse from the output of the fifth coincidence element D11 (Fig. 8), received simultaneously at the first inputs of the tenth D16, eleventh D17, and twelfth D18 coincidence elements, does not pass through them, since no logical unit signals were formed at their second inputs at that moment .

 The second main pulse again changes the state of the synchronization trigger D29, which closes the seventh coincidence element D13 with its direct output, stopping the passage of reference frequency pulses through it to the counting input of the first counter 11 (Fig. 11), and opens the seventh coincidence element D14 with an inverse output (Fig. 8) to pass the reference frequency pulses through the fourth output to the counting input of the second counter 12 (Fig. 1). With the same signal from the inverse output of the trigger synchronization D29 (Fig. 8), the fifth trigger D25 is brought into a single state. The latter opens the ninth match element D15, which in turn opens the eleventh match element D17. In this case, the second main pulse passes through the eleventh coincidence element D17 and through the fifth output enters the second input of the fourth driver 7 (Fig. 1). The signal from the direct output of the trigger trigger D29 (Fig. 8) through the third output, the first switch 19 (Fig. 1) connects the output of the first counter 11 to the second (information) input of the first random access memory 21. The further process of recording information in the first random access memory 21 at the zero address and reset the first 11 and second 12 counters given earlier in the description of the invention.

 The third main pulse from the output of the fifth coincidence element D11 (Fig. 8) again changes the state of the synchronization trigger D29, as a result of which the seventh coincidence element D13 opens again, providing the reference frequency pulses to the counting input of the first counter 11 (Fig. 1), and closes the eighth coincidence element D14 (Fig. 8), stopping the arrival of these pulses at the counting input of the second counter 12 (Fig. 1). At the same time, the voltage drop at the direct output of the trigger synchronization trigger D29 (Fig. 8), having passed the ninth coincidence element D15, sets the sixth trigger D26, which opens its twelfth coincidence element D18 with its direct output. At this moment, the pulse acting on the first input of the twelfth coincidence element D18 appears at its output and through the first OR element D31 and the first output goes to the counting input of the fifth address counter 15 (Fig. 1), setting the first address code on its output . Thus, the pulse at the output of the first element D31 "OR" (Fig. 8) during the measurement process is allocated only with the arrival of the third main pulse. A delay of two main pulses is necessary to exclude writing to the first random access memory 21 (Fig. 1) at the zero address of a random number fixed by the second counter 12 before starting the measurement.

 When the engine crankshaft is rotated by an angle corresponding to the period of change in torque, i.e., when the eighth pulse coincides (Fig. 8) at the output of the fifth element D11, a voltage drop appears at the output of the fifth divider D5, which puts the seventh trigger D27 to zero. By a positive voltage drop at the inverse output of the seventh trigger D27, the fourteenth coincidence element D20 opens and through the eighth output, the reference frequency pulses from the second output of the second frequency divider D2 are fed to the counting input of the fourth counter 14 (Fig. 1). At the same time, the negative voltage drop at the direct output of the seventh flip-flop D27 (Fig. 8) stops receiving the reference frequency pulses through the thirteenth coincidence element D19 and the sixth output to the counting input of the third counter 13 (Fig. 1).

 The described process of operation of the control unit 10 in the measurement mode continues until the completion of the engine cycle. At the same time, a positive voltage drop appears on the second output of the sixth frequency divider D6 (Fig. 8), which opens the tenth coincidence element D16, and the main pulse acting on its first input passes to the installation input of the operating mode trigger D28 and puts it into a single state. A negative voltage drop at the inverted output of the D28 trigger of the operating mode closes the fifth D11, seventh D13, eighth D14, thirteenth D19 and fourteenth D20 coincidence elements and puts the third trigger D23 in the zero state, closing the third coincidence element D9 and stopping the passage of reference frequency pulses through it.

 At the same time, a positive voltage drop at the direct output of the operating mode trigger D28 opens the fourth coincidence element D10 for passing reference frequency pulses (fifth input) through it to the first input of the sixth coincidence element D12. At this point, the device is prepared for processing the measurement results by calculating the coefficient of rotation unevenness within the engine cycle, which is done by starting the calculator 27 (Fig. 1). To calculate the coefficient of non-uniformity of rotation within the first period of change of torque, press the second push-button switch S2 (Fig. 8). In this case, the fourth trigger D24 goes into a single state and opens the sixth coincidence element D12 for passing pulses to the first synchronization input of the fourth frequency divider D4 and through the inverter D30, the first OR element D31 and the first output to the counting input of the fifth address counter 15 (FIG. 1). When seven pulses arrive at the first synchronization input of the fourth frequency divider D4 (Fig. 8), a voltage drop appears on its second output, which puts the fourth trigger D24 to zero and the sixth coincidence element D12 closes. At the same time, this voltage drop through the second element D32 "OR" and the ninth output goes to the counting input of the sixth counter 16 (Fig. 1) with the subsequent formation of the code of the first address. After calculation, the value of the coefficient of rotation unevenness within the first period of change in torque appears on the first indicator 28. The values of the uneven rotation coefficients within the second and subsequent periods of change in torque are determined by periodically pressing the second push-button switch S2 (Fig. 8). On this, the cycle of operation of the control unit 10 (Fig. 1) ends and the signal "Reset" is again set to its original state.

 The first 19 and second 20 switches work similarly. Upon receipt at the second (control) input of the first switch 19 (20) (input 3, Fig. 9) a logic zero signal from the third output of the control unit 10 (Fig. 1), the number code present on the first input (bus 1, Fig. 9 ) of the first switch 19 (20), is transmitted to its output, that is, the information output of the first counter 11 (13) is connected to the second (information) input of the first random access memory 21 (22), after which the contents of this counter are copied to the first random access memory 21 (22). When applying to the second (control) input of the first switch 19 (20) a logical unit, the number code present on the second input (bus 2, Fig. 9) of the first switch 19 (20) appears at its output, that is, the information output of the second counter 12 (14) is connected to the second (information) input of the first random access memory 21 (22) and the contents of this counter are copied to the first random access memory 21 (22).

 Thus, the information outputs of the first (11) 13 and second 12 (14) counters are alternately connected to the second (information) input of the first random access memory 21 (22) depending on the state of the logical signal at input 3 (Fig. 9).

 The scheme of the first 25 (Fig. 1) and second 26 comparison elements works as follows. Before starting work, by pressing the push-button switch S1 (Fig. 1), the trigger D28 is returned to its initial state. In this case, the positive element from the inverse output of the trigger D28 opens the second element D27 "OR", as a result of which the first register 23 (Fig. 1) opens to record the first number. Upon receipt at the second input of the comparison element 25 (26) (bus 1, Fig. 10) of the code of the number recorded at the zero address in the first random access memory 21, this number is written to the first register 23 (24) and simultaneously comes from its output to the first input of the comparison element 25 (26) (bus 2, Fig. 10). Next, using the adders D1-D16, the numbers A and B are compared bitwise. Since A = B, then at the output of the third coincidence element 19, a logical zero (negative voltage drop) appears, which, having passed the third inverter D23 and the first element D26 "OR", transfers the trigger D28 to a single state, in which through the second element D27 "OR "control signals can only pass from the output of the fifth inverter D25. At the same time there is a similar record of the same number A in the second register 24 (Fig. 1). When the next number arrives at the second input of the comparison element 25 (26) (bus 1, Fig. 10), it is likewise compared with the number B using adders D1-D16.

 For the first comparison element 25 (Fig. 1), if A <B, then the fourth coincidence element D20 (Fig. 10) is activated and the signal from its output through the fifth inverter D25 and the second OR element D27 is fed to the synchronizing (control) input first register 23 (Fig. 1). According to this signal, in the first register 23, instead of the number B, the number A is written as a new number B. At the same time, the same numbers are compared in the second comparison element 26. Since the condition A <B is not fulfilled for it, the number in the second register 24 does not change.

 If A <B, then at the output of the fourth inverter D24 (Fig. 10) a signal appears that passes through the first element D26 "OR", but does not further affect the state of trigger D28. At the same time, the same comparison of numbers A and B occurs in the second comparison element 26 (Fig. 1). In this case, the signal from the output of the fourth inverter D24 (Fig. 10) enters through the second element D27 "OR" to the synchronizing (control) input of the second register 24 (Fig. 1), as a result of which the number A is written in it as a new number B.

 The described operation of the circuit then proceeds similarly as it arrives at the first input (bus) (Fig. 10) of numbers within the cycle of the engine. At the end of the cycle of the engine in the first 23 (Fig. 1) and second 24 registers are stored, respectively, the maximum and minimum values of numbers. To obtain similar numbers within the period of change in torque, you must first set the trigger D28 (Fig. 10) to its original state by pressing the push-button switch S1.

For the case of writing the code of the number A, if A = B, it should be noted that in reality, the number B means two numbers: B _max , if it is written in the first register 23 (Fig. 1), and B _min , if it is written in the second register 24. At the beginning of the search process for the maximum and minimum values of numbers B _max B _min . Then, as a result of sequentially sorting the values of the numbers contained in the first random access memory 21, the maximum (B _max ) and minimum (B _min ) values of numbers are stored in the first 23 and second 24 registers, that is, B _max ≠ B _min . In the case when, in the process of sequentially sorting the values of numbers, it turns out that A B _max or A B _min , then the code of the number A does not correspond respectively in the first 23 or second 24 registers. Moreover, the contents of the first 23 and second 24 registers naturally do not change and, therefore, this case does not affect the final result, which consists in finding the maximum and minimum values of numbers from a given sequence.

 The proposed device is most appropriate to use for diagnosing the technical condition of cars, tractors, combines and other agricultural and road-building machines during their maintenance and repair in road transport, agriculture, construction and road facilities, as well as for fine-tuning, testing and quality control of manufacturing internal combustion engines at manufacturing plants of the automotive industry, tractor, agricultural and road construction engineering.

 The use of the device allows, in comparison with existing devices, to increase the accuracy of monitoring the unevenness of rotation of the crankshaft of internal combustion engines, to increase the reliability of engine diagnostics due to the possibility of determining the technical condition of individual cylinders, and therefore, to improve the manufacturing quality and operational reliability of engines and reduce the cost of maintaining their operability in operation process.

Claims (9)

 1. Device for monitoring uneven rotation of the shaft of an internal combustion engine, comprising a speed sensor, first and second formers, first counter, first and second registers, first and second comparison elements, a pulse generator, a computer and a first indicator, the first output of the speed sensor connected to the input of the first driver, the direct information output of the first register is connected to the first input of the calculator and the first input of the first comparison element, and the direct information output of the second the histra is connected to the second input of the calculator and the first input of the second comparison element, the output of the calculator is connected to the input of the first indicator, characterized in that a synchronization sensor, a third, fourth and fifth drivers, a frequency divider, a control unit, a second, third, fourth, are introduced into it fifth, sixth, seventh and eighth counters, first and second switches, first and second random access memory and a second indicator, and the output of the synchronization sensor is connected to the input of the third driver, the output of which connected to the first input of the control unit, the second output of the speed sensor is connected to the input of the second driver, the output of which is connected to the second input of the control unit, the output of the first driver is connected to the third input of the control unit and the first input of the fifth driver, the output of the pulse generator is connected to the fourth input of the unit control and the input of the frequency divider, the first output of which is connected to the second input of the fifth driver, the second output to the fifth input of the control unit and the first input of the fourth driver device, the first output of the control unit is connected to the counting input of the fifth counter, the second output of the control unit is connected to the counting input of the first counter, the information output of which is connected to the first input of the first switch, the third output of the control unit is connected to the second input of the first switch, the fourth output of the control unit is connected to the counting input of the second counter, the information output of which is connected to the third input of the first switch, the fifth output of the control unit is connected to the second input of the fourth form leveler, the first and second outputs of which are connected to the zeroing inputs of the first and second counters, the third and fourth outputs to the first inputs of the first and second random access memory, and the fifth and sixth outputs to the zeroing inputs of the third and fourth counters, the sixth output of the control unit connected to the counting input of the third counter, the information output of which is connected to the first input of the second switch, the seventh output of the control unit is connected to the second input of the second switch, the eighth output of the control unit is connected to the counting input of the fourth counter, the information output of which is connected to the third input of the second switch, the ninth and tenth outputs of the control unit are connected to the counting inputs of the sixth and seventh counters respectively, the information outputs of the first and second switches are connected to the second inputs, respectively the first and second operational storage devices, the third inputs of which are connected to the information outputs of the fifth and sixth counters, respectively the first and second outputs of the fifth shaper are connected respectively to the counting input and the zeroing input of the eighth counter, the output of which is connected to the input of the second indicator, the information output of the first random access memory is connected to the information inputs of the first and second registers and second inputs of the first and second comparison elements, the outputs of which connected to the synchronizing inputs of the first and second registers, respectively, and the information outputs of the seventh counter and the second operational memory his device, respectively to third and fourth inputs of the calculator.  2. The device according to claim 1, characterized in that the pulse generator contains the first, second and third logical elements 2 AND NOT, resistors, a capacitor and a quartz resonator, the inputs and outputs of the first and second logical elements are interconnected via resistors, the output of the first logical the element is connected through a capacitor to the inputs of the second logic element, the output of which is connected to the inputs of the third logic element and through a quartz resonator with the inputs of the first logic element, and the output of the third logic element Exit pulse generator.  3. The device according to claim 1, characterized in that the first and second formers contain each first, second and third capacitors, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh resistors, the first, the second and third operational amplifiers, the first, second and third diodes, a zener diode and an inverter, and the direct input of the first operational amplifier is connected through a series-connected first resistor and first capacitor to a source of zero potential, and the connection point of each form of the converter, the inverse input of the first operational amplifier is connected through a second resistor to a source of zero potential, the first power input of the first operational amplifier is connected to a positive voltage source, the second input to a negative voltage source, and the output through a third resistor is connected to its inverse input and through a sixth resistor with a direct input of the second operational amplifier, the fourth and fifth resistors connected in series are connected respectively to a positive voltage source a source of zero potential, and the point of their connection is connected through the seventh resistor to the inverse input of the second operational amplifier, the first power input of which is connected to a positive voltage source, the second power input to a source of zero potential, and the output of the second operational amplifier is connected through its eighth resistor direct input, which is connected to the cathode of the first diode, the anode of which is connected to a source of zero potential, the output of the second operational amplifier through series-connected the second capacitor, the ninth and tenth resistors are connected to the inverse input of the third operational amplifier, the connection point of the ninth and tenth resistors is connected in parallel to the second and third diodes and the third capacitor is connected to a source of zero potential, and the cathode of the second diode is connected to the anode of the third diode, direct input and the correction input of the third operational amplifier is connected to a source of zero potential, the first power input of the third operational amplifier is connected to a positive source voltage, the second power input with a negative voltage source, and the output through the eleventh resistor is connected to the inverter input, which is connected to the zener diode cathode, the anode of which is connected to a zero potential source, and the inverter output is the output of each driver.  4. The device according to claim 1, characterized in that the third driver includes a first, second, third, fourth, fifth, sixth, seventh trimmer, eighth, ninth, tenth, eleventh, twelfth and thirteenth resistors, first, second and third operational amplifiers , the first, second and third diodes, the first and second capacitors, a zener diode and an inverter, and the direct input of the first operational amplifier is connected through the first resistor to a source of zero potential, the inverse input through the second resistor to the input of the third shaper, the first the first power input of the first operational amplifier is connected to a positive voltage source, the second power input to a negative voltage source, and the output through the fourth resistor is connected to its inverse input, which is connected through a third resistor to a source of zero potential, the output of the first operational amplifier through a ninth resistor is connected to direct input of the operational amplifier, the fifth, sixth and seventh tuning resistors connected in series are connected by the fifth resistor to the source of positive voltage and the seventh trimming resistor to the source of zero potential, and the connection point of the fifth and sixth resistors is connected through the eighth resistor to the inverse input of the second operational amplifier, the output of which is connected through the tenth resistor to the direct input of the second operational amplifier, which is connected to the cathode of the first diode, the anode of which connected to a source of zero potential, the output of the second operational amplifier through series-connected first capacitor, eleventh and twelfth resistors connected to the inverse input of the third operational amplifier, the connection point of the eleventh and twelfth resistors through parallel connected second and third diodes and the second capacitor is connected to a source of zero potential, the cathode of the second diode connected to the anode of the third diode, the direct input and the correction input of the third operational amplifier are connected to a source of zero potential, the first power input of the third operational amplifier is connected to a positive voltage source, the second power input from a source com negative voltage via a thirteenth resistor output connected to the input of the inverter, which is connected to the cathode of the zener diode, the anode of which is connected to the zero potential source and the output of the inverter output of the third driver.  5. The device according to claim 1, characterized in that the fourth driver includes a frequency divider, first and second inverters, first and second coincidence circuits, first, second, third and fourth channels of signal generation, each of which contains the first and second coincidence circuits, the first, second, third, fourth, fifth and sixth D-flip-flops, an inverter, a prohibition trigger and a capacitor, with the first inputs of the first coincidence circuit of the first, second, third and fourth signal conditioning channels being connected in parallel, the first input of the fourth the driver, the parallel input of the first inverter, the first synchronization input of the frequency divider, the second input of the first matching circuit of the first signal conditioning channel, the first and second inputs of the inverter of the first signal conditioning channel and the first input of the second matching circuit of the first signal conditioning channel, the second input of the fourth driver, the output of the first the inverter is connected to the second input of the first matching circuit of the second signal conditioning channel, the first output of the frequency divider is connected to its second input syn ronization, the second output is connected to the second input of the first matching circuit of the third signal conditioning channel and the input of the second inverter, the output of which is connected to the second input of the first matching circuit of the fourth signal conditioning channel, the inverter output in each signal conditioning channel is connected through the capacitor to the zero potential source and the second the input of the second coincidence circuit, the output of which is connected to the R-inputs of the first, second, third, fourth, fifth, sixth D-flip-flops and the inhibition trigger, the inverse output to the other is connected to the third input of the first coincidence circuit, the output of which is connected to the synchronization input of the first D-trigger, the inverse output of which is connected to the synchronization inputs of the second, third, fourth, fifth and sixth D-triggers and the D-input of the first D-trigger, inverse output the second D-trigger is connected to the D-input of the third D-trigger, the direct output of which is connected to the D-input of the fourth D-trigger, the output of which is connected to the D-input of the fifth D-trigger, the output of which is connected to the D-input of the sixth D-trigger whose inverse output is connected is denied with the D-input of the second D-trigger and the S-input of the inhibit trigger, the inverse outputs of the fifth D-triggers of the first and second signal conditioning channels, respectively, the first and second outputs of the fourth driver, the inverse outputs of the third D-triggers of the first and second signal conditioning channels are connected, respectively to the first and second inputs of the first coincidence circuit of the fourth driver, the output of which is the third output of the fourth driver, the inverse outputs of the third D-flip-flops and the fourth signal conditioning channels are connected s, respectively, with the first and second inputs of the second matching circuit of the fourth shaper, the output of which is the fourth output of the fourth shaper, the inverse outputs of the fifth D-flip-flops of the third and fourth channels of signal generation, respectively, the fifth and sixth outputs of the fourth shaper.  6. The device according to claim 1, characterized in that the fifth driver includes a D-trigger, capacitor, resistor, diode and a matching element, wherein the first input of the matching element is the first input of the fifth driver, the synchronization input of the D-trigger is the second input of the fifth driver, direct output The D-flip-flop is connected to the second input of the coincidence element, the output of which is the first output of the fifth driver, the inverse output of the D-flip-flop is connected to its D-input and, through a capacitor and a parallel-connected resistor and diode, is connected to a positive voltage source voltage, and the cathode of the diode is connected to the source of positive voltage, and the connection point of the capacitor, resistor and diode is the second output of the fifth shaper.  7. The device according to p. 1, characterized in that the control unit comprises a first, second, third, fourth, fifth and sixth frequency dividers, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh , twelfth, thirteenth and fourteenth coincidence elements, first, second, third, fourth, fifth, sixth and seventh triggers, mode trigger, synchronization trigger, inverter, first and second elements OR, first and second push buttons, the first input of the first element matches first entry control lock, the second input of the first coincidence element is connected through the first push-button switch to a source of zero potential, and the output is with the S-input of the first trigger, the direct output of which is connected to the first input of the second coincidence element, the second input of which is the second input of the control unit, the output of the second coincidence element connected to the S-input of the second trigger, the direct output of which is connected to the first input of the fifth coincidence element, the first synchronization input of the first frequency divider, the third input of the control unit, the first and second the Rth inputs of the first frequency divider are connected to a source of zero potential, the first output is connected to its second synchronization input, and the second output is connected to the second input of the fifth coincidence element, the first synchronization input of the second frequency divider is connected in parallel, the first inputs of the seventh and eighth coincidence elements are the fourth the input of the control unit, and the first input of the fourth coincidence element, the fifth input of the control unit, the first and second R-inputs of the second and third frequency dividers are connected to the source of zero sweat In this case, the first output of the second frequency divider is connected to its second synchronization input, and the second output with the first inputs of the thirteenth and fourteenth coincidence elements and the first synchronization input of the third frequency divider, the first output of which is connected to its second synchronization input, and the second output to the first input of the third coincidence element, the output of the fifth coincidence element is connected to the first inputs of the tenth, eleventh and twelfth coincidence elements, the first and second synchronization inputs of the fifth divider you and the synchronization trigger input, the inverse output of which is connected to its D-input, the second input of the eighth match element and the synchronization input of the fifth trigger, whose direct output is connected to the first input of the ninth match element, the output of which is connected to the second input of the eleventh match element and the input synchronization of the sixth trigger, the direct output of which is connected to the second input of the twelfth coincidence element, the output of which is connected to the first input of the first element OR, the direct output of the trigger The synchronization ra is connected to the second input of the ninth coincidence element, the second input of the seventh coincidence element and the synchronization input of the third trigger, the output of the fifth frequency divider is connected to the synchronization input of the seventh trigger, the direct output of which is connected to the second input of the thirteenth coincidence element, the first input of the second OR element and the first the synchronization input of the sixth frequency divider, the inverse output of the seventh trigger to its D-input and the second input of the fourteenth coincidence element, the first output of the sixth divides For frequency, it is connected to its second synchronization input, and the second output to the second input of the tenth coincidence element, the output of which is connected to the S-input of the operating mode trigger, the direct output of which is connected to the second input of the fourth coincidence element, and the inverse output to the third inputs of the fifth, seventh , eighth, thirteenth and fourteenth coincidence elements and D- and R-inputs of the third trigger, the direct output of which is connected to the second input of the third coincidence element, the output of the fourth coincidence element is connected to the first input the sixth coincidence element, the output of which is connected to the first synchronization input of the fourth frequency divider and the inverter input, the output of which is connected to the second input of the first OR element, whose output is the first output of the control unit, the first output of the fourth frequency divider is connected to its second synchronization input, the second output with the second input of the second element OR and the D- and R-inputs of the fourth trigger, the C-input of which is connected to the source of zero potential through the second push-button switch, and the direct output to the second input is sixth about the coincidence element, the output of the seventh coincidence element the second output of the control unit, the direct output of the synchronization trigger the third output of the control unit, the outputs of the eighth, eleventh and thirteenth coincidence elements, respectively the fourth, fifth and sixth outputs of the control unit, the direct output of the seventh trigger the seventh output of the control unit, the outputs the fourteenth match element, the second OR element, and the third match element, respectively, the eighth, ninth, and tenth outputs of the control unit.  8. The device according to claim 1, characterized in that the first and second switches contain each first, second, third, fourth, fifth, sixth, seventh and eighth two-digit multiplexers, the first information inputs of each discharge of all multiplexers, the first input of each switch, the second the inputs of each switch, the second information inputs of each category of all multiplexers, the second input of each switch, the first address inputs of all multiplexers connected in parallel, the third input of each switch, in parallel The second address inputs of all multiplexers are connected to a source of zero potential, and the first and second outputs of all multiplexers are the output of each switch.  9. The device according to p. 1, characterized in that the first and second comparison elements contain every first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth one-bit adders, first, second, third and fourth elements of coincidence, first, second, third, fourth and fifth inverters, first and second OR elements, a trigger and a push-button switch, the first input of the first adder connected to a source of zero potential, the first input The second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth adders are connected to the transfer outputs of the first, second, third, fourth, fifth, sixth, seventh, respectively the eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth and fifteenth adders, the second inputs of all adders the first input of each element of comparison, the transfer inputs of all adders the second input of each element This comparison, the outputs of the sum of the first, second, third, fourth, fifth, sixth, seventh and eighth adders are connected respectively to the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of the first matching element, the outputs of the sum of the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth and sixteenth adders respectively to the first, second, third, fourth, fifth, sixth, seventh and eighth inputs of the second matching element, the outputs of the first and second coincidence elements are connected to the inputs of the first and second inverters respectively, the outputs of which are connected respectively to the first and second inputs of the third coincidence element, the output of which is connected to the first input of the fourth coincidence element and through the third inverter with the first input of the first OR element, the transfer output of the sixteenth adder is connected to the input of the fourth inverter and the second input of the fourth element of coincidence, the output of which through the fifth inverter is connected to the second input of the first element OR, the output is four of the second inverter is connected to the third input of the first OR element, the output of which is connected to the S-input of the trigger, the R-input of which is connected via a push-button switch to a source of zero potential, the inverse output of the trigger is connected to the first input of the second OR element, while for the first comparison element the second the input of the second OR element is connected to the output of the fifth inverter, for the second comparison element, the second input of the second OR element to the output of the fourth inverter, and the output of the second OR element is the output of each Eden.

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