RU2068602C1 - Large integral circuit - Google Patents

Abstract

FIELD: microelectronics. SUBSTANCE: circuit has crystal holder, which is designed as plate of single- crystal semiconductor material which crystal is oriented in (100). Physical layers of multiple-level commutation circuit are generated on surface of said plate. Commutation system has contact areas which provide certain combinations for locating crystals which are mounted by means of reverse crystal method, as well as single chip integral circuits and components of micro electronic design. Crystals are made from single-crystal material, are oriented in (100) and shaped as frustum of pyramid which side walls are shaped as sets of equilateral trapeziums which are generated by set of crystal planes {111}. Crystal holder support surface has conductor which is made from single-crystal semiconductor material which has through holes in which crystals of single-chip integral circuits and components are located. Through holes in conductor conform to shape and size of crystals. EFFECT: increased functional capabilities. 1 dwg

Description

 The invention relates to the field of microelectronics and can be used in the manufacture of semiconductor integrated circuits (ICs) with a large (LSI) and ultra-large (VLSI) degree of integration, as well as in the production of multi-chip modules (MKM) and other hybrid microassemblies of units and blocks of electronic equipment ( IET) and electronic equipment (REA) of increased complexity, with advanced functionality and small overall dimensions.

There are known designs of large integrated circuits and other tightly packed devices, the descriptions of which are presented in the materials of Japanese applications [2-4,6] and patent documents of other countries [5,7-9]
The application materials [2-4,5] provide descriptions of the designs of large integrated circuits based on the implementation of the principle of "integration on a whole plate", when after the formation of physical layers of 3-7 types of monolithic ICs located on the surface of a single semiconductor plate, functional control methods carry out the fixation of either functionally suitable crystals of monolithic IP, or individual functionally complete blocks and nodes of IP. Then, using the methods of computer-aided design and tracing, they form individually for each plate a multi-level wiring that allows you to connect functionally suitable crystals or individual blocks of monolithic ICs into a single functionally complete system or device.

 The application materials [6-8] provide descriptions of the designs of close-packed devices and IET and REA units based on the implementation of the principles of mounting monolithic IC crystals on the surface of foreign plates with formed switching systems that allow combining individual monolithic ICs made using different technologies into a functionally complete device or block placed on a single basis.

 The materials [9] describe a silicon substrate with universally programmable interconnects, called the Unipro SSB and containing a network of thin-film metal interconnects that are separated at the intersection by a thin layer of amorphous polycrystalline silicon. When a voltage of about 20 V is applied to the intersection, the amorphous silicon becomes conductive, forming a "custom" interconnect. Components, including crystals of monolithic ICs, are fastened by means of epoxy glue, and the contact pads of the mounted crystals with metal interconnects of the switching board are switched using conductive conductors.

The main disadvantages of the designs of large integrated circuits and multichip modules based on them, the description of which is presented in the materials of patent documents [2-4.5] are:
low values of reliability characteristics, which is associated with insufficient information during functional control of monolithic IC crystals in the wafer composition;
the individuality of creating a switching system for each plate due to the unpredictability of the distribution of functionally suitable crystals or blocks of monolithic ICs placed on one plate;
the inability to use semiconductor devices manufactured using various technologies;
the need to create technological processes and techniques that ensure the planarization of the surface relief of a large area.

The main disadvantages of the designs of close-packed assemblies and blocks of IET and REA, the description of which are presented in the materials of patent documents [6-8], should include:
low density of installation associated with the inability to create busbars with a width of less than 100 microns;
low reliability indicators associated with the use of materials with different coefficients of thermal expansion (CTE);
difficulties associated with solving the problems of heat dissipation during the operation of thermal power;
low rates of maintainability;
high cost of manufacturing and testing;
the widespread use of severely deficient and precious metals, which significantly worsens the technical and economic indicators of production.

The main disadvantages of the design, the description of which is presented in the materials [9] should include:
low manufacturability associated with the need to use monolithic ICs for fixing crystals on the surface of a substrate with a switching system of various adhesive compositions, which to a large extent leads to an increase in thermal resistance;
the process of mounting crystals of monolithic ICs on the surface of the circuit board in an automatic mode is complicated, which is associated with the use of adhesive compositions as fixing elements;
difficulties with the installation of crystals on the surface of a circuit board made of single-crystal silicon, which is associated with the need to use precision optical equipment with a large depth of field;
the absence of a protective coating for the switching system of the circuit board in most practical cases of use can lead to a decrease in reliability characteristics or a decrease in the time between failures;
the device’s functionality is limited due to the use of only two levels of interconnects made of aluminum as a switching system;
insufficient level of installation density associated with the need to use busbars of interconnects made of aluminum as contact pads of the switching system of the circuit board, which makes the application of the known design very limited.

The closest in technical essence solution is the design of a large integrated circuit [2]
The known design provides the highest density of the layout of the currently known designs of close-packed structures of nodes and blocks, but at the same time, the known design has a number of significant drawbacks, which include:
the need to use technical vision tools for mounting monolithic IC crystals, which significantly reduces the technical and economic indicators of the production of functionally complex components and assemblies of IET and CEA;
the volume of the material of the crystal holder is not used effectively, in the known construction of the semiconductor wafer, a purely passive role is assigned, it acts as a crystal carrier and serves as a substrate for the formation of the physical layers of the switching system;
low degree of automation of installation and assembly processes associated with the use of expensive precision optical equipment with a large depth of field;
low reliability associated with the small plate thickness of the semiconductor material used as the starting material.

 The above listed disadvantages of the known design adopted for the prototype significantly complicate the use of the known design as the basis for the creation of nodes and blocks of IET and REA of the increased complexity group used in the construction of electronic watches (ELF), personal computers (PCs), workstations ( AWP) on the basis of the latter, as well as other devices and products for household, general industrial or special purposes.

 The aim of the invention is to increase the reliability and manufacturability of the manufacture of large integrated circuits.

This goal is achieved by the fact that in a large integrated circuit containing a crystal holder made of a single-crystal semiconductor material with a crystallographic orientation of (100), with a multi-level switching system formed on its surface, on the contact pads of which are made contacting bodies partially placed in the volume of the semiconductor material, made in the form of spherical or columnar leads coated with a layer of solder, and at least one semiconductor crystal boron with contact pads, a conductor in the form of a plate of a single-crystal semiconductor material with a crystallographic orientation of (100) is mounted on the surface of the crystal holder, made with an opening in which a crystal is placed, the side surface of which and the side surface of the hole are conformal and made in the form of isosceles trapezoidal formed by families crystallographic planes III} and the bases of the crystal and the holes are rectangles formed by crystallographic planes (100), moreover, the linear dimensions of the holes are selected from the ratio:
L _cond L _cr + 1,41 (N _cond N _{body cont} ),
where L _{cr the} linear crystal size of the semiconductor device, microns;
L _cond linear size of the base of the hole of the conductor, microns;
H _{cond the} thickness of the conductor body, microns;
N _{body contact body} height contact, microns.

 The drawing shows a transverse vertical section of the structure of a large integrated circuit.

 The large integrated circuit contains the first single-crystal silicon wafer 1, the working surface of which is oriented in the direction of the crystallographic plane (100), signal buses 2 and 3 of a multilevel switching system formed on the surface of the wafer that functions as a crystal holder, layers of an interlayer dielectric 4, protective dielectric 5, contact platforms 6 of the switching system of the crystal holder, made in the upper level of metallization of the contacting body 7, located on the contact area 6 and bottom 8 buried in the volume of the material of the semiconductor crystal holder, diffusion regions of the semiconductor 9 p-type conductivity, in the volume of the material of which are buried contact bodies, layers of tin 10 and indium 11, which act as solder, contact pads 12 of monolithic ICs and other components in microelectronic performance, ensuring the operability of the device as a whole, crystals of monolithic IC 13 mounted on familiarity, formed by the contact bodies of the crystal holder, polycrystalline layers silicon 14, which acts as a damping layer and separates the lower part of the contact bodies from the volume of the crystal carrier material, the jig 15, which is a single-crystal silicon plate, the working surface of which is oriented in the direction of the crystallographic plane (100), with through holes 16, which serve to accommodate monolithic crystals IC, side faces of 17 crystals of monolithic ICs, bases of crystals 18 and 19 of monolithic ICs, side faces of 20 through-holes of the conductor, layers of silicon dioxide 21 and 22 on the surface of the conductor and crystals of monolithic ICs.

 The following are examples of the practical implementation of the design of a large integrated circuit.

 Example 1

 On the surface of the semiconductor wafer 1, which is a single crystal silicon wafer 100 KEF 4.5 (100) -480, which meets the requirements of ETO.035.206 TU, ETO.035.217 TU, ETO.035.240 TU or ETO.035.245 STU of n-type conductivity, performing simultaneously the functions of the carrier base and the circuit board, using the methods of planar technology, a multilevel switching system is formed, consisting of two levels of metallized conductive signal buses 2 and 3, an interlayer dielectric 4, a protective layer 5, contact pads 6 with the surface of the latter by contacting bodies 7, made in the form of spherical or columnar leads. The lower part 8 of the contacting bodies 7 is partially buried in the near-surface volume 9, which is a region of the p-type semiconductor. The upper part of the contacting bodies 7 is covered with layers of indium 10 and tin 11 having a low melting point and performing the functions of solder, while the contacting body 7 is made of copper. To compensate for various kinds of mechanical stresses arising both under the influence of temperature influences and during mechanical influences during installation and connection of contact pads 12 crystals of monolithic IC 13 or other components in microelectronic design, ensuring the operability of the device as a whole, lower part 8 of the body contacting is separated from the volume of the semiconductor wafer 1 by a layer 14 of polycrystalline silicon, a thickness of 0.1-0.65 μm, which performs the function of damping th structural element.

A conductor 15 is mounted on the surface of the plate 1, which is a 100 KEF 4.5 (100) -480 single-crystal silicon wafer that meets the requirements described above. Through holes 16 are formed in the plate 15, the shape and geometric dimensions of which conformally reproduce the shape and geometric dimensions of the respective crystals 13 of monolithic ICs. In this case, crystals 13 are made in the form of truncated pyramids, the lateral faces of which are sets of isosceles trapeziums formed by a family of crystallographic planes. III} The lateral faces of 17 crystals of monolithic ICs form with base planes 18 or 19, which are rectangles formed by crystallographic planes (100), the angle 54.75 ^o or 125.25 ^o . On a smaller base 18 of a monolithic IC crystal, physical layers of a monolithic IC or other components are formed in microelectronic design with switching systems equipped with contact pads 12 in direct physical and electrical contact with contact bodies 7 due to the formation of soldered contact with metals 10 and 11 covering contacting bodies 7.

 The contacting bodies 7 in certain combinations form familiarities for monolithic IC 13 crystals mounted by the inverted crystal method, which is also limited by the side faces 20 of the through holes 16 of the conductor. In this case, the lateral faces 20 serve as guides during the installation of crystals 13, which allows the use of crystals 13 in the corresponding holes of the conductor until the contact pads 12 are in contact with the upper parts of the contact bodies 7 without using expensive vision systems.

 Due to the fact that the linear size of the through hole of the conductor 16 is always larger than the linear size of the base 18 of the crystal 13 of the monolithic IC, it is possible to automatically mount the crystals 13 into the through holes of the conductor 16 with subsequent heating of either individual mounted crystals of the monolithic ICs or of all crystals 13 mounted in through holes 16, to temperatures at which the solder layers 10 and 11 melt and the formation of a eutectic layer, creating a soldered contact with the material pad 12.

Due to the fact that both the through holes 16 of the conductor 15 and the crystals 13 of the monolithic ICs were obtained using the methods of photolithographic processing and anisotropic etching, the following relation between the linear dimensions of the structural elements of a large integrated circuit is fulfilled:
L _cond L _cr + 1,41 (N _cond N _{body cont} ),
where L _{cr the} linear crystal size of the semiconductor device, microns;
L _cond linear size of the base of the hole of the conductor, microns;
H _{cond the} thickness of the conductor plate, microns;
N _body contact _body height, microns.

 Due to the fact that the surface of the body of the conductor 15, as well as the surface of the side faces 20 of the through holes 16, is covered with layers 21 of silicon dioxide, and the diffusion of germanium atoms is carried out in the side faces 17 of the mounted crystals 13, it is possible to fix the crystals 13 of monolithic ICs in the through holes 16 conductor due to the formation of glasses with a low melting point.

 Example 2

 The design of the large integrated circuit is similar to the design described in Example 1, except that 100 KDB 10 (100) -480 single-crystal silicon wafers that meet the requirements of the above specifications are used as the material of both the crystal holder and the conductor.

 A large integrated circuit of the proposed design works as follows.

 On the signal lines 2 and 3 of the multilevel switching system of the crystal holder 1, the signal from the external device through the contacting bodies 7 is fed to the contact pads 12 of monolithic integrated circuits 13 located in the through holes 16 of the conductor 15 mounted on the surface of the crystal holder 1, and is processed through the contacting bodies 7 and signal buses 2 and 3 of the multilevel switching system of the crystal holder enters the external contact pads of a large integrated circuit, connected to external devices oystvami.

 The design of a large integrated circuit, in the manufacturing cycle of which the techniques and methods of planar technology are widely used, will find wide application in the creation of assemblies and blocks of IET and REA of an increased complexity group with expanded functional capabilities, improved mass-dimensional parameters and increased reliability characteristics in the production of electromechanical and electronic watches, in the production of information panels on LCD indicators, highly stabilized secondary sources Power Cove, computer facilities, such as "A million on the table," such as computers and computer workstations.

Using the proposed design of a large integrated circuit in comparison with the design of a large integrated circuit adopted as a prototype allows you to get the following advantages:
automate the process of mounting crystals of monolithic ICs through the use of a conductor with through holes, the side faces of which serve as guides;
reduce production costs due to the rejection of the use of expensive high-precision equipment for the installation of crystals, in particular means of technical vision;
to increase the reliability of the design of a multi-chip assembly due to the precise positioning of crystals of monolithic ICs in the through holes of the conductor;
to increase the mechanical strength of the structure by increasing the total thickness of the crystal holder, taking into account the thickness of the conductor plate;
provides precision mounting of monolithic IC crystals due to the use of planar technology and selective etching processes in the manufacturing technological cycle;
allows to increase the production efficiency of semiconductor devices due to the use of single-crystal silicon wafers that have been rejected at certain stages of the technological cycle of manufacturing semiconductor devices as starting materials for the crystal holder and conductor create non-waste production.

Claims (1)

A large integrated circuit containing a crystal holder made of a single-crystal semiconductor material with a crystallographic orientation of (100), with a multi-level switching system formed on its surface, on the contact pads of which are made contacting bodies partially placed in the volume of the semiconductor material, made in the form of spherical or bar terminals, coated with a layer of solder and at least one crystal of a semiconductor device with contact pads, featuring In order to increase reliability and manufacturability, a conductor is installed on the surface of the crystal holder in the form of a plate of a single-crystal semiconductor material with a crystallographic orientation (100), made with an opening in which a crystal is placed, the side surface of which and the side surface of the hole are conformal and made in the form of isosceles trapeziums formed by families of crystallographic planes III} and the rectangles formed by the crystal serve as the bases of the crystal and the hole graphic planes (100), and the linear dimensions of the hole are selected from the relation:
L _{to about n d} L _{to p} + 1.41 (N _{c o n d} H _{m l f o n a to t} ), where L _{to p} linear crystal size of a semiconductor device, microns;
L _{to about n d} linear size of the base of the hole of the conductor, microns;
N _{to o n d} conductor plate thickness, microns;
H _{m l f o n a to t.} - contact body height, microns.