RU2060593C1 - Method for encoding digital information and device for implementation of said method - Google Patents

Abstract

FIELD: computer engineering, devices for communications. SUBSTANCE: method involves splitting data packet into several data units and their encoding. Operation of unit encoding is embraced by two feedback circuits: by information data unit and by additional data unit, which is generated during each operation of unit encoding and depends on information data unit that has been processed before and on encoding password. Method may be used for sending confidential digital information through inter-computer communication lines. Device has multiplexer, encoding unit, information memory unit, unit of registers. EFFECT: increased speed. 2 cl, 3 dwg

Description

 The invention relates to computer and communication technology and can be used to encode digital confidential information stored in a computer and transmitted via inter-machine communication channels.

 There is a method of encoding digital information of a small volume or its individual blocks (data blocks), which consists in multi-stage encoding of a data block, in which the data block at each stage is divided into several segments, to which substitution operations are sequentially applied.

 The disadvantage is the practical impossibility of encoding large blocks (more than 128 bits), which requires a preliminary breakdown of digital information into a large number of data blocks and the introduction of a data block integrity control segment into each data block, as well as the complexity of the device.

 A known method of encoding data blocks, which consists in independent block coding of data blocks. The device comprises a first register, a first multiplexer, a permutation node, a second adder, a nonlinear block and a first adder, the output of which is the first output of the device and connected to the input of the first register, the output of which is the second output of the device, the first input of which is the second input of the multiplexer, whose output is connected through a series-connected second register and a second multiplexer connected to the second input of the first adder, as well as a random access memory block, the output of which dklyuchen to the second input of the first adder, the input memory unit is the input device key information, whose second input is the second input of the second multiplexer.

 A disadvantage of the known technical solution is the need to modify, when encoding each data block, a large amount of key information, which leads to the need to separate the functions of encoding information and modify key information in time and, accordingly, to low device performance.

 The goal of improving performance.

 In FIG. 1 and 2 are structural diagrams of a device explaining the essence of a method for encoding digital information; figure 3 structural electrical diagram of a device for encoding digital information.

 The digital information encoding device comprises a multiplexer 1, an encoding unit 2, a memory information block 3, a register block 4.

 The data block coding method is based on the coverage of the block coding operation by two feedback circuits (OS). The first OS chain (OS1) returns the encoded information data subunits S 'for re-encoding. The second OS chain (OS2) returns the auxiliary code block 1 generated by the block coding operation, which is a function of the current encoded information block, the auxiliary code block generated during the previous block coding operation, and the key for encoding the subsequent information block. According to this definition, the auxiliary code block depends on the current information block and all previous ones. The coded information subblock is also a function of the current information block and all previous ones.

 Of the two chains of OS OS1 and OS2, one is internal and the other external.

 With internal OS2, the coding of all information blocks of data S1 SN is initially carried out with the formation of auxiliary code blocks I1 IN 1 for each coding operation, and then the transmission of coded information subblocks S1 'SN' for re-encoding. The coding order of information data blocks can be arbitrary, including depending on the encoding key or auxiliary code block, while, for example, the auxiliary code block can also specify the number of the next coding information data block. In the simplest case, the coding order of information data blocks alternates: first in increasing numbers of information data blocks, then in descending order.

 When the operation of block coding 1 is reversible, the decoded information data subunits are identical to the original ones. You can also notice that even when coding information blocks of data twice (if the block coding operation ensures that each bit of the output coded data sub-block depends on each bit of the input data block, each bit of the output coded digital information will depend on each bit of the input digital information, i.e., the input digital information will be encoded as a single data block, while the size of the encoded data block can change with discreteness into one block (practically Din bytes).

 With an even number of coding steps for each information segment, the order of the information sectors to be encoded should be reversed. With an odd number of steps, the order of information sectors during encoding and decoding is the same.

 With internal OS1, initially, multiple coding of one information data block Sj is performed, and then all auxiliary code blocks I1j I4j are installed to encode the subsequent information data block. In this case, it is possible to transfer auxiliary code blocks between different levels of coding of an information data block according to various laws, including those depending on the encoding key.

 When opening both OS circuits, each bit of encoded digital information will depend on each bit of the input information of the current and previous information data blocks, which requires the use of rather complex coding nodes.

 Alternatives of alternating the order of OS chains are also possible. In this case, digital information is divided into data blocks containing several data subunits. Digital information is encoded with internal OS2 inside these blocks and with internal OS1 between the blocks of the simplest encoding nodes. The maximum amount of encoded information is practically unlimited.

 In FIG. Figures 1 and 2 show detailed coding and decoding schemes with internal OS2. It can be seen that when using this coding unit, to ensure that each bit of digital output information depends on each bit of input digital information, four-time coding of each input data information block is necessary, but the lower bits of the data information block and the most significant bits are encoded exactly two times.

 The device operates as follows.

 In the first encoding operation, the input information data blocks through the multiplexer 1 are fed to the information input of the encoding node 2, which forms a coded information sub-block of data at the information output and an auxiliary code block at the additional output. The encoded information data sub-block and the auxiliary code block at the end of the encoding operation are recorded in the memory information block 3 and the register block 4. Further, depending on the adopted sequence of actions of the OS, the generated auxiliary code block is transferred to the additional input of the encoding node 2 and the next information data block is encoded coming from the device input to the encoding node 2 through multiplexer 1 (with internal OS2) or a once-encoded information data subunit is transmitted through the multiplexer 1 to the information input of the encoding node 2 and its re-encoding (with internal OS1).

 At the end of the operating cycle of the internal OS, information subblocks are transferred from the information block 3 memory, information subblocks through the multiplexer 1 to the information input of the encoding node 2 for re-encoding (with internal OS2) or the transfer of auxiliary code blocks from the information block 3 memory auxiliary code blocks to an additional input of encoding node 2 for encoding the next input segment (with internal OS1).

 The procedure for writing and reading information data sub-blocks and auxiliary code blocks can be established according to various laws, including those depending on the encoding key or auxiliary code block.

Claims (2)

 1. A method of encoding digital information, which consists in splitting digital information into one or more data blocks, each of which is divided into data blocks that are encoded in several stages, characterized in that at each stage of encoding the first data block from one of the input data blocks form an auxiliary code block, from other data subblocks and previously formed auxiliary code blocks, alternately form new auxiliary code blocks and subblocks coded at the first stage for data, at each stage of encoding subsequent data blocks from one of the input data subblocks and an auxiliary code block generated by encoding the previous data block, an encoded subblock and a new auxiliary code block are formed, from other subblocks and previously formed auxiliary code blocks, new auxiliary code blocks are alternately formed blocks and sub-blocks of data encoded in subsequent steps.  2. A device for encoding digital information containing a multiplexer, the first input of which is the information input of the device, and the output is connected to the information input of the encoding node, the first output of which is the information output of the device, characterized in that a register block and an information memory block are inserted into it, the output of which is connected to the second input of the multiplexer, while the first and second outputs of the encoding unit are connected to the inputs of the memory information block and the register block, respectively the outputs of which are connected to the additional input of the encoding node.

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