RU2039416C1 - Digital adaptive receiver of digital signals - Google Patents

Abstract

FIELD: electric communications. SUBSTANCE: device has automatic level control amplifier 2, adaptive corrector 8 and decoder 13. band-pass filter 1, five multipliers 4, 5, 15, 16, 30, oscillator 6, four low-pass filters 7, 8, 9, 10, six adders 11, 12, 22, 23, 29, 31, phase correctors control unit 13, commutation unit 14, converter 15 for signals with linear frequency modulation, synchronization signals detection unit 16, unscrambling unit 19, error calculation unit 24, comparison unit 25, delay line 26 having taps, address generation unit 27, integrator 28, delay gate 32. EFFECT: increased stability to noise when device operates with communication channels having great linear distortions and variations in level of received signal. 3 cl, 4 dwg

Description

 The invention relates to telecommunication technology and can be used to receive discrete signals transmitted over communication channels with a speed of up to 16.0 kbit / s

 According to the principle of operation, the proposed device is close to the receivers of digital modems. It is known "Device for receiving discrete signals" [1] containing a matching unit, a phase shifter, an analog-to-digital converter (ADC), a band corrector, a clock synchronization unit, a phase instability compensation unit, an amplitude instability compensation unit, a decision unit, an amplitude adjustment unit, a unit phase error calculations, stationary filter, adaptive filter, coefficient adjustment block, adder, non-linear converter and decoder.

 The disadvantage of this device is the low noise immunity when working on communication channels of deteriorating quality (with large linear distortions and impulse noise).

 Closest to the technical nature of the proposed device is a "Digital signal receiving device" [2] containing an error calculation unit, an amplifier with AGC, a phase shifter, an ADC, an adaptive corrector, a level control unit, a demodulation and phase compensation unit, a decision unit, a decoder.

 The disadvantage of the prototype is the low noise immunity when working on communication channels with large linear distortions (with large non-uniformity of the voltage of the communication channel) and significant fluctuations in the level of the received signal.

 The aim of the invention is to increase the noise immunity when working on communication channels with large linear distortions and significant fluctuations in the level of the received signal.

 In FIG. 1 shows a structural diagram of the proposed digital receiver; in FIG. 2 circuit block calculation; in FIG. 3 circuit block comparison; in FIG. 4 is a diagram of a first delay line and an address generating unit.

 The digital adaptive receiver contains a bandpass filter 1, an amplifier 2 with automatic level control (AGC), an analog-to-digital converter (ADC) 3, the first, second multipliers 4, 5, the generator 6, the first, second, third, fourth filters 7, 8, 9, 10 low frequencies, first, second adders 11, 12, phase corrector control unit 13, switching unit 14, signal converter with linear modulation frequency 15, clock extraction unit 16, adaptive corrector 17, decoder 18, descrambler 19, third, fourth multipliers 20, 21, third, fourth sum tori 22, 23, error calculation unit 24, comparison unit 25, first delay line 26 with taps, address generation unit 27, integrator 28, fifth adder 29, fifth multiplier 30, sixth adder 31, delay element 32.

 The error calculation unit 24 comprises a first multiplier 33, a drive 34, a second multiplier 35 subtracting a counter 36, a summing counter 37, and a delay element 38.

Block 25 comparison contains M delay elements 39 ¹ -39 ^M M adders 40 ¹ -40 ^M M comparators 41 ¹ -41 ^M and M-1 keys 42 ¹ -42 ^M-1 .

Delay line 26 consists of M delay elements 43 ¹ -43 ^M.

The address generating unit 27 contains M keys 44 ¹ -44 ^M , the delay element 39 forms a delay line 45.

 The device operates as follows.

 The analog signal coming from the communication channel is filtered by a band-pass filter 1, amplified by an amplifier with automatic level control 2, which maintains a constant signal level at the input of the analog-to-digital converter 3 when it changes in the communication channel. From the output of the analog-to-digital converter 3, the received signal is digitally supplied to the first inputs of the multipliers 4, 5, the second inputs of which are supplied from the corresponding outputs of the generator 6 with a reference voltage with a frequency coinciding with the frequency of the carrier oscillation. The multipliers 4, 5 together with the generator 6 form a spectrum converter, which transfers the received signal from the frequency band 0.3-3.4 kHz to the lower frequency region. The low-pass filter 7,8,9,10, included at the output of the multipliers 4,5, filter the detected signal. At the output of adder 11, the real component of the complex envelope of the detected signal X (nT) is extracted, and the imaginary component Y (nT) of the complex envelope of the signal is formed at the output of adder 12.

 In addition to the filtering functions of the low-pass filter, 7,8,9,10 together with the adders 11, 12 and the control unit of the phase correctors 13 form a compromise corrector for the unevenness of the GVZ of the communication channel. For this, in the control unit of the phase correctors 13, the values of the impulse characteristics (IH) of the low-pass filter 7.8,9,10 are recorded, corresponding to the averaged characteristics of the communication channel with a different number of re-receiving sections, from one to M.

(nT) и мнимой

(nT) составляющих поступает на вход декодера 18, в котором реализуется операция вынесения решения о принятом символе. Декодированный информационный сигнал в виде последовательности символов с выхода декодера 18 поступает на вход дескремблера 24, в котором он преобразуется в исходный вид и поступает на выход устройства.The real and imaginary components of the outputs of the adder 11, 12 are fed to the first and second inputs of the switching unit 14, which in the case under consideration switches them to the inputs of the block for selecting clock signals 16 and adaptive corrector 17, bypassing the signal converter with linear frequency modulation 15. The corrected signal in the form of estimates real

(nT) and imaginary

(nT) of the components goes to the input of the decoder 18, in which the operation of deciding on the received symbol is implemented. The decoded information signal in the form of a sequence of characters from the output of the decoder 18 is fed to the input of the descrambler 24, in which it is converted to its original form and fed to the output of the device.

 From the outputs of the adders 11, 12, the real and imaginary components of the received signal also arrive respectively at the first and second inputs of the multiplier 20 and at the first and second inputs of the multiplier 21.

The values of the signals X ² (nT) and Y ² (nT) from the outputs of the multipliers 20, 21 are fed to the first and second inputs of the adder 22, at the output of which the square of the envelope module of the received signal (Z) ² X ² (nT) + Y ² ( nT).

 In the presence of linear distortions in the communication channel (large non-uniformity of the GVZ), the envelope of the received signal loses its reading properties and changes in amplitude, and these changes depend on the value of the non-uniformity of the GVZ of the communication channel.

In the adder 23, the square of the envelope modulus of the received signal is compared with the reference value U _e1 equal to the square of the envelope of the signal in the absence of linear distortion in the channel.

The output of the adder 23 generates an error:
ε (nT) Z (nT) ² U _e1 , caused by the presence of linear distortions and additive noise in the communication channel. Error ε (nT), corresponding to a certain value of their LPF 7,8,9,10, is fed to the input of error calculation unit 24, in which the mean square error (RMS) is calculated over the averaging interval of N samples.

The squares of errors ε ² (nT) obtained at the output of the multiplier 33 of the error calculation unit 24 are accumulated in the accumulator 34. Simultaneously with the error samples, pulses with a sampling frequency t _d arrive at the input of the subtracting counter 36 with a capacity of N. When the subtracting counter 36 is reset, a pulse is generated at its output, according to which the sum of the squared errors from the drive 34 is fed to the first input of the second multiplier 35, the second input of which is supplied with a constant signal proportional to 1 / N-1.

e $\genfrac{}{}{0ex}{}{\text{2}}{\text{к}}$
Полученное значение СКО записывается в линию задержки с отводами 45 блока сравнения 25. Одновременно с этим в линию задержки с отводами 26 записывается состояние суммирующего счетчика 37, соответствующее адресу, по которому в блоке управления фазовыми корректорами 13 записано значение ИХ ФНЧ 7,8,9,10, соответствующее каналу связи с одним переприемным участком.Thus, at the moment of zeroing the subtracting counter 36 at the first output of the error calculation unit 24, the mean square error (RMS) value is calculated, calculated in accordance with the expression

e $\genfrac{}{}{0ex}{}{\text{2}}{\text{to}}$
The obtained RMS value is recorded in the delay line with taps 45 of the comparison unit 25. At the same time, the state of the totalizing counter 37 is recorded in the delay line with taps 26, which corresponds to the address at which the LPF 7.8.9 is recorded in the control unit for phase correctors 13, 10, corresponding to a communication channel with one receiver section.

 The pulse from the output of the subtracting counter 36 with the delay caused by the passage through the delay element 38 of the error calculation unit 24 is fed to the input of the phase corrector control unit 13. At this pulse, new values are entered from the phase corrector 13 control unit in the low-pass filter 7,8,9,10 THEM corresponding to a communication channel with two receiving stations. Further, the process of calculating the standard deviation occurs in accordance with the algorithm described above.

 The obtained MSE value is recorded in the delay line with taps 45, and the previously recorded MSE value is advanced along the delay line. Similarly, the state of the summing counter 37 is recorded in the first delay line with taps 26.

 At the output of the delay element 38 of the error calculation unit 24, an impulse appears, according to which from the control unit of the phase correctors 13 in the low-pass filter 7,8,9,10 new values of them correspond to the communication channel with three receiver sections.

-

=E₁, которая поступает на вход компаратора 41¹, который работает по следующему алгоритму: если Е₁ > 0, то на выходе компаратора 41¹формируется сигнал логической 1, если Е₁ < 0, то на выходе компаратора 41¹ формируется сигнал логического 0. При наличии на выходе компаратора 41¹ логической 1 ключ 42¹ замыкается в положение 2 и на его выходе появляется значение СКО

(меньшее из двух сравниваемых значений СКО).The process described above is cyclically repeated until all M RMS values corresponding to the tuning of the low-pass filter 7,8,9,10 for communication channels with a length from 1 to M receiving sections are calculated. At the end of this process, in the first delay line with taps 26, M addresses of their low pass filter will be recorded 7,8,9,10, and in the delay line with taps 45 the RMS values corresponding to these addresses will be recorded. When writing to the totalizing counter 37 of the number M, a transfer pulse is generated at its first output, which arrives at the second inputs of the adders 40 ¹ , 40 ^M of the comparison unit 25. Under the influence of this pulse, an error is calculated in the adder 10 ¹

-

= E ₁ , which is fed to the input of the comparator 41 ¹ , which works according to the following algorithm: if E ₁ > 0, then the output of the comparator 41 ¹ generates a logical 1 signal, if E ₁ <0, then a logic signal is generated at the output of the comparator 41 ¹ 0. If there is a logical 1 at the output of the comparator 41 ^{1, the} key 42 ¹ closes to position 2 and the RMS value appears at its output

(the smaller of the two compared RMSE values).

.If there is a logical zero at the output of the comparator 41 ^{1, the} key 42 ¹ closes to position 1, at which the MSE value passes to its output

.

при логическом 0 на выходе компаратора 41¹ ключ 44¹переключается в положение 1 и на его выходе появляется адрес, соответствующий значению СКО

.The signal from the output of the comparator 41 ¹ also goes to the third input of the key 44 ¹ of the address generation unit 27. If the output of the comparator 41 ¹ is equal to logical 1, then the key 44 ¹ switches to position 2 (see figure 4) and appears on its output address corresponding to the standard deviation

with a logical 0 at the output of the comparator 41 ^{1, the} key 44 ¹ switches to position 1 and an address corresponding to the RMS value appears at its output

.

На выходе ключа 42² появляется наименьшее из значений СКО, которое сравнивается со следующим значением СКО, записанным во второй линии задержки с отводами 45. Аналогичным образом на выходе ключа 44² блока формирования адреса 27 появляется адрес, соответствующий наименьшему из сравниваемых значений СКО. По окончании процесса сравнивания ошибок на выходе компаратора 41^М появляется сигнал (логическая 1 или логического 0), по которому на выходе ключа 44^Мпоявляется адрес, по которому в блоке управления фазовыми корректорами 13 записано значение ИХ ФНЧ 7,8,9,10, соответствующее наименьшей из сравниваемых величине СКО.The smallest of the two compared MSE values from the output of the key 42 ¹ is supplied to the first inputs of the adder 40 ² and the key 42 ² , in which this MSE value is compared with the MSE value in the same way as described above

At the output of key 42 ² , the smallest RMS value appears, which is compared with the next RMS value recorded in the second delay line with taps 45. Similarly, at the output of key 44 ² of the address generation unit 27, an address corresponding to the smallest compared RMS value appears. At the end of the error comparison process, a signal (logical 1 or logical 0) appears at the output of the comparator 41 ^M , at which the address appears at the output of the 44 ^M key, at which the value of the low-pass filter is recorded in the control unit for phase correctors 13, 7,8,9,10, corresponding to the smallest compared value of standard deviation.

 Thus, the adaptive adjustment procedure of the compromise corrector for the non-uniformity of the GWZ of the communication channel is performed, based on the low-pass filter 7,8,9,10. The combination of a compromise adaptive corrector and adaptive corrector, which is adaptively adjusted according to the minimum standard deviation criterion, makes it possible to compensate linear distortions in the communication channel with high accuracy, thereby reducing the amount of intersymbol distortions that have the main effect on the noise immunity of discrete signals at transmission rates above 4800 bit / s.

 The gain adjustment of the amplifier with automatic level 2 is as follows.

The square of the envelope module of the received signal from the output of the adder 22 is fed to the input of the integrator 28, averaging the values of the received signal to eliminate false adjustments of the gain of the amplifier with automatic level 2 when receiving AFM and KAM signals. The average value of the received signal in the adder 29 is compared with a reference voltage U _e2 equal to the nominal level of the received signal.

Z(t)

/dt
Данный алгоритм в заявляемом устройстве реализуется с помощью умножителя 30, сумматора 31 и элемента задержки 32.The algorithm for adjusting the gain of the amplifier with automatic level 2 control has the following form:
K _{n + 1} K _n + με _n where K _{n is} the gain at the nth moment of time;
μ- coefficient of adaptation;
ε _n U _pr U _et1 error in estimating the amplitude of the received signal;
U _ol

Z (t)

/ dt
This algorithm in the inventive device is implemented using a multiplier 30, an adder 31 and a delay element 32.

 The calculated value of the gain from the output of the adder 31 is transmitted in digital form to the second input of the amplifier with automatic level 2 control, thereby maintaining a constant level of the received signal at the input of the analog-to-digital converter 3.

Claims (3)

 1. A DIGITAL ADAPTIVE DISCRETE SIGNAL RECEIVER, comprising an amplifier with AGC, the output of which is connected to the input of an analog-to-digital converter (ADC), an adaptive corrector and a decoder, characterized in that a bandpass filter, a first, second, third and fourth multipliers, a generator, first, second, third and fourth low-pass filters, first, second, third, fourth, fifth, sixth adders, a phase corrector control unit, a switching unit, a signal converter with linear frequency modulation, a synchronization allocation unit Catch, descrambler, error calculation unit, comparison unit, delay line with taps, address generation unit, integrator and delay element, the input of the bandpass filter being the input of the device and the output connected to the first inputs of the first and second multipliers, the second inputs of which are connected to the corresponding generator outputs, the output of the first multiplier is connected to the first inputs of the first and second low-pass filters, the second inputs of which are connected to the input of the phase corrector control unit and the first inputs of the third and the fourth low-pass filter, the second inputs of which are connected to the output of the second multiplier, the output of the first low-pass filter is connected to the first input of the first adder, the second input of which is connected to the output of the third low-pass filter, is connected to the first input of the second adder, the second input of which is connected to the output fourth low-pass filter, the output of the first adder is connected to the first input of the switching unit, the first and second inputs of the third multiplier, the second input of the switching unit is connected to the output of the second sum at the first and second inputs of the fourth multiplier, the first output of the switching unit is connected to the first output of the linear frequency modulated signal converter, the first input of the clock allocation unit and the first input of the adaptive corrector, the second input of which is connected to the second input of the clock selection unit, the second output of the signal converter with linear frequency modulation and the second output of the switching unit, the third and fourth outputs of which are connected respectively to the first and second inputs For a signal with linear frequency modulation, the first and second outputs of the adaptive corrector are connected respectively to the first and second inputs of the decoder, the output of which is connected to the input of the descrambler, the output of which is the output of the device, the output of the sixth adder is connected to the second input of the amplifier with AGC and the input of the delay element, the output of which is connected to the first input of the second adder, the output of the third and fourth multipliers are connected to the inputs of the third adder, the output of which is connected to the first input of the fourth adder and the integrator, the output of the fourth adder, the second output of which is the first input of the reference voltage, is connected to the first input of the error calculation unit, the second input of which is the input of the sampling frequency, the first output of the error calculation unit is connected to the first input of the comparison unit, the second input of which is connected to the second the output of the error calculation unit, the third output of which is connected to the input of the delay line with taps, M outputs of which are connected to the first M inputs of the address generation unit, M of the second inputs of which connected to the M outputs of the comparison unit, the fourth output of the error calculation unit is connected to the output of the address generation unit and the input of the phase corrector control unit, the integrator output is connected to the first input of the fifth adder, the second input of which is the second input of the reference voltage, the output of the fifth adder is connected to the first input the fifth multiplier, the output of which is connected to the second input of the sixth adder, the second input of the fifth multiplier is the corresponding input of the device.  2. The digital adaptive receiver according to claim 1, characterized in that the error calculation unit contains a subtracting and summing counter, a delay element, a drive and two multipliers, the first and second inputs of the first multiplier are combined and are the first input of the error calculation unit, the second input of which is the input of the subtracting counter, the output of which is connected to the inputs of the totalizing counter, the delay element and the first input of the drive, the second input of which is connected to its output and the first input of the second multiplier, the second input of which is is the constant signal input, and the output is the first output of the error calculation unit, the third output of which is the first output of the summing counter, the second output of which is the second output of the second error calculation unit, the third output of which is the output of the delay element.  3. The digital adaptive receiver according to claim 1, characterized in that the comparison unit contains a delay line with taps, consisting of M series-connected delay elements, M adders, M comparators and M-1 keys, the first input of the comparison unit being the input of the delay line with taps combined with the first input of the first adder and the first input of the first key, the second input of which is connected to the second input of the first adder and the first tap of the delay line with taps, the third inputs of all M adders are connected to each other and form the second input of the comparison unit, the output of the first adder is connected to the input of the first comparator, the output of which is connected to the third input of the first key and is the first output of the comparison unit, the second output of which is the output of the second comparator connected to the third input of the second key, the first input of which is connected to the first the input of the second adder and the output of the first key, the second inputs of the second adder and the second key are connected to the second tap of the delay line with taps, the output of the second comparator is connected to the third input key, the output of the second adder is connected to the input of the second comparator, the output M-1 of the key is connected to the first input of the Mth adder, the second input of which is connected to the last tap of the delay line with taps, the output of the Mth adder is connected to the input of the Mth comparator whose output is the Mth output of the comparison unit.

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