RU2037966C1 - Two-wire duplex digital transmission system with time sharing - Google Patents

Abstract

FIELD: communications. SUBSTANCE: device has scrambling unit, transmission buffer memory unit, encoder, filter for high frequency of transmitted signal, transmitting amplifier, first, second, third and fourth switches, automatic gain control unit, variable corrector, correcting amplifier, filter for high frequency of received signal, decision making unit, decoder, buffer memory unit, unscrambling unit, driving oscillator, transmission frequency generation unit, receiving frequency generation unit, clock synchronization unit, packet synchronization unit, analysis unit, balance circuit, balancing transformer, low-pass filter. EFFECT: increased noise immunity, decreased transition interference between transmitting and receiving directions, decreased dispersion of phase error, increased precision of correction of errors between characters. 3 cl, 3 dwg

Description

 The invention relates to telecommunications and can be used to organize two-wire digital duplex subscriber lines while maintaining telephone communications in the tonal frequency range.

 The purpose of improving noise immunity.

 Figure 1 presents the structural electrical diagram of a two-wire duplex transmission system with time division; figure 2 is a structural diagram of a block clock synchronization; figure 3 is a structural diagram of an analysis unit.

 The two-wire time-division duplex digital transmission system comprises a scrambler 1, a transmission buffer memory unit 2, an encoder 3, a high-pass filter 4, a transmission amplifier 5, first and second keys 6.7, an automatic gain control unit 8, a variable corrector 9, a correction an amplifier 10, a high-pass filter 11, a decision block 12, a decoder 13, a reception buffer memory block 14, a descrambler 15, a master oscillator 16, a transmission frequency generating unit 17, a receiving frequency generating unit 18, a clock synchronization unit 19 tion, packet synchronization unit 20, analysis unit 21, the third and fourth keys 22,23, balanced circuit 24, a matching transformer 25, filter 26 is a lowpass.

 The clock synchronization unit 19 contains a character determiner 27, the first and second delay elements 28.29, a decoder 30, a multiplier 31, a three-stable key 32, a proportional-integrating filter 33, a voltage controlled oscillator 34, an integrator 35. The analysis unit 21 contains a character determiner 36 , the first, second, third and fourth delay elements 37-40, a decoder 41, a multiplier 42, a three-stable key 43, an integrator 44.

 Two-wire duplex digital transmission system with time division is as follows.

 The discrete information signal is fed to the input of the scrambler 1 of the first station. The scrambler serves to form a pseudo-random signal structure, which makes it possible for the adaptive nodes of the system to work stably.

Scrambler 1 is implemented as a self-synchronizing device with a generating polynomial, for example, 1 + x ^-3 + x ^-20 .

The signal from the output of the scrambler 1 is fed to the first input of block 2 of the transmission buffer memory, which serves to form transmission packets. The structure of the transmission packet contains 256 information bits and 4 bits for the packet synchronization signal. The incoming scrambled information in block 2 of the transmission buffer memory is recorded at an information rate of 64 kbit / s and is read at a linear speed of 144 kbit / s. Therefore, the time duration of the packet transmission cycle is T _c 4 ms, which corresponds to 576 clock (bit) time intervals.

The process of writing and reading is controlled by signals arriving at the second input of transmission buffer unit 2 from the first output of transmission frequency generating unit 17. In turn, the frequency grid required to control the operation of the system nodes is formed by the transmission frequency generation unit 17 from the fundamental frequency of the master oscillator 16 f _sg 3456 kHz.

 From the output of block 2 of the transmission buffer memory, the signal is fed to the input of the encoder 3, which converts the scrambled information signal into a linear code according to the law of a bi-pulse relative signal. The relative bi-pulse code is selected as linear based on compatibility considerations for the digital transmission channel and the telephone channel.

 The signal from the output of the encoder 3 is fed to the input of the high-pass filter 4, which serves to suppress the low-frequency components of the bi-pulse signal spectrum in order to eliminate the influence of the digital channel on the telephone channel.

From the output of the high-pass filter 4, the signal through the transmission amplifier 5, which sets the required signal amplitude at the line input (from 1 to 3 V), is fed to the first input of the first key 6. The keys 6 and 7 are used to temporarily separate the transmission and reception directions. The operation of the keys is controlled by signals arriving at their second inputs from the outputs of the transmission frequency generating unit 17. During the transmission time interval t ₁ .t _4, key 6 is open, and the remaining keys are closed. The signal from the output of the key 6, passing through the matching transformer 25, is fed to the input of a two-wire line. At the end of the packet transmission at time t _4, key 6 is closed, and keys 22 and 23 are opened and remain open for six clock time intervals until time t ₆ . The keys 22 and 23 together with the balanced circuit 24 serve to eliminate the influence of the transmission packet on the received signal by reducing the power of the reflected signal, which occurs due to incomplete matching of the input impedances of the equipment with the cable line. The balance circuit 24 is a serial RC circuit.

At time t ₆ , when the keys 22 and 23 are closed, the key 7 is opened and remains open until the end of the cycle, i.e. until the next opening of the key 6. The open state of the key 7 means that the first station is ready to receive a packet transmitted from the second (opposite) station.

m_n+i

(t-jT+τ)g^ном(t-(i+j)T+τ)+ζ(t), (1)
где m_n 1; + 1} передаваемые информационные символы; кодирование по закону относительного биимпульсного кода; g^ном(t) номинальная составляющая импульсного отклика линейного тракта;

(t) переменная составляющая импульсного отклика линейного тракта; L_n длительность межсимвольной интерференции; ζ (t) флуктуационный гауссовский шум; τ неизвестная задержка сигнала.The received signal, which passed a two-wire line and distorted due to the uneven frequency characteristics of the cable, is fed through a matching transformer 25 to the input of the key 7 of the second (opposite) station. Through the public key 7, the signal is fed to the input of the automatic gain control unit 8, where partial compensation of the flat attenuation of the two-wire line is made. Next, the amplified signal is fed to the first input of the variable corrector 9, which, together with the correction amplifier 10, serves to form the required signal spectrum at the input of the decision block 12 and the required (for example, Gaussian) digital path response. With this in mind, the analytical signal at the output of the correction amplifier in the time interval t from nT to (n + 1) T can be represented as an additive mixture of the useful signal and Gaussian interference
x (t)

m _{n + i}

(t-jT + τ) g ^nom (t- (i + j) T + τ) + ζ (t), (1)
where m _n 1; + 1} transmitted information symbols; coding according to the law of a relative bi-pulse code; g ^nom (t) is the nominal component of the impulse response of the linear path;

(t) a variable component of the impulse response of the linear path; L _{n the} duration of intersymbol interference; ζ (t) fluctuation Gaussian noise; τ unknown signal delay.

(t) импульсного отклика, кроме основного. С этой целью производится подстройка частотной характеристики переменного корректора 9 при отклонениях характеристик кабельной линии от номинальных значений. Это достигается путем подачи на второй вход переменного корректора 9 управляющего сигнала с выхода блока 21 анализа.Therefore, the variable corrector 9 serves to suppress all samples of the variable component

(t) impulse response other than the primary. For this purpose, the frequency response of the variable corrector 9 is adjusted when the cable line characteristics deviate from the nominal values. This is achieved by applying to the second input of the variable corrector 9 a control signal from the output of the analysis unit 21.

The correction amplifier 10 is tuned to the nominal length of the cable line and serves to form the nominal component g ^nom (t) of the impulse response of the path, for example, a Gaussian shape. From the output of the correction amplifier 10, the corrected signal is fed to the input of the high-pass filter 11, designed to suppress low-frequency interference (up to 4.3 kHz) in order to eliminate the influence of the telephone channel on the digital transmission channel.

The signal x (t) from the output of the high-pass filter 11 is supplied simultaneously to the second inputs of the clock synchronization block 19 and the analysis block 21, as well as to the input of the decision block 12, where the received symbols m are estimated $\genfrac{}{}{0ex}{}{\text{*}}{\text{n}}$ 1; + 1} Next, the signal through the decoder 13 is fed to the first input of the reception buffer block 14. On the other hand, the signal from the output of decision block 12 is fed to the first inputs of clock synchronization block 19, packet synchronization block 20, and analysis block 21. The analysis unit 21 generates a control signal, which is supplied to the second input of the variable corrector 9.

 In block 19 of the clock synchronization, the unknown delay τ of the signal is monitored and the reference (clock) decision decision times are set. The signal with a clock frequency from the output of the clock synchronization block 19 is fed to the second inputs of the packet synchronization block 20 and the reception frequency generating block 18. In the packet synchronization block, the sync group in the receive packet is recognized. If a sync group is detected, the corresponding command is received from the output of the packet synchronization block 20 to the first input of the reception frequency generating block 18. According to this command, the block 18 forming the reception frequencies through the first output sends a signal to the second input of the block 14 of the reception buffer memory, which allows recording into the main memory the information that is received at the first input of this block. Recording is performed at a linear speed of 144 kbit / s, and is read to the output of block 14 of the buffer memory with an information speed of 64 kbit / s. For each write enable command, only 256 bits of information are recorded in the operative memory of the reception buffer block 14, after which the buffer memory block 14 goes into standby mode until the next synchronization block 20 is detected by the packet synchronization block.

 From the output of block 14 of the buffer memory, the data stream through the descrambler 15, which performs the opposite function of scrambling, is fed to the information output of the second station.

 The transmission of information packets in the opposite direction from the second station to the first station is similar. However, at the second station, the start of the transmission of the packet is determined by the command from the second output of the receiving frequency generating unit 18 to the second input of the transmit frequency generating unit 17. This command is issued at 28 clock intervals, i.e. 0.2 ms after the end of recording, 256 bits of information are received in block 14 of the reception buffer memory of the second station. This 0.2 ms time is required to provide a sufficient guard interval between the transmission and reception packets of the first station.

 Thus, there is an exchange of information packets between stations with a linear speed of 144 kbit / s.

-

(3)
В соответствии с указанным алгоритмом оценки на первый вход первого блока 19 тактовой синхронизации поступают сигналы с выхода блока 12 принятия решения, а на второй вход сигнал x(t) с выхода фильтра верхних частот приема 11.The clock synchronization unit 19 serves to track the unknown delay τ of the signal x (t) in order to form a train of pulses with a clock frequency. Estimation of the signal delay is performed according to the sign algorithm at the reference nT time instants
Δ ₁ τ _n ^* K _os Sign (x _{n + 1/2} ). D [m _n ^* , m _{n + 1} ^* ] (2) where T is the clock time interval;
Δ ₁ operator of the first difference;
To _{os the} coefficient in the feedback circuit;
Sign (˙) function sign (˙);
D (˙) is a key function that takes one of three values (0,1, 1), and
D (

-

(3)
In accordance with the specified evaluation algorithm, the first input of the first clock synchronization block 19 receives signals from the output of the decision block 12, and the second input receives the signal x (t) from the output of the high-pass filter 11.

The first input of the decoder 30 receives a signal m _{n + 1} ^* directly from the first input clock unit 19, and the second input signal m _n ^* output from the second delay element which performs delay of one clock cycle T. The decoder 30 determines the sequence of input signals, satisfying conditions (3). The signal (0.1 or 1) from the output of the decoder 30 is fed to the second input of the multiplier 31.

n +

T Стробирующие сигналы поступают на второй вход первого блока 27 определения знака с выхода генератора 34, управляемого напряжением, через инвертор 35.In the determinant 27 of the sign, the sign of the signal x (t) entering the first input is determined at the gating times

n +

T Gating signals are fed to the second input of the first sign determining unit 27 from the output of the voltage-controlled generator 34 through the inverter 35.

 The signal from the output of the character determiner 27 through the first delay element 28, by means of which a delay of 0.5T is carried out, is fed to the first input of the multiplier 31. The output signal of the multiplier 31 controls the first three-stable key 32, switching high and low potentials depending on the sign input signal.

 The signal from the output of the first three-stable key 32 is fed to the input of a proportional-integrating filter 33, which generates a control signal to the generator 34. Thus, the frequency and phase of the output pulse sequence are adjusted in the clock synchronization block 19.

 Block 21 analysis is used to generate a control signal by a variable corrector 9.

 The formation of the control signal of the evaluation signal of the unknown variable component g ≈ (t) of the pulse response of the digital path is carried out according to the following algorithm (see the TEO).

-

; (5)
В соответствии с алгоритмом (4) оценки g ≈* (t) на первый вход блока 21 анализа поступают сигналы m_n ^* с выхода блока 12 принятия решения, а на второй вход сигнал x(t) с выхода фильтра 11 верхних частот приема.Δ ₁ g _{o, n} ^{≈ *} K _os Sign (x _{n + 3/2} ) ˙D [m _n ^* , m _{n + 1} ^* , m _{n + 2} ^* , m _{n +3} ^* ]
(4) where D (˙) is a key function defined as
D (

-

; (5)
In accordance with the estimation algorithm (4), g ≈ * (t), the signals m _n ^* are received at the first input of the analysis block 21 from the output of the decision block 12, and the signal x (t) from the output of the high-pass filter 11 is received at the second input.

At the first input of the decoder 41, the signal m _{n + 3} ^* is received directly from the first input of the analysis unit 21, and the signals m _{n + 2} ^* , m _{n + 1} ^* , m _n ^* from the outputs are supplied sequentially to the second, third, and fourth inputs of the decoder 41 connected by the second 38, third 39, fourth 40 delay elements, each of which produces a delay of one clock cycle T. The decoder 41 determines a combination of input signals that satisfy the conditions (5). The signal from the output of the second decoder (0, 1 or 1) is fed to the second input of the multiplier 42.

)Т. Сигнал с выхода определителя 36 знака через первый элемент задержки 37, где производится задержка на интервал (-

T

T), поступает на первый вход перемножителя 42. Выходной сигнал перемножителя 42 осуществляет управление вторым трехстабильным ключом 43, коммутирующим высокий и низкий потенциал в зависимости от знака входного сигнала. Сигнал с выхода ключа 43 поступает на вход интегратора 44, где производится выделение постоянной составляющей сигнала управления, воздействующий на регулируемый элемент переменного корректора 9.The sign determinant 36 determines the sign of the signal x (t) at time instants t (n +

) T. The signal from the output of the determinant 36 signs through the first delay element 37, where a delay is made for the interval (-

T

T), is supplied to the first input of the multiplier 42. The output of the multiplier 42 controls the second tri-stable switch 43, switching the high and low potential depending on the sign of the input signal. The signal from the output of the key 43 is fed to the input of the integrator 44, where the DC component of the control signal is extracted, acting on the adjustable element of the variable corrector 9.

 A duplex digital channel is organized in the supratonal frequency region. In this case, the low-frequency telephone channel is stored in the region up to 3.4 kHz. The telephone channel is allocated using a low-pass filter 26, which serves to eliminate the mutual influence of telephone and digital channels.

Claims (3)

 1. A TWO-WIRED DUPLEX DIGITAL TRANSMISSION SYSTEM WITH TEMPORARY SEPARATION, containing transmit buffer memory blocks, a receive buffer memory block, four keys, characterized in that, in order to increase noise immunity, a scrambler, a descrambler, a block for generating transmission frequencies, a block for generating reception frequencies are introduced, master oscillator, packet synchronization block, clock synchronization block, encoder connected in series, high-pass filter of transmission and transmission amplifier, as well as analysis unit, balanced circuit, filter frequencies, matching circuit, matching transformer and series-connected automatic gain control unit, variable corrector, correction amplifier, high-pass filter, decision block and decoder, the output of which and the first output of the receiving frequency generating unit are connected to the first and second inputs of the block the buffer memory of the reception, the output of which is connected to the input of the descrambler, the output of which is the information output of the system, while the output of the master oscillator and the second the stroke of the reception frequency generation unit is connected respectively to the first and second inputs of the transmission frequency generation unit, the first output of which is connected to the second input of the transmission buffer memory block, the scrambler output is connected to its first input, the input of which is the information input of the system, and the output of the transmission buffer memory block connected to the input of the encoder, and the output of the transmission amplifier and the second output of the transmission frequency generation unit are connected respectively to the first and second inputs of the first key, the output to The second output of the primary winding of the matching transformer is connected to the input of the balanced circuit, the output of which, as well as the outputs of the third and the fourth key is connected to a common bus, while the third output of the transmission frequency generating unit is connected to the second input of the second key, the output of which is connected to the output of the automatic adjustment, and the fourth output of the transmission frequency generating unit is connected to the second inputs of the third and fourth keys, and the output of the decision unit is connected to the first inputs of the clock synchronization unit, the packet synchronization unit and the analysis unit, the output of which is connected to the second input of the variable corrector, and the outputs the high-pass filter of the reception is connected to the second inputs of the analysis unit and the clock synchronization unit, the output of which is connected to the second inputs of the reception frequency generation unit and the packet si chronicity, the output of which is connected to the first input unit generating a reception frequency, wherein the terminals of the secondary winding of the matching transformer are inputs of a two-wire line and are connected to the inputs of lowpass filter whose outputs are the inputs of the telephone channel.  2. The system according to claim 1, characterized in that the clock synchronization unit contains a sign determinant, first and second delay elements, a decoder, an integrator and a series-connected multiplier, a three-stable key, a proportionally-integrated filter and a voltage-controlled generator, the output of which is the output a clock synchronization unit, the first and second inputs of which are, respectively, the first input of the sign determinant and the input of the second delay element connected to the first input of the decoder to the second input to torogo connected to the output of the second delay element, wherein the generator output voltage controlled by the inverter is connected to a second input the sign of the determinant, the output of which through the first delay element connected to the first input of the multiplier, to the second input of which is connected to the output of the decoder.  3. The system according to claim 1, characterized in that the analysis unit contains a sign identifier, the input of which is the second input of the analysis unit, and the sign identifier output is connected to the first input of the multiplier through the first delay element, the output of which is connected to the integrator input through a three-stable key, the output of which is the output of the analysis unit, as well as the decoder and the second, third and fourth delay elements connected in series, the input of the second delay element being the first input of the analysis unit and connected to the first the input of the decoder, to the second, third and fourth inputs of which the outputs of the second, third and fourth delay elements are connected, and the output of the decoder is connected to the second input of the multiplier.

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