RU2034327C1 - Device for sorting data - Google Patents

Abstract

FIELD: automation and computer engineering. SUBSTANCE: device has input and output channels, two memory unit with stack architecture, comparison unit, memory unit, control unit, control unit of memory unit, counter, register, comparison unit, stacks, commutator, code generator, address bus generator. Device provides on-line sorting of data while they arrive. Sorted array is output in either ascending or descending order. New feature of the described device is separation of data into standard length constituents (characters). Process of data sorting runs along with information input. This results in possibility to simplify hardware, in particular decreased number of memory circuits for processing variable length data, as well as in possibility to decrease time of data sorting when slow external device is used. EFFECT: simplified design, increased efficiency. 9 dwg

Description

 The invention relates to technical means of automation and computer technology and can be used in information processing devices, in particular, for compiling dictionaries, reference books, creating without data.

 Known devices for sorting numbers [1,2] allow you to sort an array of numbers in ascending and descending order.

 As a prototype of the selected device information sorting [3] allows you to organize data arrays.

 A disadvantage of the known device is the limited functionality of a constant data length, or hardware redundancy in the processing of data of variable length.

 The goal is to expand the functionality and reduce the hardware redundancy of the device.

 The invention allows to organize character-by-character work with data, which minimizes costs, for example, on memory circuits when working with data of variable length.

 The solution to the problem is achieved by the fact that in the information sorting device containing two stacked memory blocks, a comparison element, a control unit, input and output channels, a random access memory unit, a switching and identification unit are introduced, the first to fifth control outputs of the control unit being connected respectively to the first to fifth control inputs of the random access memory unit, the information input of which is connected to the input channel, the control output is connected to the fourth control input of the control unit, information the output is connected to the first information input of the comparison element and the second information input of the switching and identification unit, the control output of the latter is connected to the fourteenth control input of the control unit, the first to third control inputs are connected respectively from the tenth to twelfth control outputs of the latter, the second information output is connected to the output channel, the first information output is connected to the information input of the second stack memory block, the first and second control inputs are it is connected respectively to the sixth and seventh control outputs of the control unit, the first and second control outputs are connected to the tenth and eleventh control inputs of the latter, the information output is connected to the information input of the first stack memory block, the first and second control inputs of which are connected respectively to the eighth and the ninth control outputs of the control unit, the first and second control outputs are connected to the twelfth and thirteenth control inputs respectively one, the information output is connected to the first information input of the switching and identification unit and to the second information input of the comparison element, the first to third control outputs of the latter are connected respectively to the control inputs from the fifth to the seventh, control unit, from the first to third control inputs of the control unit ZAGR "," ChTPR "," WHAT ", as well as the eighth and ninth control inputs" RESET "and" START "of the latter are external inputs of the device, the thirteenth and fourteenth control outputs of the" GT "and" BLUE "block The controls are the external outputs of the device.

 The input channel (VHK) is used to receive data, a block of random access memory (BOP) for temporary storage of the received word (number).

 The comparison element (ES) compares the characters of the received word (number) and already ordered words (numbers).

 Stacked memory blocks 1 and 2 (SBP1 and SBP2) are used to store part of the sorted array and organize sorting.

 The switching and identification unit (БКиИ) serves for switching information from various sources to the information input of the SBP2 block, switching the information output of the SBP1 block to the output channel, and also for determining the layer boundaries of the ordered array.

 The output channel (OUT) is used to output data.

 The control unit (CU) controls the other units of the device.

The theory of normal algorithms is universal with respect to any algorithmic schemes. Known algorithms that allow you to arrange words from an array, for example, on the basis of alphabetical order. Universal devices for implementing substitution formulas in the form of Markov algorithms are known (1). By the Markov algorithm we mean a finite sequence of formulas of the form: S - >> T, where S is a sample, T is a permutation, S and T are arbitrary words in a fixed alphabet. The formula works by detecting a fragment in the word that matches the sample and replacing the detected fragment with a substitution word. Therefore, when the word being processed is represented as:
P R ₁ SR ₂ , where the graphic equal sign; R ₁ , R ₂ any words in a fixed alphabet, the result of the formula is: PR ₁ TR ₂ .

 Detection of a fragment that matches the pattern is carried out from left to right by the word being processed.

 Ordering (sorting) of words in the theory of normal algorithms occupies a special place, since it relates to difficult tasks in which formulas (products) are used that contain patterns with operations specified in their structure. In this case, we are talking about the operation of comparing "more", "less" and "equal". The substitution in the formulas "S - >> T" also has its own specifics and does not semantically coincide with the word being processed, but is an auxiliary service word indicating the position of the word among other words in a given ordering rule.

The work of the proposed device for sorting information is based on a modified algorithm that contains a sample and a substitution with the above features. The information sorting device implements formulas of the following form:
S ₁ ⊗ S ₂ - >> T ₁ / T ₂ (1) where S ₁ and S ₂ are the sample comparads; ⊗ - a symbol denoting the operation of comparing by "more", "less" and "equal", as well as a comparison of the length of the comparads; T _{1 is} a position indicator in a partially ordered array of one of the comparands depending on the result of the comparison or comparison of the word lengths; T _{2 is the} pointer to the next (current) command or rule for constructing a sample based on the results of word comparison; /, delimiters in the form of service characters not included in the main alphabet.

In the proposed device, the meaning of the substitution fragment T ₂ is to receive the next character from the input channel.

 A formula of the form (1) defines a recursive implementation of the ordering process.

 Figure 1 shows a structural diagram of a device for sorting information; figure 2 circuit block RAM; figure 3 diagram of the comparison element; figure 4 diagram of SBP2; figure 5 diagram of SBP1; 6 is a diagram of a switching and identification unit; Figures 7 and 8 informative GAW work of the control unit; figure 9 marked GAW operation of the control unit.

 The information sorting device (Fig. 1) contains an input channel 1, a RAM block 2, a comparison element 3, a memory stack block 4 (SBP2), a memory stack block 5 (SBP1), a switching and identification unit 6, an output channel 7, block 8 management.

To describe the operation algorithm of control unit 8, the following identifiers are used:
1. ZAGR recording signal to the device.

 2. ChTPR signal issuing device ordered array in ascending order.

 3. So that the device gives out an ordered array in descending order.

 4. OBSH zeroing signal received at the input of the counter of the BOP unit.

 5. INSC signal incrementing the contents of the counter block BOP.

 6. ZPRG signal write to the register RG block BOP information from the counter midrange block BOP.

 7. ZPOZU signal write / not read RAM unit BOP.

 8. VK1 signal selection chip RAM RAM unit BOP (inverse).

 9. COP sign of the end of the word located in the BOP unit.

 10. MORE sign that the I2 symbol is larger than the I3 symbol.

 11. Equal sign that the symbol I2 is equal to the symbol I3.

 12. LESS sign that the I2 symbol is less than the I3 symbol.

 13. RESET device reset signal.

 14. START device start signal.

 15. ZPS2 signal write to the stack block SBP2.

 16. ЧТС2 read signal from the stack of SBP2 block.

 17. C2PN is an indication that the stack of the SBP2 block is full.

 18. C2PT indicates that the stack of the SBP2 block is empty.

 19. ZPS1 signal write to the stack of the block SBP1.

 20. ЧТС1 read signal from the stack of SBP1 block.

 21. C1PN is an indication that the stack of the SBP1 block is full.

 22. C1PT indicates that the stack of SBP1 is empty.

 23. HS sign of the boundary between the words of an ordered array.

 24. A1 address 1, supplied to the input of the switch KM block BCI.

 25. A2 address 2 supplied to the input of the switch KM block BCI.

 26. RV signal permission to issue information to the output channel.

 27. GT signal of readiness of the device.

 28. BLU external synchronization output signal.

 29. I1 input RAM of the BOP unit.

 30. And2 the output of the RAM unit BOP.

 31. I3 the output of the stack block SBP1.

 32. And4 the output of the stack block SBP2.

 33. I5 the output of the switch KM block BCI.

 34. I6 output data of the bus driver ShF block БКиИ.

 The operation of the device control algorithm.

 Content GAW control is shown in Fig.7 and reflects the operation of the control unit (Fig.1).

 The signal "RESET" (block 2 of the flowchart of the algorithm) resets the information stored in the stacks of the blocks SBP1 and SBP2, by the commands "CTS2: 1" and "CTS1: 1" (block 4 GAU) until the stacks will become empty and the signs "S1PT = 1" and "C2PT = 1" (block 3 GAW) will not be established (Fig.7).

 The signal "START" (block 5 GAW) is the transition to block 6 GAW, otherwise to block 5 GAW.

 The signal “WHAT” (block 6 GAW) is the transition to block 63 of the algorithm. The signal "ChTPR" (block 7 GAW) is the transition to block 58 GAW.

 The signal "ZAGR" (block 8 GAW) is loading the input word in the BOP (figure 1), otherwise the transition to block 6 GAW.

 In block 9 of the GAW, the command "OSCH: 1" resets the counter (MF) of the BOP unit (Fig. 2). Until the signal "ZAGR" is removed (block 10 GAU), by the command "RAM: 1", the input symbol is written into RAM at the address stored in the MF counter (Fig. 2) and at the same time, the output of the external synchronizing signal " SIN: 1 "(block 11 GAW) (figure 1). In block 12 GAW by the command "INSC: 1" the content of the midrange counter is increased by one (figure 2), the transition to block 10 GAW.

 In block 13 of the GAW, by the command "ZPRG: 1", the state of the MF counter is recorded in the register RG (figure 2), in this case equal to the number of characters in the received word.

 In block 14 GAW analyzes the sign of the emptyness of the stack block SBP1 (figure 5) "C1PT = 1". On this basis, the transition to block 16 of the algorithm.

 In block 15 of the GAW, the MSC counter is reset to zero using the “OCCH: 1” command (Fig. 2), the character is recorded from the “ЧТС1: 1”, “A1: 1”, “A2: 1” and “ЗПС2: 1” commands block SBP1 to block SBP2, while the signals "A1" and "A2" supplied to the address inputs of the switch (KM) connect its output to input I3 (Fig. 6). The transition to block 19 GAW.

 In block 16 GAW analyzes the sign of the emptiness of the side stack SBP2 (figure 4) "C2PT = 1". On this basis, the transition to the block 40 GAW, otherwise the word is recorded from SBP2 in SBP1 (figure 1).

 In block 17 GAW analyzes the sign of the boundary between words in the stacked blocks of memory (figure 1) "HS = 1", identified by a special service code. On this basis, the transition to block 15 GAW.

 In block 18 of the GAW by the commands "CTS2: 1" and "ZPS1: 1", the next character is recorded from the stack of the SBP2 block to the stack of the SBP1 block (Fig. 4.5). The transition to block 17 GAW.

 In block 19 of the GAW, the sign that I2 is less than I3 “LESS = 1”, issued by the comparison element (FIG. 1), is analyzed. On this basis, the transition to block 20 GAW, otherwise to block 35 GAW.

 In the block 20 GAW analyzes the sign of the boundary between the words in the stacks (Fig 4,5) "HS = 1". On this basis, the transition to block 22 GAW.

 In block 21 of the GAW, the commands “ЧТС2: 1” and “ЗПС1: 1” record the character from SBP2 to SBP1 (Fig. 1). The transition to block 20 GAW.

 In block 22 GAW analyzes the sign of the emptiness of the stack block SBP2 (figure 4) "C2PT = 1". On this basis, the transition to the block 40 GAW.

 In block 23 of the GAW, the commands “CTS2: 1” and “ZPS1: 1” record the character from SBP2 to SBP1 (Fig. 1).

 In block 24 GAW analyzes the sign of the word boundary in the stacks of blocks SBP2 and SBP1 (Fig. 4,5) "GS = 1". On this basis, the transition to block 25 GAW, otherwise to block 23 of the algorithm.

 In block 25 of the GAW, the command “obsch: 1” resets the counter of the midrange of the BOP unit (Fig. 2), the commands “ЧТС1: 1”, “ЗПС2: 1”, “A1: 1”, “А2: 1” record character from SBP1 to SBP2 (figure 1).

 In block 26 of the GAW, the sign that I2 is less than I3 "LESS = 1" is analyzed, according to which the transition to block 20 of the GAW is performed.

 In the block 27 GAW analyzes the sign that I2 is equal to I3 "EQUAL = 1", by which the transition to block 31 GAW.

 In block 28 of the GAW, a sign is analyzed that I2 is greater than I3 “MORE = 1”, issued by the ES comparison element (FIG. 1). On this basis, the transition to block 29 GAW, otherwise to block 26 GAW, and signs are checked again.

 In the block 29 GAW analyzes the sign of the word boundary in the stacks (Fig. 4,5) "GS = 1", which is the transition to block 40 GAW.

 In the block 30 GAU for the commands "CTS1: 1", "A1: 1", "A2: 1", "ZPS2: 1" is the entry in SBP2 character from block SBP1 (figure 1). The transition to block 29 GAW.

 In block 31 GAW by the command "INSC: 1" the content of the midrange counter is increased by one (figure 2). By the commands "ЧТС1: 1", "A1: 1", "A2: 1", "ЗПС2: 1", the character from SBP1 is recorded in SBP2 (Fig. 1).

 In block 32 GAW analyzes the sign of the word boundary in the stacks (Fig. 4,5) "HS = 1" or the empty space of the stack block SBP2 "C2PT" (Fig.4). On this basis, the transition to block 34 GAW.

 In the block 33 GAW analyzes the sign of the end of the word stored in the BOP "KS = 1" (Fig. 1), issued with the equality of the states of the MF counter and the register RG of the BOP block (Fig.2). On this basis, the transition to block 20 GAW, otherwise to block 26 GAW.

 In the block 34 GAW analyzes the sign of the end of the word in the BOP "KS = 1" (figure 1). On this basis, the transition to block 40 GAW, otherwise to block 29 GAW.

 In block 35 GAW analyzes the sign that I2 is equal to I3 "EQUAL = 1" (figure 1). If "EQUAL = 0", the transition to block 44 GAW.

 In block 36 GAW by the command "INSC: 1" the content of the midrange counter is increased by one (figure 2). By the commands "ЧТС1: 1", "A1: 1", "A2: 1", "ЗПС2: 1", the character from SBP1 is recorded in SBP2 (Fig. 1).

 In block 37 GAW analyzes the sign of the word boundary in the stacks or the empty space of the stack block SBP2, respectively, "GS = 1" and "C2PT = 1" (Fig.5.5). On this basis, the transition to block 39 GAW.

 In block 38 GAW analyzes the sign of the end of the word in the BOP "KS = 1" (figure 1). On this basis, the transition to block 20 GAW, otherwise to block 19 GAW.

 In block 39 GAW analyzes the sign of the end of the word in the BOP "KS = 1" (figure 1). On this basis, the transition to block 40 GAW, otherwise to block 45 GAW.

 In the block 40 GAW by the command "OSCH: 1" the MF counter is cleared (Fig. 2), by the commands "ZPS2: 1" and "A2: 1" the service code of the boundary between the words is written to the stack of the SBP2 block (Fig. 4), and the signal "A2", arriving at the address input of the switch (CM) of the BCI unit, the output of the FC code generator generating the service code is switched to the output of the switch CM (Fig.6).

 In block 41 GAW analyzes the sign of the end of the word in the BOP "KS = 1" (figure 1). On the basis of the transition to block 71 GAW.

 In block 42 of the GAU, the commands “ZPS2: 1” and “A1: 1” record the character from RAM with the address stored in the MF counter (FIG. 2), in SBP2 (FIG. 1), at the same time, to the address input of the KM switch block BCI receives the signal "A1" and commutes the input And2 to the output of the CM (Fig.6).

 In block 43 GAW by the command "INSC: 1" there is an increase by one unit of the contents of the midrange counter (figure 2). The transition to block 41 GAW.

 In block 44 of the GAW, a sign is analyzed that I2 is greater than I3 "MORE = 1" (Fig. 1). If "MORE = 0", the transition to block 19 GAW.

 In the block 45 GAW analyzes the sign of the word boundary "HS = 1" in the stacks or the empty space of the stack block SBP2 "C2PT = 1" (Fig. 4,5). On this basis, the transition to block 47 GAW.

 In block 46 GAU for the commands "CTS1: 1", "ZPS2: 1", "A1: 1", "A2: 1" is a record in SBP2 character from SBP1 (figure 1). The transition to block 45 GAW.

 In block 47 of the algorithm, the sign of emptiness SBP1 "C1PT = 1" is analyzed (Fig. 1). On the basis of the transition to block 40 GAW.

 In block 48 of the GAW, the command “OSCH: 1” resets the MF counter (Fig. 2), and the commands “ЧТС1: 1”, “ЗПС2: 1”, “А1: 1”, “А2: 1” record in SBP2 character from SBP1 (figure 1).

 In block 49 of the GAW, a sign is analyzed that I2 is less than I3 “LESS = 1” (FIG. 1). On the basis of the transition to block 56 GAW.

 In block 50 GAW analyzes the sign that I2 is equal to I3 "EQUAL = 1" (figure 1). On the basis of the transition to block 52 GAW.

 In block 51 of the GAW, a sign is analyzed that I2 is greater than I3 "MORE = 1" (Fig. 1). On the basis of the transition to block 45 GAW, otherwise to block 49 GAW.

 In block 52 of the GAW, by the command “INSCH: 1”, the content of the midrange counter is increased by one (Fig. 2), by the commands “CTS1: 1”, “ZPS2: 1”, “A1: 1”, “A2: 1”, the recording the symbol in SBP2 from SBP1 (Fig. 1).

 In block 53 GAW analyzes the sign of the word boundary "HS = 1" in the stacks or the empty space of the stack block SBP2 "C2PT = 1" (Fig.5.5). If the sign is equal to zero, the transition to block 55 GAW.

 In block 54 GAW analyzes the sign of the end of the word in the BOP "KS = 1" (figure 1). On this basis, the transition to block 40 GAW, otherwise to block 45 GAW.

 In the block 55 GAW analyzes the sign of the end of the word in the BOP "KS = 1". If "KS = 0", the transition to block 49 GAW.

 In block 56 GAW analyzes the sign of the boundary between the words in the stacks "HS = 1" (Fig 4,5). On the basis of the transition to the block 40 of the algorithm.

 In block 57 of the GAW, the symbol “SBT2: 1” and “ZPS1: 1” rewrites the symbol from SBP2 to SBP1 (Fig. 1). The transition to block 56 GAW.

 In block 58 of the GAW, the sign of emptiness SBP2 "C2PT" is analyzed. If "C2PT = 1", the transition to block 60 GAW.

 In block 59 of the GAW, the symbol “SBT2: 1” and “ZPS1: 1” rewrites the symbol from SBP2 to SBP1 (Fig. 1). The transition to block 58 GAW.

 In block 60 GAW analyzes the sign of the presence of the signal "CHTPR" (figure 1). If "ChTPR = 1", the transition to block 61 GAW, otherwise to block 60 GAW.

 In block 61 GAW analyzes the sign of emptiness SBP1 "C1PT = 1" (figure 1). On the basis of the transition to block 72 GAW.

 In block 62 GAW, the symbol is issued from SBP1 to the output channel by the commands "CTS1: 1" and "PB: 1" and at the same time the synchronization output signal "SIN: 1" is issued. When this signal "RV" the output of the bus driver is connected to its input (Fig.6).

 In block 63 GAW analyzed the sign of the void SBP1 "S1PT = 1" (figure 1). On the basis of the transition to block 65 GAW.

 In block 64 of the GAW, the commands “ЧТС1: 1”, “ЗПС2: 1”, “А1: 1”, “А2: 1” record the character from SBP1 to SBP2 (Fig. 1). The transition to block 63 GAW.

 In block 65 GAW analyzes the presence of the signal "WHAT = 1" (figure 1). If "WHAT = 1", the transition to block 66 GAW, otherwise to block 65 GAW.

 In block 66 GAW analyzes the sign of emptiness SBP2 "C2PT = 1" (figure 1). On the basis of the transition to block 72 GAW.

 In block 67 GAW analyzes the sign of the boundary between the words in the stacks (Fig. 4,5) "GS". If "HS = 1", the transition to block 69 GAW.

 In block 68 of the GAW, the commands “CTS2: 1”, “ZPS1: 1” correspond to the symbol from SBP2 to SBP1 (Fig. 1). The transition to block 67 GAW.

 In block 69 GAW analyzes the sign of the emptiness SBP1 "S1PT" (figure 1). If "S1PT = 1", the transition to block 65 GAW.

 In block 70 GAW, the symbol is output to the output channel from SBP1 by the commands “РВ: 1”, “ЧТС1: 1 and at the same time the signal“ SYN: 1 ”is issued. The transition to block 69 GAW.

 In block 71, the GAW analyzes the sign of SBP1 or SBP2 is full of "C1PN or C2PN" (Fig. 1). If the sign is equal to zero, there is a transition to block 6 GAW, otherwise the sorting is urgently stopped and the transition to block 72 GAW.

 In block 72 GAW issued an external signal of readiness of the device "GT: 1" (figure 1).

 The operation of the information sorting device is as follows.

 External control signals "ZAGR", "CHTPR", "WHAT", "START" and "RESET" are received in the control unit 8, the signals "GT" and "SIN" from the control unit 8. The input channel is an interface by which words to be sorted arrive character by character. The output channel is an interface through which sorted words are received character-by-character to an external device.

 The main idea of the work is as follows.

 Sorting data occurs as it becomes available. At the input of the sorting device, the current word (number) is received and written into the BOP, where the symbol is a component of the word, which has a fixed length. The beginning of the sorted array is considered the first character of the smallest number (words), the end is the last character of the largest, while the array is stored in the stacks of blocks SBP1 and SBP2 (Fig. 1). The indicated stacks (Fig. 4,5) are organized in the form of LIFO queues (the last to come first went), the beginning of the sorted array being the first to come on the stack of SBP2, and the end to go first to the stack of SBP1. A search is made for the weight place of the current word in the array of already ordered data by symbol-by-symbol comparisons by the ES comparison element of the current word with the words in the array of ordered data. The weighted place of a word is the position of the current word in the ordered array, when the word closest to it, which is one position earlier, is less than or equal to it, and the word that is placed one position later is greater than or equal to it.

 Search for the weight of the word (current) is as follows. The first character of the current word is compared by a comparison element (ES) with the first character of the first word from the stack of the SBP1 block (Fig. 1). If the result of the comparison is equality, the second characters are compared, etc. until the result of the comparison is “more” or “less,” or one of the words does not end. Moreover, the compared characters are overwritten from SBP1 to SBP2. The result of the comparison of two words: if the words ended at the same time, they are equal, if the signal “MORE = 1” was issued by the comparison element (ES) (that is, the word symbol from the BOP is larger than the word symbol from SBP1), or the word of the block SBP1 has ended, and the word BOP no current word in BOP, more than the investigated number from SBP1. If the signal “LESS = 1” is issued by the comparison element (that is, the word character from BOP is less than the word character from SBP1), or the current word has ended, and the word being studied (from SBP1) is not the current word larger than the word studied. Further, if the current word is equal to the word studied, it is written behind it in SBP2, if the current word is larger, it is compared with the next largest word studied, until the current word is equal to the next word from the stack, then it is written after the next word studied, or it won’t less than the next one, then the current word from the BOP is written in front of it, or the end of the array is not reached, when the end of the array is reached, the current word from the BOP is written to the end. If the current word is less than the studied one, then it is compared with the next nearest smaller studied one until it becomes equal to the next one, or more than it, then the word from the BOP is written to the array behind the studied word (i.e., a position closer to the end of the array), or not the beginning of the array will be reached, when the beginning is reached, the word from the BOP is written to the array first.

 The above-described entries in the BOP, the search for a weight place and the entry in the stacked memory blocks storing the sorted array occur character-by-character, are repeated n times, where n is the number of words to be sorted. After that, the ordered information is symbolically issued to the output channel in ascending or descending order.

 Block 2 of RAM contains a counter (MF), a register (WG), random access memory (RAM) and a comparator (KP) (figure 2). To the inverse input of RAM, the choice of the crystal is fed by the constant "0" (not VK). Input information I1 goes to RAM input. The signal "OSCH = 1" is the zeroing of the counter. By the signal "RAM = 1" the input symbol is written into RAM at the address stored in the counter. By the signal "INSC = 1" the content of the counter is increased by one. By the signal "ЗПРГ = 1", issued at the end of the word download, the contents of the counter, in this case equal to the number of characters in the word, are recorded in the register. If "ZPOZU = 0", the symbol located at the address stored in the counter is output to the output of RAM I2. The comparator (KP), the inputs of which are the outputs of the register and the counter, determines the sign of the end of the word "KS", issued to the control unit 8 with the equality of these codes (figure 1).

 Comparison element 3 contains a comparator (KP) (Fig. 3), which compares the I2 and I3 symbols arriving at its inputs and outputs to the control unit 8 (Fig. 1) signals "MORE = 1" (if I2 is greater than I3), "LESS = 1 "(if I2 is less than I3)," EQUAL = 1 "(if I2 is equal to I3).

 The stack block 4 of the memory contains a stack (figure 4) and serves to store part of the sorted array. By the signal "ZPS2 = 1", the I5 symbol is written to the top of the stack, by the signal "CTS2 = 1", the symbol to the I4 output is read from the top of the stack. When this stack signals are issued to the control unit 8 (figure 1) "C2PN = 1" (if the stack is full) and "C2PT = 1" (if the stack is empty).

 Stack unit 5 memory contains a stack (figure 5) and serves to store another part of the sorted array. By the signal "ЧТС1 = 1", the symbol for the I3 output is read from the top of the stack, by the signal "ЗПС1 = 1" the I4 symbol is written to the top of the stack. When this stack signals are issued to the control unit 8 (Fig. 1) "C1PN = 1" (if the stack is full) and "C1PT = 1" (if the stack is empty).

 Block 6 switching and identification (Fig.6) contains a bus driver (BF) with three output states, a comparator (CP), a switch (KM), a code generator (FC). Serves for issuing an ordered array of words to the output channel OUT and switching signals from three sources to input SBP2 (Fig. 1). By the signal "RV = 1" information from the input of the IF I3 is transmitted to its output I6. When "PB = 0", its output is in a high impedance state. Signals A1 and A2 go to the address inputs of the KM switch, I5 is its output, to which I3 input information is transmitted via "A1 = 1", "A2 = 1", I2 is transmitted through "A1 = 1", "A2 = 0", or the service code of the boundary between words generated by the code generator (FC) is transmitted, the specified connection is made with "A1 = 0", "A2 = 1". The output of the switch I5 is fed to the input SBP2 (figure 1). The comparator, at the inputs of which I3 and the FC output go, determines the sign of the boundary between the ordered words "GS", issued to the control unit 8 (Fig. 1) when the symbol located at the top of the SBP1 stack is equal to the service code.

 The control unit 8 is synthesized based on the GAW control (Fig.7) in a known manner (2).

 Marked GAW operation of the control unit 8 is shown in Fig.8, where indicated.

Logical conditions:
X1: RESET
X2: "START"
X3: "S2PT and C1PT"
X4: "WHAT"
X5: "ChTPR"
X6: ZAGR
X7: "S2PT"
X8: LESS
X9: "GS"
X10: "GS or C2PT"
X11: "MORE"
X12: "EQUAL"
X13: "KS"
X14: C1PT
X15: "S2PN or C1PN"
Operators:
U1: "TTS1: 1"
U2: "TTS2: 1"
U3: "OSSH: 1"
U4: RV: 1
U5: "RAM: 1"
Y6: "SIN: 1"
U7: "INSC: 1"
U8: "ZPRG: 1"
U9: “A1: 1”
U10: “A2: 1”
U11: "ZPS1: 1"
U12: "GT: 1"
U13: "ZPS2: 1"

Claims (1)

 INFORMATION SORTING DEVICE comprising two stacked memory blocks, a comparison element, a control unit, characterized in that input and output channels, a random access memory unit, a switching and identification unit are introduced therein, the first to fifth control outputs of the control unit being connected respectively from the first the fifth control inputs of the RAM block, the information input of which is connected to the input channel, the control output with the fourth control input of the control unit, the information output with the first the input of the comparison element and the second information input of the switching and identification unit, the control output of the latter is connected to the fourteenth control input of the control unit, the first to third control inputs are connected respectively from the tenth to twelfth control outputs of the last, the second information output with the output channel, the first information output with the information input of the second stacked memory block, the first and second control inputs of the latter are connected respectively to the sixth and seventh control outputs of the control unit, the first and second control outputs, respectively, with the tenth and eleventh control inputs of the latter, an information output with the information input of the first stack memory block, the first and second control inputs of which are connected to the eighth and ninth control outputs of the control unit, the first and second control outputs - respectively with the twelfth and thirteenth control inputs of the last, information output with the first information input of the switching unit identification and identification and with the second information input of the comparison element, the first to third control outputs of the latter are connected respectively to the fifth to seventh control inputs of the control unit, from the first to third control inputs of the control unit, as well as the eighth and ninth control inputs of the latter are external inputs of the device , thirteenth and fourteenth control outputs of the control unit are external outputs of the device.

Images