RU2024183C1 - Digital filter - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: known device having first address counter 6, second address counter 10, and third address counter 11 whose address inputs are connected to outputs of reference generator 7 and outputs of first and second address counters are connected, respectively, to first and second address inputs of first read-only storage unit 8, and also input register 3 whose data input functions as digital filter input, output of device being output of output register 2, is provided in addition with second read-only storage unit 9, main storage 4, and multiplying accumulator 1, all inserted between output of third address counter 11 and data input of output register 2, as well as ratio storage unit 5 connected between output of third address counter and data input of multiplying accumulator 1, its other address input being combined with other address input of second read-only storage unit 9 and with first address input of first read-only storage unit 8 whose control output is connected with control inputs of main storage, input and output registers, and multiplying accumulator and its address input is connected to other address input of main storage; output of multiplying accumulator 1 is combined with output of input register 3 and with main storage input/output. EFFECT: improved speed. 1 dwg

Description

 The invention relates to computer technology and can be used in digital signal processing systems.

 A device is known for performing digital filtering, comprising a pulse shaper, an address counter, a memory block of ranks of sample coefficients, a multiplexer, a synchronization block. Filtering the signals is carried out according to the convolution formula [1].

 This device has a narrow range of functionality, a low degree of unification, significant hardware costs.

 Also known is a device designed to perform digital filtering, containing input and output registers, address counters, a reference generator, read-only memory, microprocessor sections with an accelerated transfer circuit [2].

 This device has a wide range of functionality and a high degree of unification.

 The process of restructuring and adapting the calculation algorithm to a specific DSP algorithm in this device is ensured by appropriate program changes that do not affect the connection diagrams and the structure of the processor as a whole. However, this device has a low speed, which is due to the software, and not the hardware implementation of the calculation procedure. Any operation in such a processor requires several microcommands, each of which represents elementary logical operations, shift operations, memory retrieval, transfer, etc. The micro-ROM ROM contains both the address of where the operands are, and information about what operations you need to perform with them. Therefore, the calculation of a single sample, for example, according to the convolution formula, may require the execution of several tens to several hundred microcommands. The achievable sampling rate for this device is on the order of units of kilohertz with dozens of NFCs.

 The purpose of the invention is improving performance.

 This is achieved by the fact that in the digital filtering device containing the first, second and third address counters, the address inputs of which are connected to the outputs of the reference generator, and the outputs of the first and second of which are connected respectively to the first and second address inputs of the first block of read-only memory, and an input register, the information input of which is the input of a digital filtering device, the output of which is the output of the output register, between the output of the third address counter and the information input of the output In the second register, a second read-only memory unit, random access memory (RAM) and a storage multiplier are connected in series, a coefficient memory unit is connected between the output of the third address counter and the information input of the storage multiplier, another address input of which is combined with another address input of the second read-only memory unit and with the first address input of the first block of read-only memory, the control output of which is connected to the control inputs of RAM, input and output registers and the storage multiplier, and address output - with another address input of RAM, while the output of the storage multiplier is combined with the output of the input register and the input-output of RAM.

 The proposed device contains a minimum number of types of elements: address counter, random access memory (RAM), memory blocks of RAM address, coefficient memory implemented on read-only programmable memory devices (ROM), multiplier-drive, register, provides for the possibility of using various such devices digital processing devices, for example, a non-recursive digital filter (NFC), a recursive digital filter (RCF), cascading filters, step-by-step conversion systems sampling frequency, multichannel digital filter, discrete Fourier converters and provides high performance.

 A comparative analysis of the proposed solution with the prototype shows that the claimed device differs from the known one in that between the output of the third address counter and the information input of the output register, the second RAM unit and the storage multiplier are connected in series, and between the output of the third address counter and the information input of the multiplier drive included block memory coefficients.

 Thus, the proposed device meets the criteria of the invention of "novelty." When analyzing the known and claimed devices, it was found that the claimed device has properties that do not coincide with the properties of known solutions, therefore, it has significant differences.

 The drawing shows a functional diagram of the device.

 The digital signal processing device comprises a storage multiplier 1, the output of which is connected to the input of the output register 2, to the output of the input register 3, to the input-output of the random access memory of the samples of the input signal of the RAM and to the first information input of the multiplier-drive 1, the second information input which is connected to the output of the coefficient memory unit 5 implemented on the EEPROM, the group of address inputs of which are connected to the outputs of the address counter 6, the input of which is connected to the output of the reference generator 7, first the second and second blocks 8, 9 of permanent memory implemented on the ROM, the address outputs of which are connected to the address inputs of the random access memory of the samples of the input signal, and the control outputs of the first block 8 of constant memory are connected to the control inputs of the random access memory 4, input and output registers 3, 2, of the storage multiplier 1, the first group of address inputs of the first block 8 of constant memory is connected to the outputs of the first address counter 6 and with the first group of address inputs of the second block 9 of constant memory hi, the second group of address inputs of the first block 8 of constant memory is connected to the outputs of the second address counter 10, the input of which is connected to the second output of the reference generator 7, the second group of address inputs of the second block 9 of constant memory and block 5 of the coefficient memory are connected to the address outputs of the third address counter 11, the input of which is connected to the third output of the reference generator 7.

 Description of the operation of the device.

h_ix(t-i), (1) где h_i - коэффициенты импульсной характеристики (КИХ);
x(t-i) - отсчеты входного сигнала, осуществляется посредством сдвига адреса ячеек ОЗУ 4 входных отсчетов относительно адреса ППЗУ коэффициентов 5 ИХ (КИХ) синхронно с вычислением каждого выходного отсчета. Адрес ОЗУ 4 линии задержки и ППЗУ 5 КИХ задается счетчиком 6, коэффициент пересчета (число состояний) которого К₁ выбирается из условия К₁ ≥N. Один полный цикл работы счетчика 6 соответствует вычислению одного отсчета сигнала Y_j. Коды состояний счетчика 10 разбивают адресное пространство ПЗУ 8 на К₂сектора, где К₂ ≥N - коэффициент пересчета счетчика 10. В каждом секторе записываются последовательности адресов ОЗУ, причем к-я последовательность адресов, соответствующая к-му состоянию счетчика 10 (К=0, К2-1), отличается от (К-1)-й последовательности циклическим сдвигом элементов (адресов ОЗУ) на одну позицию. Таким образом, смена состояния счетчика 10, происходящая после вычисления каждого отсчета сигнала Yj, вызывает циклическое смещение адресов ячеек ОЗУ относительно адресов ячеек ПЗУ коэффициентов (смещение сигнала в линии задержки), обеспечивая тем самым выполнение операции свертки.Organization of addressing RAM cells 4 and ROM 5, 8, 9 coefficients of the processing algorithm when implementing convolution of the form
Y _j =

h _i x (ti), (1) where h _i are the impulse response coefficients (FIR);
x (ti) - samples of the input signal, carried out by shifting the address of the RAM cells 4 input samples relative to the address of the ROM coefficients 5 of them (FIR) synchronously with the calculation of each output sample. The address of the RAM 4 of the delay line and the ROM 5 of the FIR is set by the counter 6, the conversion factor (number of states) of which K ₁ is selected from the condition K ₁ ≥N. One full cycle of the counter 6 corresponds to the calculation of a single sample signal Y _j . The status codes of counter 10 divide the address space of ROM 8 into K ₂ sectors, where K ₂ ≥N is the conversion factor of counter 10. In each sector, sequences of RAM addresses are written, and the k-th address sequence corresponding to the k-th state of counter 10 (K = 0, K2-1), differs from the (K-1) -th sequence by a cyclic shift of elements (RAM addresses) by one position. Thus, the change of state of the counter 10, which occurs after calculating each sample of the signal Yj, causes a cyclic shift of the addresses of the RAM cells relative to the addresses of the cells of the ROM coefficients (signal shift in the delay line), thereby ensuring the convolution operation.

When implementing multi-channel (n-channel) devices, devices with parallel connection and recursive or non-recursive digital filters, as well as when performing transformations that require multiple operations of the same type, a counter 11 with a conversion factor n and a second read-only memory block 9 are used, by means of which the RAM address field is divided into n "pages", the change of which is done when the state of the counter 11 changes when moving from one of the parallel devices to another or when changing e from one operation of the same type to the next. In this case, a pulse sequence with a frequency F, determined by the complexity of the devices (for example, filters) and the maximum speed of the units included in the device, primarily the time of multiplication of UN1, is supplied to the counting input of the counter 6 from the reference generator. A sequence of pulses with a frequency of F / K _{1 is} supplied to the counting input of the counter 11, and a frequency of F / K ₁ ˙n is supplied to the input of the counter 10.

 When cascading the DF on this device is implemented, for example, for the case of stepwise conversion of the sampling frequency, it is sufficient to appropriately change the program ROM 8, 9 of the RAM address 4 LZ and set a new multiple of the period of individual links update period of the RAM address 4 using counter 11.

 By changing the program EEPROM 8 and 9, recursive DSP algorithms are implemented. The operation mode of the multiplier-accumulator 1, its tristable output stage, as well as RAM and input and output registers are also controlled by the ROM 8, where the control program is written for these purposes.

 High performance in the proposed structure is ensured by the hardware implementation of the basic DSP multiplication with accumulation using the multiplier-accumulator UN1 and the possibility of organizing a conveyor mode of operation. At the same time, processing coefficients are stored in ROM 5 (for example, FIR), and in ROM 8, 9 there is directly the address of RAM cells 4, the memory of the input samples of the processed signal when implementing the NCF, as well as the output samples for the RCF or intermediate results when implementing other DSP algorithms .

 The conveyor mode of operation is organized by simultaneously generating the RAM address, fetching the required sample from the RAM and the processing coefficient from the ROM, and also performing the operation of the DSP algorithm.

=

или для случая многоканального режима работы
F_д=

=

где t_зад - большее из времен формирования адреса ОЗУ, формирования адреса ПЗУ КИХ, выборки содержимого ОЗУ, одного умножения с накоплением;
t_Rg - время записи в выходной регистр.So, for example, when implementing a NFC of order N by expression (1), the maximum possible filter sampling frequency is
F _d =

=

or for the case of multi-channel operation
F _d =

=

where t _ass is the larger of the times the RAM address is formed, the FIR ROM address is generated, the RAM contents are sampled, one multiplication with accumulation;
t _Rg is the time of writing to the output register.

Actually, t _ass is determined by the time of multiplication with accumulation. The achievable sampling frequencies in this case are of the order of hundreds of kilohertz for dozens of NFCs.

 The proposed digital filtering device allows, in comparison with the prototype, to increase the speed of the device.

Claims (1)

 DIGITAL FILTER containing the first, second and third address counters, the address inputs of which are connected to the outputs of the reference generator, and the outputs of the first and second counters, respectively, to the first and second address inputs of the first block of read-only memory, as well as an input register, the information input of which is an input digital filter, the output of which is the output of the output register, characterized in that, in order to improve performance, between the output of the third address counter and the information input of the output register and a second block of read-only memory, random-access memory and a storage multiplier are connected in series, between the output of the third address counter and the information input of the storage multiplier, a coefficient memory unit is included, the other address input of which is combined with another address input of the second read-only memory block and with the first address input the first block of read-only memory, the control output of which is connected to the control inputs of random access memory, input and output registers, and intelligently Ithel storage, and an address output - to another address input of the random access memory, the output of multiplier-accumulator is combined with the output of the input register and input-output of a random access memory.