RU2021632C1 - Divider - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has m n-bit adders 1 (m is odd number, n is even number), four modulo 2 convolution units 2-5, two comparison circuits 8, 9, and newly introduced fifth and sixth modulo 2 convolution units 6, 7 with appropriate ties. EFFECT: improved speed of parity check dividers. 4 dwg

Description

 The invention relates to computer technology and can be used in the development of high-speed devices for dividing numbers with parity.

 A device for division, built on a single-cycle principle and containing mn-bit adders m is an odd number, n is an even number) [1]. The device implements a method of dividing numbers without restoring residues.

 The disadvantages of this device are the relatively low speed and low reliability of the generated results due to the large number of equipment used and the lack of built-in controls.

 The closest in technical essence to the present invention is a device for division, containing mn-bit adders (m + n-1 is the bit capacity of the dividend, m is an odd number, n is an even number), two comparison elements and four convolution nodes modulo two, moreover, the first input of the first adder is connected to the highest bits (from the first to the n-th) of the input of the divisible device, the bits of the output of the result, except the senior, of each j-th adder (1≅ j ≅ m-1) and (n + j) the input bit of the divisible device is connected to the corresponding bits of the first input (j + 1) -th adder, the second inputs of all adders are connected to the input of the device divider, the upper bits of the outputs of the jth adders of the group and the transfer output from the highest bit of the mth adder form the group of outputs of the private device, the output of the result of the mth adder is the output of the remainder of the device, the inverting input of the first adder is connected to the input of the logical unit of the device, the highest bit of the output result of each j-th adder is connected to the inverting input of the (j + 1) -th adder, the inputs of the control bits of the dividend and div device, the outputs of the internal inter-bit transfers of all adders and the input of the logical unit of the device are connected to the corresponding inputs of the first convolution node modulo two, the output of the result of the mth adder is connected to the input of the second convolution node modulo two, the input of the third convolution node modulo two is connected to the input of the device divider, the group of outputs of the private device is connected to the group of inputs of the fourth convolution node modulo two, the outputs of the second and fourth convolution nodes modulo two are respectively outputs the control bits of the remainder and the private device, the outputs of the first and second convolution nodes modulo two are connected respectively to the first and second inputs of the first comparison element, the first and second inputs of the second comparison element are connected respectively to the input of the control discharge of the device divider and the output of the third convolution node modulo two , the outputs of the first and second comparison elements form the output of the error sign of the device [2].

 This device provides high reliability of the results generated in it due to the presence of built-in hardware parity control tools.

 The disadvantage of this device is the lack of high speed, due to the fact that the formation of quotients is carried out according to the significant digits of residues.

 The aim of the invention is to increase the speed of the device due to the formation of numbers of quotient quotient transfers from sign digits of residues.

 The goal is achieved by the fact that the division device containing mn-bit adders (m + n-1-bit divisibility, m is an odd number, n is an even number), four convolution nodes modulo two and two comparison elements, and the first input the first adder is connected to the highest bits (from the first to the n-th) of the input of the divisible device, the bits of the output of the result, except for the highest, of the jth adder (1≅ j ≅ m -1) and the (n + j) -th bit of the input of the dividend devices are connected to the corresponding bits of the first input of the (j + 1) -th adder, the second inputs of all adders are connected s to the input of the device divider, the output of the mth adder is the output of the remainder of the device, the inputs of the control bits of the dividend and device divider, the input of the logical unit of the device, the outputs of the internal interdigital transfers of all adders are connected to the corresponding inputs of the first convolution node modulo two, the output of which is connected with the first input of the first comparison element, the input of the second convolution node modulo two is connected to the output of the result of the m-th adder, and the output is connected to the output of the control discharge of the remainder The input of the third convolution node modulo two is connected to the input of the device divider, and the output to the first input of the second comparison element, the second input of which is connected to the control discharge input of the device divider, the outputs of the first and second comparison elements are connected to the output of the device error indicator, input the inverting of the first adder is connected to the input of the logical unit of the device, two nodes of convolution are introduced modulo two, and the transfer output from the high order of the j-th adder is connected to the inversion input of the (j + 1) -th sum ator, carry outputs from the senior bits of all adders form a group of outputs of the private device, carry outputs from the senior bits of adders from the first to (m-1) -th are connected to the input of the fourth convolution node modulo two, the output of which is connected to the fifth input of the first convolution node modulo two and with the first input of the fifth convolution node modulo two, the second input of which is connected to the transfer output from the highest bit of the m-th adder, and the output to the output of the control bit of the private device, the outputs of the highest bits of the result are sum Hur first to (m-1) -th are connected to the first input of the sixth node modulo two convolution, a second input coupled to an output of the second convolution node modulo two, and an output - to a second input of the first comparison element.

The inventive device contains the following distinctive features not found in any other of the known devices:
1) the fifth and sixth convolution nodes modulo two;
2) the transfer output from the high order bit of each adder is connected to the corresponding output bit of the private device, i.e. in the device, the formation of quotients is carried out by transfers from the higher digits of the adders;
3) the transfer output from the high order of the jth adder is connected to the inverting input of the (j + 1) th adder;
4) the outputs of the senior bits of the results of the first to (m-1) -th adders are connected to the first input of the sixth convolution node modulo two;
5) the output of the fourth convolution node modulo two is connected to the fifth input of the first convolution node modulo two.

 The above distinguishing features together provide an increase in the speed of the device with the same reliability of the results generated in it.

 Thus, since the proposed device has distinctive features that are absent in all known analogues and due to which the achievement of the goal is achieved, that the claimed technical solution meets the criterion of "significant differences".

 Figure 1 shows the structural diagram of a device for dividing; figure 2 - for m = 3 and n = 4, the implementation of the device in the form of an iterative network without monitoring equipment; figure 3 - cell structure of the iterative network; figure 4 - two examples explaining the division of numbers in a working and faulty device depicted in figure 2.

The device for dividing numbers (Fig. 1) contains mn-bit adders (n + m-1 bit divisible, m is an odd number, n is an even number) 1 ₁ -1 _m , nodes 2-7 convolution modulo two from the first to sixth, respectively, the first 8 and second 9 comparison elements, input 10 ₁ n high order of the divisible device, input 10 ₂ (m-1) low order of the divisible device, input 11 - device divider, input 12 of the logical unit of the device, input 13 of the control bit of the dividend devices, input 14 of the control discharge of the device divider, output 15 of the private device, output 16 of the control Private compression discharge device, the output device 17, a residue discharge outlet 18 of control device residue, yield 19 feature a device error, yield: 20 ₁ -20 _m (n-1) LSBs result adders 1 ₁ -1 _m respectively, yield 21 ₁ -21 _m senior bits of the results of adders 1 ₁ -1 _m respectively, outputs 22 ₁ -22 _{m of} internal inter-bit transfers of adders 1 ₁ -1 _m, respectively, outputs 23 ₁ -23 _m transfers from the senior bits of adders 1 ₁ -1 _m, respectively.

The first input of the adder 1 _{1 is} connected to the input 10 ₁ n of the highest bits of the divisible device, the bits of the output of the result, except for the highest, of the adder 1j (1≅j≅m-1) and the (n + j) th bit of the input of the divisible device (it is fed to input 10 _{2 of the} device) are connected to the corresponding bits of the first input of the adder 1 _{j + 1} , the second inputs of the adders 1 ₁ -1 _{m are} connected to the input 11 of the device divider, the result output (outputs 20 _m and 21 _m ) of the adder 1 _m is the output 17 of the remainder of the device , inputs 13, 14 of the control bits of the dividend and divider, respectively, input 12 of the logical unit devices and outputs 22 ₁ -22 _{m of} internal inter-bit transfers of adders 1 ₁ -1 _m connected to the corresponding inputs of the first node 2 convolution modulo two, the output of which is connected to the first input of the first comparison element, the input of the second node 3 convolution modulo two is connected to the output result (outputs 20 _m and 21 _m ) of the adder 1 _m , and the output is connected to the output 18 of the control discharge of the remainder of the device, the input of the third node 4 convolution modulo two is connected to the input 11 of the device divider, and the output to the first input of the second comparison element 9, the second entrance is th connected to the input 14 of the control discharge divider device outputs elements 8, 9 comparisons are connected to the output 19, device error flag, the input of inverting adder 11 is connected to the input 12 of the logical device units, yield 23 _j transfer from MSB of adder 1 _j is connected to the input of inverting adder 1 _{j + 1} , outputs 23 ₁ -23 _m transfers from the upper digits of the adders 1 ₁ -1 _m form a group of outputs 15 of the private device, outputs 23 ₁ -23 _m-1 transfers from the upper digits of the adders 1 ₁ -1 _{m-1 are} connected with the input of the fourth node 5 convolution modulo two, the output of which is connected to the fifth input of the first node 2 convolution modulo two and with the first input of the fifth node 6, convolution modulo two, the second input of which is connected to the output 23 _m transfer from the senior discharge of the adder 1 _m , and the output to the output 16 control bits of a private device, outputs 21 ₁ -21 _{m-1 of the} highest bits of the results of adders 1 ₁ -1 _{m-1 are} connected to the first input of the sixth node 7 convolution modulo two, the second input of which is connected to the output of the second node 3 convolution modulo two , and the output with the second input of the first element 8 is compared i.

Consider the purpose and implementation of the nodes and elements of the device. Adders 1 ₁ -1 _m n-bit (m is an odd number, n is an even number) binary combination type. They are interconnected with the inputs and outputs of the device in such a way that they form a single-cycle matrix divider that implements the division method without restoring residues. Depending on the value of the control signal at the inverting input of the adder, the information supplied to its second input from the input 11 of the device divider is either inverted (if the value of the previous remainder is positive) or passes unchanged (if the value of the previous remainder is negative). Simultaneously with inverting the information, a logic unit signal is supplied to the adder transfer input, which ensures the supply of a divider to the adder in an additional code. Thus, each adder 1 ₁ -1 _m is an adder with a controlled inverter at the second input. The transfer in adders 1 ₁ -1 _m can be arranged in any way.

In Fig. 2, for m = 3 and n = 4, an implementation of a single-cycle matrix divider without recovery of residuals is shown (in Fig. 1 it is formed by adders 1 ₁ -1 _m with corresponding connections) in the form of an iterative network. It divides the dividend X = X _o , X ₁ X ₂ X ₃ X ₄ X ₅ by the divisor Y = 0, Y ₁ Y ₂ Y ₃ , resulting in the quotient Z = Z ₀ ; Z ₁ Z ₂ and shifted by two digits to the left, the remainder R = R _0, R ₁ R ₂ R ₃ (the true remainder is P / 4). It is assumed that the divisor and divisor are positive numbers, with the divisor 1 / 2≅Y≅1 divisible by X≅2Y.

(T_i+C_i+1)⊕ C_i, где С_i и S^f _i - перенос и сумма сумматора соответственно;
G_i=А_iВ_i - функция генерации переноса;
Т_i=А_i+В_i - функция транзита переноса;
А_i,В_i,С_i+1 - разрядные слагаемые сумматора.The network uses cells 24 of the same type. Cell 24 (figure 3) contains a two-input addition element 25 modulo two and a single-bit binary adder 26. If as an adder 26 to use a single-bit binary adder with a functional dependence of the sum on the transfer, then in the proposed device for dividing the equipment for parity will be detected all result errors caused by a single device malfunction or a single error in the input data. The operation of the adder with the functional dependence of the amount of transfer is described by the following logical expressions:
C _i = G _i + T _i C _{i + 1} ,
S $\genfrac{}{}{0ex}{}{\text{f}}{\text{i}}$ = f _i ⊕ C _i =

(T _i + C _{i + 1} ) ⊕ C _i , where C _i and S ^f _i are the carry and sum of the adder, respectively;
G _i = A _i B _i - transfer generation function;
T _i = A _i + B _i - transfer transit function;
And _i , B _i , C _{i + 1} - bit terms of the adder.

 As in the prototype device, the adder can be implemented on three elements 2I, one element 3I, three elements 2 OR, one element NOT and one two-input element of addition modulo two.

P

C^k, где Р_х,Р_y - контрольные разряды (четности)делимого и делителя соответственно;
Р_Сk - четность внутренних межразрядных переносов (переносов из (n-1) младших разрядов) К-ого сумматора;

- знак суммирования по модулю два;
С^k - значение переноса из старшего разряда (внешнего переноса) k-ого сумматора.The first convolution node 2 modulo two forms a value
P ₂ = P _x ⊕ P _y ⊕ 1⊕

P

C ^k , where P _x , P _y - control bits (parity) of the dividend and divider, respectively;
Р _Сk - parity of internal inter-bit transfers (transfers from (n-1) lower digits) of the K-th adder;

- a summation sign modulo two;
With ^k - the value of the transfer from the high order (external transfer) of the k-th adder.

The second convolution unit 3 modulo two forms the value of the control discharge of the remainder of the device. The third convolution unit 4 modulo two forms the value of the control discharge of the divider received at the inputs of the adders 1 ₁ -1 _m and at the input 11 of the device. The fourth convolution node 5, modulo two, forms the parity value of the transfers from the higher bits of the adders from the first to the (m-1) th. The fifth convolution unit 6 modulo two forms a control discharge of a partial device.

S^k⊕ P_R, где S^k - значение суммы старшего разряда k-го сумматора;
Р_R - значение контрольного разряда остатка устройства.The sixth node 7 of the convolution modulo two forms a value
P ₇ =

S ^k ⊕ P _R , where S ^k is the value of the sum of the highest order of the k-th adder;
P _R is the value of the control discharge of the remainder of the device.

The first comparison element 8 checks for equality
P ₂ = P ₇ , which should be performed when the operation is completed correctly.

Thus, the second comparison element 9, together with the third convolution node 4 modulo two, controls the receipt of the divider at the second inputs of the adders 1 ₁ -1 _m . Nodes 2,3,5 and 7 of the convolution modulo two and the first element 8 of the comparison control the parity of the correct execution of the division operation.

The device operates as follows. After filing a divisible device at inputs 10 ₁ and 10 ₂ , and a divisor at input 11, the computing process of determining the quotient and remainder in the device begins using the method without restoring residues. After completion of the computing process in the device, at its outputs 15 and 17, the quotient and remainder are formed, respectively, and at the outputs 16 and 18, the values of the control bits of the quotient and remainder are formed, respectively. Simultaneously with the operation of the device for dividing the numbers at the outputs 22 ₁ -22 _{m of} adders 1 ₁ -1 _m , internal inter-bit transfers are formed, which are fed to the input of the first node 2 of the convolution modulo two, to which the values of the control bits of the divisible, divider and logical signal are supplied units from the inputs 13, 14 and 12 of the device, respectively. From the output of the fourth node 5 of the convolution modulo two to the fifth input of node 2, the parity value of the transfers from the upper digits of the adders from the first to the (m-1) -th is supplied. The parity value of the remainder P ₃ formed on the second node 3 of the convolution modulo two is summed modulo two on the sixth node 7 of the convolution modulo two with the values of the sums of the highest digits of the adders from the first to (m-1) th. The values obtained at the outputs of convolution nodes 2 and 7 modulo two are compared with each other on the first comparison element 8. If these values do not match, an error signal is generated at the device output 19.

If the adders 1 ₁ -1 _{m are} built on single-bit binary adders with a functional dependence of the sum on the transfer, then in the proposed device, the parity monitoring equipment will detect all errors of the result caused by a single device malfunction. It also provides detection of all errors caused by a single error divisible at the inputs 10 ₁ and 10 _{2 of the} device. To detect single errors in the divider, which can lead to an undetectable class of errors in the operation of the device, there is a check for the parity of the arrival of the divider to the input 11 of the device and to the inputs of the adders 1 ₁ -1 _m using the third convolution node 4 modulo two and the second element 9 comparisons.

 In FIG. 4 shows two numerical examples, confirming the correct functioning of the proposed device for division. Examples are considered with reference to the iterative network depicted in FIG. 2 under the assumption that the dividend is X = 1.00101, the divisor is Y = 0.111. In the case of the correct division, the quotient Z = 1.01 shifted by two digits to the left, the remainder R = 0.010 (the true value of the remainder is R = 0.00010). Figure 4, a explains the division of numbers in a working device, in figure 4, b - in a faulty one. It is assumed that the malfunction of the device is due to the presence of a constant unit at the transfer output of the adder 26 of the cell 24, hatched in figure 2. The point in FIG. 4 indicates the formation of an internal inter-bit transfer, the value of which is unity and which is taken into account when predicting the remainder parity.

 The * sign indicates the formation of a unit transfer from the high order of the adder (external adder transfer), which forms a unit in the corresponding category of the quotient.

 A comparison of the proposed device and the prototype device by the speed of division of numbers.

In the prototype device [2], the digits of the quotient are generated by the inverse values of the sums of the upper digits of the adders 1 ₁ -1 _m and the inversion of the divider in the adders is controlled by the inverse value of the sums of the highest digits of the corresponding adders. Therefore, in relation to the iterative network in figure 2 of the prototype, the time of division of numbers is
T _D = 3 (3 τ +3 τ +2 ^. 2 τ +6 τ) = 48 τ.

In the proposed device, the digits of the quotient are formed by transfers from the upper digits of the adders 1 ₁ -1 _m and the inverting of the divider in the adders is controlled by transfers from the senior digits of the corresponding adders. Therefore, in relation to the iterative network in figure 2, the time of division of numbers is
T _D = 3 (3 τ +3 τ +2 ^. 2 τ +2 τ) = 36 τ.

 Comparing the execution time of the operation, we find that in the proposed device, the speed increased by 25%.

 The technical and economic advantage of the proposed device for dividing numbers in comparison with the known one consists in higher speed (by 25%) while maintaining the same reliability of the generated results.

Claims (1)

 DEVICE FOR DIVISION, containing m n-bit adders (n + m - 1 - bit divisibility, m-odd number, n-even number), four convolution nodes modulo two and two comparison elements, the first input of the first adder connected to the input the highest digits (from the first to the n-th) of the divisible device, the output of the digits of the result, except for the senior, of each j-th adder (1 ≅ j ≅ m - 1) and the input of the (n + j) -th bit of the divisible device are connected to the first input corresponding bits of the (j + 1) -th adder, the second inputs of all adders are connected to the input of the device divider two, the output of the result of the mth adder is the output of the remainder of the device, the inputs of the control bits of the dividend and device divider, the input of the logical unit of the device, the outputs of the internal interdigital transfers of all adders are connected to the corresponding inputs of the first convolution node modulo two, the output of which is connected to the first input of the first comparison element, the input of the second convolution node modulo two is connected to the output of the result of the m-th adder, and the output of the second convolution node modulo two is connected to the output of the control discharge of the core a device, the input of the divider of which is connected to the input of the third convolution unit modulo two, the output of which is connected to the first input of the second comparison element, the second input of which is connected to the input of the control discharge of the device divider, the outputs of the first and second comparison elements are connected to the output of the device error indicator, the inverting input of the first adder is connected to the input of the logical unit of the device, characterized in that two nodes of the convolution modulo two are introduced into the device, the transfer output from the highest order j- of the adder is connected to the inverting input of the (j + 1) adder, the carry outputs from the high bits of all adders form a group of outputs of the private device, the carry outputs from the high bits of the first to (m - 1) th adders are connected to the input of the fourth convolution node modulo two, the output of which is connected to the fifth input of the first convolution node modulo two and to the first input of the fifth convolution node modulo two, the second input of which is connected to the transfer output from the highest bit of the m-th adder, and the output of the fifth convolution node modulo two soy dynamin with the output of the control bit of the private device, the outputs of the senior bits of the results of the first to (m - 1) th adders are connected to the first input of the sixth convolution node modulo two, the second input of which is connected to the output of the second convolution node modulo two, and the output of the sixth node convolution modulo two is connected to the second input of the first comparison element.

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