RU2017167C1 - Pulse doppler locator - Google Patents

Abstract

FIELD: radio detection and ranging. SUBSTANCE: pulse Doppler locator has five selectors 1,2,12,13,16, two NOT elements 3,14, two time- delay units 4,5, two inverters 6,15, complex number multiplier, 7, smoothing unit 8, phase computing unit 9, delay element 10, subtracter 11, integrating unit 17, thresholder 18, two storage elements 19, 21, multiplier 20, plurality of control unit 22,22-3-1-5-6-7-8-9-10-11- 12-16-20; 8-17-18-18,22-14-12; 22-13-15-16; 9-11; 1-2-4-5- 7; 4-7; 22-2; 21-20; 19-18. EFFECT: increased performance efficiency. 4 cl, 8 dwg

Description

 The invention relates to the field of radar and is intended to measure the speed of an object; It can be used in radar recognition systems, as well as in air traffic control radar stations for detecting and measuring the speed of aircraft.

 Known pulse radar with digital signal processing, consisting of series-connected ADCs, a reflection suppression circuit and a Doppler frequency processing unit, including a rectangular to polar coordinate converter, a delay unit, an adder, a polar coordinate converter to a rectangular and threshold circuit. However, this device has low accuracy and complicated implementation due to the presence of a double coordinate transformation.

 Also known is the Doppler radar for measuring speed, consisting of a series-connected Gaussian filter, two channels and a division device; each consists of a series delay line, a detector, a low-pass filter and an adder. However, this device uses a continuous signal, which does not provide high resolution radar and reduces the detection range compared with the pulsed radiation mode.

 Closest to the invention is a radar device for detecting a moving target, containing serially connected delay units, a complex number multiplier and a subtractor. However, this device has low accuracy and ambiguity of measurement due to the frequency of the probing signal.

 The aim of the invention is to improve the accuracy and the expansion of the linear limits of the uniqueness of speed measurement.

 For this, a first and second keys are added to the radar device for detecting a moving target, which contains serially connected delay units, a multiplier of the complex numbers and a subtractor, the combined inputs of which are the input of the device, the first element is NOT, the input of which is connected to the output of the control unit and is the control input the second key, and the output is the control input of the first key; the output of the second key is the input of the first delay unit, the output of which is combined with the output of the first key and is the input of the second delay unit and the second input of the complex number multiplier, the first input of which is the output of the second delay unit, and the first quadrature channel from the output of the second delay unit is connected to the input multiplier of complex numbers directly, and the second through the first inverter; the output of the complex number multiplier is the input of the averaging unit, the output of which is connected to the input of the phase calculation unit, as well as to the input of the combining unit; the output of the phase calculation unit is connected to the second input of the subtractor, to the first input of which the output of the delay element is connected, the input of which is also the output of the phase calculation unit; the subtractor output is connected to the combined inputs of the third and fourth keys, the control inputs of which are connected to the output of the control unit: the third key through the second element NOT, and the fourth key directly; in addition, the output of the fourth key is the input of the second inverter, the output of which is connected to the input of the fifth key, to which the output of the third key is also connected; the control input of the fifth key is the output of the threshold device, the first input of which is the output of the combining unit, and the second input is the output of the first memory element; the output of the fifth key is the first input of the multiplier, the second input of which is the output of the second memory element, the output of the multiplier is the output of the device.

 Distinctive features of the prototype of the proposed device are additionally introduced first, second, third, fourth, fifth keys, first and second elements NOT, delay element, first and second inverters, averaging unit, phase calculation unit, phase unit, combining unit, threshold device, first and second memory elements, multiplier, control unit and new connections between them.

 Therefore, the entire claimed combination of essential features of a technical solution is new and the device meets the criterion of "novelty."

 Newly introduced blocks are known except for the phase calculation block. In addition, the newly introduced set of relationships was not found. Thus, the device meets the criterion of "significant differences".

In FIG. 1 shows a structural electrical diagram of the proposed detector-meter of Doppler signals; figure 2 is the same block delay; figure 3 is the same, the multiplier of complex numbers; figure 4 is the same block averaging; figure 5 is the same block phase calculation; figure 6 is the same block combining; in FIG. 7 - the same, control unit; on Fig - time diagrams of the operation of the proposed device (the time diagrams U _I ¹ , U _I ⁵ , U _O ⁷ shows the signal of only one quadrature component; the digital index corresponds to the block number).

 The Doppler signal detector-meter (see Fig. 1) contains the first 1 and second 2 keys, the combined inputs of which are the input of the device, the first element is NOT 3, the input of which is connected to the output of the control unit 22 and is the control input of the second key 2, and the output is the control input of the first key 1; the output of the second key is the input of the first delay unit 4, the output of which is combined with the output of the first key and is the input of the second delay unit 5 and the second input of the complex number multiplier 7, the first input of which is the output of the second delay unit 5, the first quadrature channel from the output of the second block delay 5 is connected directly to the input of the multiplier 7 of the complex numbers, and the second through the first inverter 6. The output of the multiplier 7 of the complex numbers is the input of the averaging block 8, the output of which is connected to the input of the block 9, the phase calculation, as well as to the input of the unit 17 of the Association. The output of the phase calculation unit 9 is connected to the second input of the subtractor 11, to the first input of which the output of the delay element 10 is connected, the input of which is also the output of the phase calculation unit 9. The output of the subtractor 11 is connected to the combined inputs of the third 12 and fourth 13 keys, the control inputs of which are connected to the output of the control unit 22: the third key through the second element NOT 14, and the fourth key directly. In addition, the output of the fourth key is the input of the second inverter 15, the output of which is connected to the input of the fifth key 16, to which the output of the third key is also connected. The control input of the fifth key is the output of the threshold device 18, the first input of which is the output of the combining unit 17, and the second input is the output of the first memory element 19. The output of the fifth key is the first input of the multiplier 20, the second input of which is the output of the second memory element 21, the output of the multiplier is the output of the detector-meter of Doppler signals.

 Blocks 4 (5) of the delay (see FIG. 2) contain the first 23 and second 24 delay elements, respectively, for the signals of the first and second quadrature channels.

 The multiplier 7 of complex numbers (see Fig. 3) contains two channels I, II, each of which includes the first multiplier 25 and the second multiplier 26 and the adder 27 connected in series, the output of the first multiplier 25 is connected to the other input of the adder 27 of the other channel, and the first , the second, third, and fourth inputs of the complex number multiplier, respectively, are the first inputs of the first 25 and second 26 multipliers of each channel, the second inputs of the second multipliers, the combined second inputs of the first multipliers, and The outputs of the complex number multiplier are the outputs of the channel adders. It should be borne in mind that in the description of the device as a whole and its operation, the output of the complex number multiplier means both outputs of the quadrature channels in the aggregate, as well as the first and second inputs.

(N/2-1) элемента задержки является входом (k+1)-го, k=1

(N/2-1) элемента задержки и одновременно вторым входом k-го, k=1

(N/2-1) cумматора, выход k-го, k=1

(N/2-1) сумматора служит первым входом (k+1)-го, k= 1

(N/2-1) сумматора, выход последнего, (N/2-1)-го сумматора служит выходом каждого канала блока усреднения.Block 8 averaging (see figure 4) contains two channels, each of which consists of N / 2 - 1 delay elements 28 and N / 2 - 1 adders 29; the input of each channel a is the combined input of the 1st delay element and the first input of the 1st adder, the output of the kth, k = 1

The (N / 2-1) delay element is the input of the (k + 1) th, k = 1

(N / 2-1) delay element and at the same time the second input of the k-th, k = 1

(N / 2-1) adder, k-th output, k = 1

(N / 2-1) adder serves as the first input of the (k + 1) -th, k = 1

(N / 2-1) adder, the output of the last, (N / 2-1) -th adder serves as the output of each channel of the averaging block.

 The phase calculation unit 9 (see FIG. 5) consists of a series divider 30, an arctangent function converter 31, a modular block 32, a subtracter 33, a character assignment unit 34 and a first key 35, the first input of the divider serving as the input of the imaginary part of the complex number, the corresponding sine component of the quadrature channels, and the second input of the divider is the input of the real part of the complex number and combined with the second inputs of the first 35 and second 36 keys; the output of the arc tangent functional converter is also connected to the first input of the second key; the first input of the divider is connected to the second input of the character assignment unit; the second input of the subtractor is the output of the memory element 38; the outputs of the first and second keys are the inputs of the adder 37, the output of which is the output of the phase calculation unit.

 The combining unit 17 (see Fig. 6) includes two quadrants 39.40 and adders 41, the inputs of the combining unit being the inputs of the quadrators, the outputs of the quadrators are the inputs of the adder, the output of the adder is the output of the combining unit.

 The control unit 22 (Fig. 7) consists of a delay unit 42 and a trigger 43, wherein the input of the control unit is the combined input of the delay unit and the second input of the trigger, the output of the delay unit is the first input of the trigger, and the output of the trigger is the output of the control unit.

 The detector-meter Doppler signals works as follows.

= x_j+iy_j= u_je^i(φj^+φo⁾, (1) где φ_j=ω_д˙t_j - доплеровский сдвиг фазы на момент прихода j-го импульса, поступает на коммутатор, состоящий из первого 1 и второго 2 ключей и элемента НЕ 3, управляющих сигналом U_вых ²² с блока 22 управления. При нулевом управляющем сигнале открыт первый ключ 1, и сигнал проходит на входы второго блока 5 задержки напрямую. При единичном сигнале открыт второй ключ 2, и сигнал задерживается первым блоком 4 задержки на время ΔТ = (T₂ - T₁)/2. Таким образом, неэквидистантная последовательность квадратурных составляющих U_вх ¹ сигнала преобразуется в эквидистантную U_вх ⁵ с периодом Т_ср = (T₁ + T₂)/2. Далее эта последовательность поступает на второй блок задержки 5 на время Т_ср, после чего составляющая, соответствующая мнимой части комплексного числа (синусной составляющей квадратурных каналов), дополнительно поступает на первый инвертор 3 с целью осуществления комплексного сопряжения. Далее в умножителе 7 комплексных чисел осуществляется обработка отсчетов в соответствии с алгоритмом:

x_j-1-y_j-1x_j)= где - Δφ_j= φ_j-φ_j-1= ω_д(t_j-t_j-1)=

-набег фазы за время между соседними отраженными импульсами.The sequence of quadrature components of the sum of the signal and noise U _in ¹ , followed by a wobble of the repetition period (T ₁ , T ₂ ), described in a single element of range resolution by a sequence of complex quantities:

= x _j + iy _j = u _j e ^{i (φ} j ^{+ φ} o ⁾ , (1) where φ _j = ω _д ˙t _j is the Doppler phase shift at the moment of arrival of the jth pulse, it arrives at the switch, consisting of the first 1 and the second 2 keys and the element NOT 3, controlling the signal U _o ²² from the control unit 22. With a zero control signal, the first key 1 is open, and the signal passes directly to the inputs of the second delay unit 5. With a single signal, the second key 2 is open, and the signal is delayed by the first delay unit 4 for the time ΔТ = (T ₂ - T ₁ ) / 2. Thus, not equidistant sequence quadrature components U _Rin ¹ signal is converted into equidistant _Rin ⁵ U of period T _cp = (T ₁ + T ₂₎ / 2. Further, this sequence is supplied to the second delay unit 5 for the time T _cf. After which the component corresponding to the imaginary part of the complex number (sine component of the quadrature channels) is additionally supplied to the first inverter 3 in order to perform complex coupling. Next, in the multiplier of 7 complex numbers, the samples are processed in accordance with the algorithm:

x _j-1 -y _j-1 x _j ) = where - Δφ _j = φ _j -φ _j-1 = ω _d (t _j -t _j-1 ) =

- phase delay during the time between adjacent reflected pulses.

x_2k+1+y_2k-1·y_2k+1=U cos

,

, (3) а через период Т_ср величины

,

, (4) где Δ φ^I _{2 n-1}=ω_д T₁,Δ φ_2n ^I=ω_д T₂- усредненные доплеровские набеги фазы.From the output of the multiplier 7 of complex numbers, the samples U _o ⁷ are fed to the averaging unit 8, which uses two channels, each of which contains N / 2-1 delay elements 28 for a time of 2T _cp = T ₁ + T ₂ and N / 2-1 adders 29, sliding along the azimuth periodically summing the even and odd samples, respectively. At the output of block averaging 8, according to the described principle of operation, values are formed
a

x _{2k + 1} + y _2k-1 · y _{2k + 1} = U cos

,

, (3) and after a period T _cf

,

, (4) where Δ φ ^I _{2 n-1} = ω _d T ₁ , Δ φ _2n ^I = ω _d T ₂ are the average Doppler phase incursions.

=arctg(b_j/a_j), имеющая интервал однозначности [- π/2; π/2]. Последующие преобразования величины

с целью расширения этого интервала определяются знаком величины а_j, пропорциональной косинусу исходного угла

. При aj ≥0 открыт второй ключ 36 и величина

через сумматор 37 непосредственно поступает на выход блока 9 вычисления фазы. При a_j < 0 открыт первый ключ 35, а второй ключ 36 закрыт. При этом в модульном блоке 32 образуется , вычитываемый в вычитателе 33 из величины π, поступающей из элемента 38 памяти. Полученной разности в блоке 34 присваивается знак величины b_j, пропорциональный синусу исходного угла. Рассмотренные операции позволяют расширить диапазон однозначного измерения до интервала [- π; π], т.е. получить на выходе сумматора 37 оценку усредненного по N отсчетам доплеровского сдвига фазы помехи в виде

_при

На выходе блока 9 вычисления фазы образуются величины

=ω_дT₁ и следующие через период Т_ср величины

= ω_дT₂ .The values of a _j and b _j are supplied to the corresponding inputs of the phase calculation unit 9 (see FIG. 5), in which the estimate is determined using the divider 30 and the arctangent functional converter 31

= arctan (b _j / a _j ) having an unambiguity interval [- π / 2; π / 2]. Subsequent Conversions

in order to expand this interval, they are determined by the sign of the quantity a _j proportional to the cosine of the initial angle

. For aj ≥0, the second key 36 is open and the quantity

through the adder 37 directly goes to the output of the phase calculation unit 9. When a _j <0, the first key 35 is open, and the second key 36 is closed. Thus in the modular block 32 is formed subtracted in the subtractor 33 from the value of π coming from the element 38 of the memory. The resulting difference in block 34 is assigned the sign of the quantity b _j proportional to the sine of the original angle. The operations considered allow us to expand the range of unambiguous measurements to the interval [- π; π], ie get at the output of adder 37 an estimate of the averaged over N samples Doppler phase shift of the interference in the form

_at

At the output of phase calculation unit 9, values are formed

= ω _d T ₁ and the following values through the period T _cf

= ω _d T ₂ .

(а через период

) вычитается в блоке 11 вычитания из следующей за ней величины

(через период -

); получаемая величина U_вых ¹¹

=

-

(через период -

=

-

поступает на коммутатор, состоящий из третьего 12 и четвертого 13 ключей и элемента НЕ 14. При нулевом выходном сигнале блока 22 управления U_вых ²² открыт третий ключ 12, и величины

=

-

проходит на вход пятого ключа 16 напрямую, при этом четвертый ключ 13 закрыт. При единичном сигнале блока 22 управления третий ключ 12 закрыт, а четвертый ключ 13 открыт, и величина

=

-

инвертируется вторым инвертором 15 и также поступает на пятый ключ 16.Passing through the delay element 10, the value

(and after a period

) is subtracted in block 11 subtracting from the next value

(through the period -

); the resulting value U _out ¹¹

=

-

(through the period -

=

-

arrives at the switch, consisting of the third 12 and fourth 13 keys and the element NOT 14. With a zero output signal of the control unit 22 U _out ²² open the third key 12, and the values

=

-

passes to the input of the fifth key 16 directly, while the fourth key 13 is closed. With a single signal of the control unit 22, the third key 12 is closed, and the fourth key 13 is open, and the value

=

-

is inverted by the second inverter 15 and also enters the fifth key 16.

через пятый ключ 16. В противном случае ключ 16 разомкнут, на выходе перемножителя 20 имеем сигнал U_вых ¹⁶.In order to exclude the possible operation of the device by noise, a detection circuit has been introduced into it, which blocks the issuance of an output estimate in the absence of a reflected signal. From the outputs of block 8, the averaging of the quantity and arrives at the input of block 17 of the association, where in accordance with its structure, the square of the module of the input quantity U = a _j ² + b _j ^{2 is} calculated. If this value is exceeded over the value of the threshold U of the _pores embedded in the memory element 19, then the output signal of the threshold device 18 receives a permission signal for passing the calculation result

through the fifth key 16. Otherwise, the key 16 is open, at the output of the multiplier 20 we have a signal U _out ¹⁶ .

, пройдя через ключ 16, умножается на величину K = c/[4πf_o(T₂ - T₁)], где с - скорость света; f_o - несущая частота излучаемых радиоимпульсов, записанная в элементе 21 памяти. На выходе перемножителя 20 образуется величина, пропорциональная скорости цели.Value

having passed through the key 16, it is multiplied by the value K = c / [4πf _o (T ₂ - T ₁ )], where c is the speed of light; f _o - carrier frequency of the emitted radio pulses recorded in the memory element 21. At the output of the multiplier 20, a value is formed proportional to the speed of the target.

The input of the control unit 22 (see Fig. 7) receives pulses of the transmitter synchronizer with a repetition period of 2T _sr and resets the trigger 43 to the zero state; the same signal, delayed in the delay element 42 for a time T _cf , sets the output of the trigger 43 unit. The signals generated by trigger 43 control the operation of the first 1, second 2, third 12, and fourth 13 keys.

 The effectiveness of the proposed detector-meter of Doppler signals is to increase accuracy by averaging and expanding the limits of linear velocity measurement by introducing signals with a wobble of the repetition period.

For example, when using a conventional periodic probing signal for detection at a maximum range of R _max = 200 km, the repetition period should be at least T = 2R _max / c = 1333 μs, while the unambiguously measured speed v _rmax (i.e., satisfying the inequality ω _d T = (4πv _rmax / λ) T <π) for the wavelength λ = 10 cm, v _rmax = λ / 4T = 18.75 m / s is determined.

With the introduction of a wobble period of the repetition of the probe signal, it becomes possible to expand the limits of a single measurement; for example, to measure the velocity v _rmax = 2M = 660 m / s at a wavelength of λ = 10 cm, the wobble value can be calculated as
ΔT = λ / 4v _rmax = 0.1 / 4x660 = 37.9 μs
Thus, with the same unambiguously measured range R _max = 200 km, the interval of the unambiguously measured speed during the wobble of the repetition period at λ = 10 cm with parameters T ₁ = 1333 μs, T ₂ = 1371 μs expands ΔT / T times.

Claims (5)

 1. DOPPLER SIGNAL DETECTOR-METER, comprising the first and second delay units, the first and second outputs of the first delay unit are connected to the first and second inputs of the complex number multiplier, to the third input of which the first output of the second delay unit is connected, and a subtracter, characterized in that the first and second keys are introduced, the inputs of which are combined and are the inputs of the detector-meter, the control unit, the first element NOT, the averaging unit connected in series, the phase calculation unit and the delay element, the output is connected to the first input of the subtractor, the second input of which is connected to the output of the phase calculation unit, the third key, the fifth key and the multiplier connected in series, the output of which is the output of the detector-meter, the combining unit and the threshold block, the output of which is connected to the control input of the fifth key, the first inverter, the first and second memory elements and the fourth key and the second inverter in series, the output of which is connected to the input of the fifth key, the output of the control unit connected to the control inputs of the second and fourth keys directly, and to the control inputs of the first and third keys through the first and second elements NOT, respectively, the second output of the second delay unit is connected to the fourth input of the complex number multiplier through the first inverter, the outputs of the complex number multiplier are connected to the inputs of the block averaging, the outputs of which are connected to the inputs of the combining unit, the output of the subtractor is connected to the input of the third and fourth keys, the outputs of the first and second keys are connected to the inputs respectively, first and second delay units, and outputs of the first and second memory elements are connected to second inputs respectively and a threshold multiplier unit.  2. The detector-meter according to claim 1, characterized in that the averaging unit contains two channels, each of which consists of N / 2 - 1 delay elements connected in series N / 2 - 1 adders connected in series, the combined input of the first delay element and the first the input of the first adder is the input of each channel and the corresponding input of the averaging unit, and the output of each of N / 2 - 1 delay elements is connected to the second input of the same name from N / 2 - 1 adders, the output of the last adder is the output of the channel and correspondingly m output unit averaging.  3. The detector-meter according to claim 1, characterized in that the phase calculation unit comprises a series-connected divider, an arctangent functional converter, a module calculation unit, a subtractor, a character assignment unit, a first key and an adder, a memory element and a second key, the first input of the divider combined with the second input of the character assignment unit and is the first input of the phase calculation unit, the second input of which are the second inputs of the divider and the first and second keys connected together, the output of the functional transform To arctangent connected to the first input of the second switch, whose output is connected to a second input of the adder whose output is the output of the phase calculation unit.  4. The detector-meter according to claim 1, characterized in that the combining unit contains two quadrators, the inputs of which are inputs of the combining unit, and the outputs are connected to the inputs of the adder, the output of which is the output of the combining unit.  5. The detector-meter according to claim 1, characterized in that the control unit comprises a delay unit and a trigger connected in series, the output of which is the output of the control unit, the input of which is the input of the delay unit and the second input of the trigger.

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