RU2010318C1 - Memory control unit - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: memory control unit has central control unit, bus former, unit for mating with on-line storage, data address control unit, which has address register, two decoders, physical address storage, recording unit, two control units. Data address sing control unit, data buffer memory control unit, data buffer memory are brought into the device additionally. Data address control units has two bus formers, ageing unit, substitution unit, read-out and comparison unit, two registers, two multiplexers, unit of AND gates, adder, read-out unit. Data address sing control unit has data register, read-out/record and comparison unit, control unit, storage, substitution unit, modulo 2 adder, address register, column number decoder, line number decoder, control unit. EFFECT: improved efficiency. 52 dwg

Description

 The invention relates to computer technology, and in particular to computer control devices, and can be used in the design of the memory of a computer system.

 In FIG. 1 is a block diagram of a memory management device; in FIG. 2 - data address management unit; in FIG. 3 - control unit address signs of data; in FIG. 4 - control unit buffer data memory; in FIG. 5 - central control unit; in FIG. 6 - block interface with RAM; in FIG. 7 - the first control unit; in FIG. 8 is a circuit diagram of a first bus driver; in FIG. 9 - electrical system of the aging and replacement unit; in FIG. 10 - block reading and comparison; in FIG. 11 is an electrical diagram of a readout unit of a priority sign; in FIG. 12 is an electrical diagram of a reading unit with a comparison of a significance bit; in FIG. 13 is an electrical diagram of a read and compare node for one bit of a mathematical address; in FIG. 14 - drive mathematical addresses; in FIG. 15 is an electrical diagram of a priority attribute memory cell; in FIG. 16 electric circuit of a memory cell of a bit of significance; in FIG. 17 is a circuit diagram of a memory cell for the upper digits of the mathematical address; in FIG. 18 is a recording unit; in FIG. 19 is an electrical diagram of a recording unit for storing physical and mathematical addresses for one bit; in FIG. 20 is an electrical diagram of a recording unit of one bit of the priority attribute field in the mathematical address storage; in FIG. 21 is an electrical diagram of a recording unit for one bit in a physical address storage device; in FIG. 22 is a circuit diagram of one discharge of the first multiplexer; in FIG. 23 - reading unit; in FIG. 24 is a circuit diagram of a reading unit of a discharge of a physical address storage device with two antiphase outputs; in FIG. 25 is an electrical diagram of one bit of a read node of a physical address storage device; in FIG. 26 - drive physical addresses; in FIG. 27 - second control unit; in FIG. 28 - structure of the address of access to the drive mathematical or physical addresses; in FIG. 29 - line drive mathematical addresses; in FIG. 30 - line drive physical addresses; in FIG. 31 - line drive address tag data; in FIG. 32 - the formation of the address of the address in the drive address signs of data; in FIG. 33 - structure of the mathematical address for the mode without zeroing - bits; in FIG. 34 is an electrical diagram of a signal conditioner; in FIG. 35 is a circuit diagram of an amplifier-driver of control signals; in FIG. 36 is a circuit diagram of a shaper of a temporary signal for fetching a row; in FIG. 37 - electrical circuit of the amplifier-former; in FIG. 38 - adder; in FIG. 39 - four-digit section of the adder; in FIG. 40 - four-digit section of the adder for two input operands with input transfer; in FIG. 41 - four-digit section of the adder with one operand, with a multiplexer at the input of the operand and with input transfer; in FIG. 42 is an electrical diagram of a four-bit accelerated transfer section with transfer generation; in FIG. 43 is an electrical diagram of a four-bit accelerated transfer projection; in FIG. 44 - one-bit section of the adder with one operand with a multiplexer at the input of the first operand and with input transfer; in FIG. 45 is a circuit diagram of a single-bit adder section for two operands; in FIG. 46 is a circuit diagram of a single-bit adder of two input operands for the least significant bit; in FIG. 47 is a circuit diagram of a one-bit adder section; in FIG. 48 is a circuit diagram of a one-bit adder section with one input operand and input transfer; in FIG. 49 is an electrical diagram of one discharge of a bus driver; in FIG. 50 is an electrical diagram of an addition unit modulo two; in FIG. 51 is an electrical diagram of a data buffer memory; in FIG. 52 - control unit of the interface unit with RAM.

 In FIG. 4-52 shows an example of the implementation of a memory management device made on CMOS transistors with four-column drives of mathematical and physical addresses and address tags, with a buffer memory consisting of CMOS LSI with 2Kx8 organization, 16KB capacity, which is part of the microprocessor system.

 The memory management device comprises a bus driver 1, a data address management unit 2, an address feature data control unit 3, a data buffer memory control unit 4, a data buffer memory 5, a central control unit 6, a memory interface unit 7, a bi-directional information bus 8 addresses -data, bi-directional address-information bus 9, input zero, input control bus 11 of the address strobe and data strobe, input control bus 12 "Readiness of RAM", output control conductive bus 13 "Data Ready" output interrupt control bus 14, output bus 15 commands output bus 16.

 The bus driver 1 has first and second inputs / outputs 17-1, 17-2 of the data address, a control input.

 The data address management unit 2 has an input-output of data addresses, a control input 18-1, a zero-setting input 18-2, a synchronization input 18-3, a control output.

 Unit 3 control address signs of data has an input-output address data, control input, zero input, control output 19-1 of the sign of readiness, address output 19-2, control output 19-3.

 The buffer data memory control unit 4 has an address input 20-1, a control input 20-2, a synchronization input 20-3, a ready sign of control output 21-1, a control output 21-2, address output 21-3.

 The buffer memory 5 data has a control input 22-1, address input 22-2, input-output addresses data.

 The central control unit 6 has an input / output of data addresses, an input 23-1 of an address strobe and a data strobe, a synchronization input 23-2, a control input 23-3 of the availability indicators, a control input 23-4, a control input 23-5, an output 24 -1 data availability, control output 24-2, output 24-3 of the address strobe and data strobe, control output of 24-4 interrupts.

 The memory interface unit 7 has an input-output 25-1 of data addresses, an address-information input-output 25-2, a control input 26-1 "Ready memory", an input 26-2 of the address strobe and data strobe, input 26 -3 zero settings, command output 27-1, control output 27-2 "Start RAM", control output 27-3 signs of readiness.

 The device has a bi-directional local bus 28 data-address, control bus 29, control bus 30 signs of availability.

 The data address management unit contains (Fig. 2) a first control unit 31, a first bus driver 32, an aging and replacement unit 33, a read and compare unit 34, a mathematical address storage 35, an address register 36, a first decryptor 37 lines, a write unit 38, two registers 39, 40, the first multiplexer 41, the block of And elements 42, the second multiplexer 43, the second bus driver 44, the adder 45, the read unit 46, the drive 47 physical addresses, the second control unit 48, the second decoder 49 lines. The first control unit 31 has a control input 50-1, an address input 50-2, a synchronization input 50-3, a column selection control input 50-4, a comparison feature input 50-5, an address input 50-6, the first and second control inputs 51 -1 and 51-2, output 51-3 signs of comparison. The bus driver 32 has an input of data addresses, a control input, an output of data addresses. The aging and replacement unit 33 has a data input 52-1, a comparison feature input 52-2, a control input 52-3, a control output, a data output. The reading and comparing unit 34 has first and second inputs 53-1 and 53-2 of data addresses, a control input 53-3, output 54-1 of data addresses, and output 54-2 of comparison signs. The drive 35 mathematical addresses has the address input of the row selection, the input zero, the input-output of the address data. The address register 36 has an address input, a control output, an output. The first line decoder 37 has an address input, a control input, an address output of a row sample. The recording unit 38 has a first control input 55-1, a data input 55-2, a second control input 55-3, a data address 55-4 input, first and second data address 56-1 and 56-2 outputs. The first register 39 has a data-address input, a control input, an output. The second register 40 has a data-address input, a control input, an output. The first multiplexer 41 has first and second inputs 57-1 and 57-2 of the data address, control input 57-3, the output 58-1 of the data address, the output 58-2 of the data. Block 42 elements And has a first and second address inputs 59-1 and 59-2, output. The second multiplexer 43 has an input 60-1 of data addresses, an address input 60-2, a control input 60-3, an address output. The bus driver 44 has a data address input, a control input, an address data output. The adder 45 has first and second outputs 61-1 and 61-2 of the address data, address input 61-3, control input 61-4, the output of address data. The reading unit 46 has an input of data addresses, a control input, an output of data addresses. The reading unit 46 has an input of data addresses, a control input, an output of data addresses. The drive 47 of physical addresses has an address input of a row selection, input-output of data addresses. The second control unit 48 has a data input 62-1, a control input 62-2, a column sample control input 62-3, a synchronization input 62-4, an address input 62-5, a comparison feature input 62-6, the first and second control outputs 63 -1 and 63-2. The second decoder 49 has an address input, a control input, an address output of a row sample.

 The control unit of addressable features of the data contains (Fig. 3) a data register 64, a read-write and compare unit 65, a control unit 66, a drive 67, a replacement unit 68, an addition module 69, an address register 70, a column number decoder 71, decoder 72 line numbers, node 73 control. The data register 64 has a data input, a control input, a data output. The read-write and comparison unit 65 has a data input-output, data input 74-1, address input 74-2 of the column number sample, control input 74-3, output 75-1 of comparison signs, data output 75-2, control output 75 -3, output 75-4 signs of readiness, information output 75-5. The control unit 66 has a data input, a control input, an output. The drive 67 has an input-output data, input zero, the address input of the sample line number. Block 68 substitution has an input 76-1 signs of comparison, information input 76-2, control input 76-3, address output. Block 69 addition modulo two has an address input, control input, output. Register 70 addresses has the first and second address inputs 77-1 and 77-2, control input 77-3, output. The column number decoder 71 has a first and second address inputs 78-1 and 78-2, a control input 78-3, an address output of a column number sample. The decoder 72 line numbers has an address input, a control input, an address output of a line sample. The control unit 73 has a synchronization input, a control input, an output. In the block there is a local bus 79 data-address, control bus 80.

 The buffer data memory control unit contains (Fig. 4) two AND-NOT elements 81-1, 81-2, element 3I 82, element HE 83, counter 84, two registers 85-1, 85-2, two 2AND-OR elements -NOT 86-1, 86-2, trigger 87, three elements 2-2I-OR-NOT 88-1, 88-2, 88-3, element 89, nine formers 90-1 - 90-9.

 The central control unit contains (Fig. 5) an input register 91, a command register 92, an address register 93, two state registers 94-1, 94-2, a command decoder 95, an address decoder 96, two bus former 97-1, 97-2 , encoder 98 states, five encoders 99-1 - 99-5, two output registers 100-1, 100-2, seven shapers 101-1 - 101-7.

 The RAM interface unit (Fig. 6) contains an input register 102, a parity checker 103, a write register 104, an address-data bus amplifier 105, an instruction bus amplifier-driver 106, an output register 107, an instruction-read data register 108, control unit 109.

 The first control unit contains (Fig. 7) a column number selection decoder 110, two elements HE 111-1, 111-2, a two-input column number multiplexer 112, a temporal gating unit 113 of a selected column, a driver amplifier 114 of the column reading signals, four shapers 115 -1 - 115-4 signals for comparing mathematical addresses, the first driver 116 of the control signal, the first driver 117 of the comparison signs, the amplifier-driver 118 of the recording signals of the column, the second and third amplifiers-drivers 119 and 120 of the control signals, the second Shaper 121 signs of comparison.

 The first bus driver contains (Fig. 8) thirty-two discharges of the amplifiers-shapers 122-1 - 122-32.

 The aging and replacement unit contains (Fig. 9) a node 123 for forming line priority signs, a register for storing signs 124, a node 125 for generating the number of the replaced column, a register 126 for storing the number of the replaced column.

 The reading and comparing unit contains (Fig. 10) six nodes 127-1 - 127-6 of reading bits of priority signs, a node 128 of reading with a comparison of the significance bit, eighteen nodes 129-1 - 129-18 of reading and comparing bits of a mathematical address.

 The reading unit with the comparison of the sign of significance of the signs contains (Fig. 12) two CMOS transistors 130-1, 130-2 p-type, element NOT 131, four cells 132-1 - 132-4 reading and comparing bits of mathematical addresses.

 The cell for reading and comparing bits of mathematical addresses contains (Fig. 13) a dynamic element 133 for controlling output information, a four-input switch 134 of a selected column, a bit of register 135 of an address, four elements 136-1 to 136-4 of addition modulo two, eight inverters 137-1 - 137-8 information amplification for the read discharge, four recovery elements 138-1 to 138-4, four column state control elements 139-1 to 139-4.

 The accumulator of mathematical addresses contains (Fig. 14) sixteen vertical lines, each of which consists of six cells 140-1 - 140-6 signs of priority, cells 141 bits of significance, eighteen cells 142-1 - 142-18 senior bits of the mathematical address.

 The recording unit contains (Fig. 18) four nodes 143-1 - 143-4 entries in the physical address accumulator, six nodes 144-1 - 144-6 records of the priority attribute field in the mathematical address accumulator, fifteen nodes 145-1 - 145-15 records in drives of physical and mathematical addresses, five nodes 146-1 - 146-5 records in the drive of mathematical addresses.

 The recording unit in the physical and mathematical address stores (Fig. 19) contains four elements 147-1 - 147-4 entries in the physical address store, four elements 148-1 - 148-4 entries in the mathematical address storage, two elements NOT 149-1 , 149-2.

 The recording node for one bit of the priority attribute field in the mathematical address accumulator contains (Fig. 20) four elements 150-1 to 150-4 entries in the physical address accumulator, element 151 for writing in the priority attribute category, two elements NOT 152-1, 152- 2.

 The recording unit for one bit in the physical address accumulator contains (Fig. 21) four elements 153-1 - 153-4 of the record in the physical address accumulator, two elements NOT 154-1, 154-2.

 The recording unit for one bit in the mathematical addresses accumulator is made in the same way as the recording unit in the physical addresses accumulator.

 The reading unit contains eleven nodes 155-1 - 155-11 of reading bits of the physical address accumulator in the forward code, fourteen nodes 156-1 - 156-14 of reading bits of the physical address storage device in the forward and reverse code.

 The reading unit of one bit of the physical address storage device in the forward and reverse code contains (Fig. 24) three CMOS transistors 157-1 - 157-3, two elements NOT 158-1, 158-2, four elements 159-1 - 159-4 read bits.

 The node for reading the digits of the drive of physical addresses in the direct code contains (Fig. 25) two CMOS transistors 160-1, 160-2, the element NOT 161, four elements 162-1 to 162-4 for reading the digits.

 The physical address accumulator contains (Fig. 26) sixteen vertical lines, each of which consists of twenty-five memory cells 163-1 - 163-25.

 The second control unit contains (Fig. 27) a driver 164 of the column reading signal, a driver 165 of a temporary signal for reading the drive, a driver 166 of a temporary signal for selecting a line, a decoder 167, eight multiplexers 169-1 - 169-8, four amplifier-shaper 170-1 - 170-4 read the columns of the drive, the shaper 171 address signs, four amplifier-shaper 172-1 - 172-4 write the columns of the drive, the shaper 173 temporary signal control write to the column, shaper 174 temporary signal read columns, node 175 amplifier-amplifiers of control signals, node 176 of signal conditioners.

 The adder contains (Fig. 38) a one-bit section 177 adder, four-bit section 178, two four-bit sections 179-1, 179-2 adders for two operands with input transfer, three four-bit sections 180-1 - 180-3 adder with one input operand, input transfer and input multiplexer, single-bit adder section 181 with one input operand and input transfer.

 The four-digit adder section contains (Fig. 39) a low-order single-bit adder 182 for two input operands, three single-bit adders 183-1 - 183-3 with multiplexing for the first operand and input transfer, an accelerated transfer section 184 for four bits.

 The four-bit section of the adder for two operands with input transfer contains (Fig. 40) four one-bit sections 185-1 - 185-4 of the adder for two operands, four-bit section 186 of the through transfer.

 The four-bit adder section with one operand, input transfer and input multiplexer contains (Fig. 41) four one-bit adder sections 187-1 - 187-4 with one input operand, input transfer and input multiplexer, four-bit accelerated transfer section 188.

 One bit of the bus driver has two input-output addresses of data addresses 17-1, 17-2, a control input connected to the control bus 29, and on the bus 29-1, write control signals from the local bus, on the bus, on the bus 29- 2 - a control signal for reading from a local bus, on a bus 29-3 - a control signal for the output driver to the address-data bus, on a bus 29-4 - a control signal for issuing to a local bus.

 The modulo-two addition unit contains (Fig. 50) the element NOT 189, the AND-NOT element 190, the seven modulo-two addition elements 191-1 to 191-7.

 The buffer data memory contains (Fig. 51) five memory elements 192-1 through 192-5.

 The control unit for the RAM interface unit contains a command register 193, an address register 194, an instruction decoder 195, an address decoder 196, a gating element 197, a memory response trigger 198, a ready response trigger 199, a memory module request unit 200, two AND 201-1 elements, 201-2.

 The bus driver 1 is connected by the first input-output 17-1 of the data address to the bidirectional information bus 8 of the data address address, which is also connected to the input-output of the buffer data memory 5 and to the first input-output of the data address of the memory interface unit 7. The second input-output 17-2 of the data addresses of the bus driver 1 is connected to the same inputs and outputs of the data address control unit 2, the address data tag control unit 3 and the data address input-outputs of the central control unit 6. The input 10 of setting the device’s zero is connected to the corresponding inputs of blocks 2, 3, 7. The input control bus 11 of the address strobe and data strobe, the output control bus 13 “Data availability” and the output bus 14 of the device interrupt are connected to the input and outputs of the unit of the same name 6. Control the input 23-3 of block 6 is connected to the control output 27-3 of the sign of readiness of block 7. The control input 23-4 of the signs of readiness of block 6 is connected by bus 30 to the output of block 2 and to control outputs 19-1, 21-1 of the readiness signs of blocks 3 and 4. Control input 23-5 block 6 soy Din with the same output of block 3. The control output 24-2 of block 6 by bus 29 is connected to the control inputs of the bus driver 1 and block 3, to the inputs 18-1, 20-2 of blocks 2 and 4. Output 24-3 of the address strobe and data strobe block 6 is connected to the same input of block 7. The address output 19-2 of block 3 is connected to the address input of block 4. The control and address outputs 21-2 and 21-3 are connected to the corresponding inputs 22-1 and 22-2 of the data buffer 5. Address-information input-output 25-2 of block 7 is connected to a bi-directional address-information bus 9 of the device. Control input 26-1 "Ready RAM", command output 27-1, output 27-2 "Start RAM" block 7 are connected to the corresponding buses 12, 15, 16 of the device.

 The input-output of the address-data of block 2 by the local address-data bus is connected to the first input 53-1 of the address-data of block 34, with the address input of the address register 36, with the input of 55-4 address-data of the write block 38, with the inputs of address-data the first and second registers 39 and 40, with the outputs of the address data of the bus drivers 32, 44. The output of the address register 36 is connected to the address inputs of the first and second decoders 37 and 49, to the second address input 59-2 of the block of 42 And elements, to the address input 60-1 of the second multiplexer 43, to the address inputs 50-2 and 62-5 of the first and second blocks of the unitary enterprise ION. The address outputs of the sample line decoders 37, 49 are connected to the inputs of the same name drives 35 and 47, respectively. The input-output of the data address of the drive 35 is connected to the second input 53-2 of the data address of the unit 34 and to the first output 56-1 of the data address of the recording unit 38. The input-output of the data address of the drive 47 is connected to the input of the data address of the block 46 and to the second output 56-2 of the data address of the recording unit 38. The output 54-1 of the data address of the block 34 is connected to the input 52-1 of the data of the block 33 and to the input of the address data of the bus driver 32. The output 54-2 of the comparison signs of the block 34 is connected to the same input of the first control unit 31, the output 51-3 of the signs comparison which is connected to the inputs of the same name 52-2 and 62-6 blocks 33 and 48, respectively. The control output of the block 33 is connected to the inputs 50-4 and 62-3 of the sampling control column of the control blocks 31 and 48, respectively. The data output of the unit 33 is connected to the input 55-2 of the data of the recording unit 38. The second output 56-2 of the data address of block 38 is connected to the same input of the block 46. The outputs of the first and second registers 39 and 40 are connected respectively to the first and second inputs 57-1 and 57-2 of the first multiplexer 41, the output 58-1 of the data address which is connected to the first input 61-1 of the data address of the adder 45 and to the first address input 59-1 of the block 42 of the elements I. The output 58-2 of the data of the first multiplexer 41 and the output of the block 46 are connected by a data bus to the same input 62-1 of the second block 48 management. The output of the block of elements 42 And is connected to the address input 60-2 of the second multiplexer 43. The output of the second multiplexer 43 is connected to the address input 61-3 of the adder 45, the second input 61-2 of the address data of which is connected to the output of the block 46. The first control output 51- 1 of the first control unit 31 is connected to the control inputs of the bus driver 32, blocks 33, 34, address register 36, the first decoder 37, to the first control input 55-1 of the block 38. The first control output 63-1 of the second control unit 48 is connected to the control inputs first and second registers 39 and 40, the first and second multiplexers 41 and 43, the bus driver 44, the adder 45, the physical address reading unit 46, the second decoder 49 and the second control input 55-3 of the block 38. The second control inputs 51-3, 63-2 of the first and the second control units 31 and 48 are connected to the control output of block 2. The data input of the data register 64, the address input of the addition unit 69 are modulo two, the first address input 77-1 of the address register 70, the data output 75-2 of the read-write unit 65 and comparisons are connected by a local bus 79 data-addresses to the input-output of data-addresses x block 3 control address data tags. The data output of the register 64 is connected to the data input of the block 65, the output of the comparison signs 75-1 and the information output 75-5 of which are connected to the corresponding inputs of the substitution node 68. The data input-output of block 65 is connected to the data input-output of drive 67. Control output 75-3 of block 65 is connected through control node 66 to control output 19-3 of block 3. The output 75-4 of the readiness signs of block 65 is connected to control output 19- 1 signs of readiness of block 3. The second address input 77-2 of the address register 70 is connected to the output of block 69. The output of register 7, the address is connected to the first address input 78-1 of the decoder 71, with the address input of the decoder 72 and is the address output 19-2 of the block 3. The second address input 78-2 of the decoder 71 is connected to the output node 68 substitution. The output of the decoder 71 is connected to the address input 74-2 of the sample number of the column block 65. The output of the decoder 72 is connected to the address input of the sample of the line number of the drive 67. The control inputs of the block 69 and the control unit 73 are connected to the control inputs of the block 3. The output of the control unit 73 is connected to control inputs of registers 64, 70, block 65, decoders 71, 72, node 68 substitution. The output of the zero setting of the drive 67 is connected to the input of the same block 3.

 The device operates as follows.

 When the processor executes the memory operation command, the command code and the address, followed by the address strobe A on bus 11, are received in the data memory control device via the data address bus 8. The address is recorded in the address registers located in blocks 2, 3 (Fig. 1).

 By analyzing the bits of the address, one of the following possible types of access is determined: in the data buffer memory, in RAM, in external registers.

 As external registers can be used as internal registers of the control device buffer data memory, and not related to this device (external to blocks 2, 3) registers. Further, the operation of blocks 1-7 is considered on the example of implementation in a specific microprocessor system. The decision about which data memory buffer or operational should be accessed is made based on whether there is data in the buffer. If the incoming address is mathematical (the five most significant bits of the address in the address register are not equal to zero), it must be converted to physical using the page table. For each user task, the operating system creates its own page table (TSP) and a common page table for all tasks of the operating system (TSS). The page table (TSS or TSP) is multilevel, in block 2 there is a first-level table in drives 35 and 47 (Fig. 2), the field structure of one row of the table for mathematical and physical addresses is shown in Fig. 29 and 30, respectively.

 The eighteen most significant bits of the address of the register 36 31:18 coming from the processor are compared with the corresponding bits of the line specified in the register 36 [13: 4] (Fig. 29) of the drive 35, and the thirteenth bit of the address register with the significance bit v of the selected line . If the above categories coincide, that is, the correspondence of the mathematical and physical addresses is found, the line priority values in the table are “rejuvenated”, that is, a new line is written to the sign storage register 124 in the aging unit 33 (LRU, Fig. 29), consisting of six bits, which, according to the signal for recording the bits of block 33 at the input 55-1, is written to the string of drive 35, the number of which is set by four bits 13: 4 of register 36. Since in this implementation, drives 35 and 47 are made in a four-column scheme, aging lines occurs within four columns for each row, regardless of the number of a particular row. If the comparison of addresses for one of the columns occurred, then the comparison signal from the output 54-2 coming through block 31 to the reading block 46 (Fig. 2), the bits of the physical address (0-26) go to the adder 45 (Fig. 2) , 28-1 bit - to block 6 through block 48. The full physical address of the memory access is formed by adding 27 bits of the address with an offset, that is, an address inside the page that is in the ten least significant bits of register 36 [9: 10] and gets to the second input of the adder 45. In block 6, the knowledge of the 28th bit (bit modification M) is analyzed. If it is equal to zero, then if data was written in a command from the processor, this was the first record and an interrupt is generated in the processor. As a result of the software processing of the excess, a single value of bit M is put down in this line, which allows not to go out in the future when accessing the branch of processing the excess. If there is no data in the buffer (for reading commands), which is checked in parallel with the actions to convert the address, then the physical address received in the adder through the former 44 goes to the local bus 28 and through block 1 to the bus 8 (Fig. 1).

 If in all four columns of drive 35 (Fig. 2) there was no comparison and the data is not in the data buffer 5, a new row of the page table will be pumped out from the main memory (page table of the second level) using block 4. The address of the line is determined by the sum two operands, the first of which is selected at the first input of the first operand of the adder 45 at input 61-1, where the address of the beginning of the TCC or TSP page table is supplied. Previously, the addresses in the registers 39 and 40 are recorded by the write commands in the external register in block 2 (Fig. 1). The register is selected on the basis of the "system-user" attribute in multiplexer 41. The attribute is supplied at input 62-5 to block 48 and from it in the form of a strobe at input 57-3 to multiplexer 41. The value at the second input of adder 45 is formed by combining two fields, in bits 1-7 of the second operand of the adder 45 are placed bits 10-16 of the register 36 addresses, which contains the minimum size of the page table. The digits 8-12 of the input of the adder 45 (i.e., expanding to the maximum size of the page table) are formed by superimposing a five-digit mask on five bits of the address register 36, i.e., by a logical product in block 42 (Fig. 2) of the bits 17-21 of the register 36 addresses for five digits of the mask, which is formed by the five senior digits located in registers 39 and 40, selected by the "system-user" attribute at input 57-3. In the drives 35 and 47 through the recording unit 38, the control signals at the inputs 55-1 and 55-3, respectively, are sequentially written from the main memory of the mathematical and physical addresses via buses 8 and 28 to the line determined by the decoders 37 and 49. The column number determined by the unit 33 substitution (Fig. 2), is fed to the input 62-3 of the block 48 and to the input 50-4 of the block 31 and then through the corresponding multiplexers (Fig. 7 and 27) to the inputs of the reading blocks 34 and 46. After that, if re-reading the address with the swapped bits of the mathematical address by the control signals at input 53-3 (for block 34) does not compare in any of the columns, i.e., the ready signal for output 51-2 is zero, then from block 6, a “no page” interrupt is issued on bus 14. If a comparison occurs, that is, the ready signal on bus 51-2 is equal to one, then the address from the adder 45 output, obtained by adding the physical address with an offset, as described above, bus driver 44 via bus 28 and through block 1 (FIG. . 1) enters the input 25-1 of block 7, where the appeal to the RAM is formed. In parallel with the conversion of the mathematical address into a physical one, data is sampled (if any) from the data buffer for the read command. To do this, first determine if they are in the buffer by the coincidence of the address tag stored in the corresponding line indicated by the decoder 72 lines of the drive 67 of the data address attributes (Fig. 3), with the higher bits of the mathematical address (see Fig. 28), written in register 70 addresses (Fig. 3). A drive 67 of addressable features of the data is organized in the form of a four-column associative memory similarly to the drive 35 of the mathematical addresses of block 2 (Fig. 1) with the addition of a significance and control bit (Fig. 31). Since the value stored in the drive’s address tag line corresponds to eight 32-bit words of the data buffer, eight words are paged from the RAM interface unit 7 (Fig. 1), and the total buffer size is 2K words (or VK words, depending on of the buffer memory), then the address of the call to the data buffer is smaller than the size of the mathematical page, and in order to prevent crowding out of data lines corresponding to the same page that have the highest bits of the mathematical address when accessing block 3 s NIL LSBs address added modulo two to seven bits of the address in the page number field in block 69 (FIG. 3). In this way, an improvement in address mixing in the drive 67 of the address characteristics of the data is achieved (Fig. 32).

 There are two options for the operation of the address data tag control unit 3. In the first embodiment, if a comparison signal occurs in one of four columns (the data is in the buffer), block 6 generates control signals at the output 24-2, which are converted in block 4 (Fig. 1) into a CED signal, an OE signal for reading, or ME when recording on input 22-1. If the read command is executed by the processor, then the data is read to the processor via bus 8. When data is written, the memory is also accessed (“write-through”) to maintain the coherence of shared data stored in the buffer and in the RAM, which is especially important when working on shared memory of several processors. From block 4, the address from output 21-3 goes to the data buffer memory chips in block 5 (depending on the configuration, CMOS BIS with 2Kx8 or 8Kx8 organization can be used). The package bundle is set programmatically in the status register in block 7. In block 6, the signal “Data Ready” is issued from output 19-1 of block 3.

 In the second embodiment, if no data is found in the buffer, at the physical address calculated on the adder 45, eight words of data are first swapped on bus 9, the data read from RAM is written to block 7, and then (if there was a read command) on the bus 8 per processor. The correctness of the storage of the address tag is checked by the control unit 66 (Fig. 3), and the control signal from the output 19-3 enters block 7, from where it is issued via bus 14 to process the interrupt. The operation of the replacement block 68 (Fig. 3) is completely similar to the operation of the LRU block 33 in block 2 (Fig. 2). During the operation of the page memory control device, it is possible that the line mathematical address + physical address is absent in drives 35 and 47, as it has already been superseded by the replacement mechanism (block 33), and the data is in buffer memory 5 (Fig. 1). This allows you to abandon the result of converting a mathematical address to a physical address, launching RAM, and thereby improve system performance.

 Depending on the value of the significance bit V in block 2 (Fig. 29), two modes of operation are possible when entering the task. In the first mode, if the V significance bit is reset when entering the task, this means that for the corresponding lines, the lines are pumped to drives 35 and 47 on demand. This mode is effective if the operating system solves a problem divided into several sub-tasks, and the change of tasks is relatively rare and is accompanied by a zeroing of the significance bit. This does not lead to a large overhead. However, if the operating system is designed so that entries and returns from the same task are frequent (for any task), it is suggested that when the task is exited, the V significance significance bit (second mode) is not set to zero for the page table row. At the same time, the table of first-level pages (drives 35 and 47) becomes common for several tasks, and each task retains its maximum page table size. The higher digits of the mathematical address play the role of "task number" and are different for page tables of various tasks. The size of the table of pages of the first level is limited, therefore, with an increase in the number of used pages for each task, it is possible that the most used pages are replaced using the LRU mechanism, but only in cases when there is no data in the buffer memory 5. The size of the task number field depends on the size of the page table of the current task (Fig. 33). Due to the table of pages of the second level located in the RAM, the size of the table of pages is practically unlimited and access to the second level does not lead to interruption, which increases the speed of the device. When accessing the physical address of RAM, this address enters block 7 from block 6 through the local bus 28 without conversion.

 Consider the operation of the device when accessing external registers by the example of addressing the drive of mathematical addresses of block 2. The register address by the address strobe issued from the processor via bus 11 is recorded in register 36 of block 2 (Fig. 2) in the first cycle of the command. The address of the drive line is indicated in bits 10-13 of the address that goes to the decoder 37. The sign of the drive selection is decrypted in block 6. Then, if the command being executed is a read command, the column address specified in the zero and first bits of the address, decrypted in block 31 during the second cycle of the command, it arrives at block 34. The information being read from the drive 35 is provided via the local bus 28 through the bus driver 1 (Fig. 1) to the data address bus 8 and then is written to the processor. If the command being executed was a write command, then in the phase of data transmission through the strobe output via bus 11, data through the bus driver 1 is transmitted via local bus 28 to block 38 (Fig. 2). The column address indicated in the zero and first digits of the address register (Fig. 28), decrypted in block 31, from the output 51-1 (Fig. 2) also goes to the write block 38 (Fig. 2). Data is written to the selected column of the drive 35. The write-read of the drive 47 is performed at the same address bits, the difference is in the sign of the choice of drive (Fig. 28).

 The node 73 performs the function of temporarily gating the control signals coming from block 6 from the output 24-2, and consists of known elements AND, OR, NOT and bus drivers used in blocks 31 and 48.

 Access control to the bus 28 (arbiters) is carried out by the device state machine implemented in block 6 on the encoder 98, in which the cycle of the command received from the processor, the alert signals of blocks 2, 3, 4, 7, the current cycle of the internal block timing diagram and control signals are analyzed from the processor. By analyzing these signals, the state of the machine is generated for the next cycle of the time diagram of block 6 in the form of control signals for blocks 1-4, 7.

 The invention improves the performance of the device by fetching data from the data buffer memory, and not from the RAM (when it enters the buffer), by reducing the search time due to parallel viewing of the correspondence of the mathematical and physical addresses and comparing the data address tag for data availability to the buffer, as well as due to the hardware swapping of a new line of the page table (in case of non-inclusion in the buffer) and the absence of the need to switch to the interrupt routine for this case, it is flexible to place and to allocate the newly allocated memory by introducing summation of the page table database with offset, masks for resizing the table in both multitask and single-task mode, remove the restriction on the planned number of simultaneously solved tasks due to the swap mechanism and rejection of hard partitioning of areas allocated for tasks, speed up entry and exit to a new task in multitasking due to the presence of a fast data buffer and a mechanism for updating only the "old pages", provide the ability to change the size of zuemoy buffer memory data specified by a sign in the status register. (56) U.S. Patent No. 4,493,026, cl. G 06 F 13/00, 1985.

 U.S. Patent No. 4,804,097, cl. G 06 F 12/10, 1989.

Claims (1)

MEMORY CONTROL DEVICE containing a central control unit, a bus former, an RAM memory interface unit, a data address management unit, including an address register, two decoders, a mathematical address storage device, an address storage unit, a two-way address storage device addresses / data of the bus former and the information input / output of the interface unit with the operative memory are connected to the bi-directional information bus of the addresses / data of the device, address and information input / the output that controls the input and the control output of the device for interfacing with the operative memory are the address-information input / output, respectively, the control input "Readiness of the operative memory" and the control output "Start of the operative memory" of the device, which controls the input of the "Gateway" The "data readiness" of which is the input and output of the central control unit of the same name, which controls the input of the sign of readiness of which is connected to the same output of the interface unit with random access memory, which controls the input address “Address and data strobe” of which is connected to the central control unit output of the same name, the control output of which is connected to the control inputs of the data address control unit and the bus former, the second information input / output of the address / data input / address of the address data of the central control unit and to the input / output of addresses / data of the control unit of the data address, the output of which is connected via the control bus to the control input of the central control unit interruption of which is the device output of the same name, the output bus of the commands of which is connected to the command output of the RAM unit, the input for setting the device zero is connected to the inputs of the data address control unit and the RAM / address control unit the data is connected by a bi-directional local information / address bus with the address input of the register and the address / data input of the recording unit, the first and second outputs of addresses / data of which I connect are, respectively, to the inputs / outputs of addresses / data of the drive of mathematical addresses and the drive of physical addresses, the address inputs of a sample of a string which are respectively connected to the outputs of the first and second decoders of a line, the address inputs of which are connected to the output of the address of the address of the address register the line and the first control input of the recording unit are connected to the first control output of the first control unit, the control input of which and the control input of the second control unit are connected to the control input to the control unit of the data address, the control input of the second decoder and the second control input of the recording unit are connected to the first control output of the second control unit, the second control output of which and the second control output of the control unit of the control unit of the control unit of the control unit a block for managing addressable data signs, a block for managing buffer data memory, a block for buffer data memory, two bus forms are additionally introduced into a block for managing addressing data a pointer, an aging and replacement unit, a reading and comparing unit, two registers, two multiplexers, an AND block, an adder, a reading unit, and a control unit for addressable data signs contain a data register, a read / write and comparison unit, a control unit, a drive unit , the replacement node, the addition unit modulo two, the address register, the column number decoder, the line number decoder, the control node, the second information input / output of the bus former / address of the bus former is connected to the same input / output of the address of the control unit by the data that controls the input of which and controls the input of the control unit of the buffer memory of the data are connected to the control output of the central control unit, the control inputs of which are connected to the control output of the sign of readiness of the data of the control unit of the buffer memory and the control of the address of the control unit of the control unit connected respectively to the control input of the central control unit and to the address input of the control unit of the buffer memory, the address and control outputs to which are connected to the inputs of the data buffer memory block of the same name, the input / output of addresses / data of which is connected via a bi-directional information bus of addresses / data to the input / output of addresses / data of the interface unit with the operational memory, the input for setting the device zero is connected to the inputs for setting the zero of the control unit the address signs of the data and the control unit of the buffer data memory, the control input of the control unit of the data addresses is connected to the control inputs of the first and second control units, the control inputs are selectable The address of the data address management unit is connected to the control output of the aging and replacement unit, the data output of which is connected to the data input of the recording unit, the data input of the aging and replacement unit and the address / data input of the first bus former are connected to the address / data output of the reading and comparison unit, output comparison signs of which is connected to the same input of the first control unit, the output of signs of comparison of which is connected to the same input of the aging and replacement unit and the second control unit, the first control output the first control unit is connected to the control inputs of the reader and comparison unit, the aging and replacement unit, the first bus former, the output of which, the first input of addresses / data of the read and compare unit, the output of the second bus former, the addresses of the a bi-directional local address / data bus, which is connected to the input / output of addresses / data of the data address control unit, the output of the first and second registers are connected respectively to the first and second inputs of the addresses / data of the first the multiplexer, the address / data output of which is connected to the first input of the addresses / data of the adder and the first address input of the block of elements "AND", the second address input of which, the first and second address inputs of the second multiplexer is connected to the output of the element the address input of the second multiplexer, the output of which is connected to the address input of the adder, the output of which is connected to the address / data input of the second bus former, the address / data input / output of the physical address storage device is connected to the address input / the data of the reading unit, the output of which is connected to the second input of addresses / data of the adder, the output of the reading unit and the output of data of the first multiplexer are connected to the data input of the second control unit, the first control output of which is connected to the control inputs of the first and second
and the second multiplexers, the second bus former, the adder, the read unit, the second line decoder, the second control outputs of the first and second control units are connected to the control output of the control unit, the address of the input to the input of the input to the input address / data of the control unit address data signs is connected via a local address / data bus to the data register data input, to the address input of the addition unit modulo two, with the output of the data block and read / write and comparison, with the first address input of the address register, the second address input of which is connected to the output of the addition unit modulo two, the output of the address register is connected to the first address input of the decoder of the column number, to the address of the address of the address control of addressable data signs, the input of which is set to zero which is connected to the drive input of the same name, the output of the column number decoder is connected to the address input of the column number selection of the reader / writer and comparison unit, input yes of which is connected to the output of the data register, the output of the comparison signal and the information output of the reader / writer and comparison unit are connected to the inputs of the equivalent node of the same name, the output of which is connected to the second address of the decoder of the number of the decoder , the input / output of the data of which is connected to the input / output of data of the reader / writer and comparison unit, the output of the sign of readiness of which is the same output of the address control unit The data output and the data output and the control output of the reader / writer and comparison unit are connected to the same inputs of the control unit, the output of which is connected to the control output of the control unit with addressable data signs, the control input of which is connected to the control inputs of the addition unit modulo two and the control unit, the output of which on the control bus it is connected to the control inputs of the data register, address register, column number decoder, row number decoder, substitution unit, read / write and comparison unit.

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