RU192998U1 - RADIATION-RESISTANT STATIC OPERATIVE REMEMBERING DEVICE (RAM) ON COMPLETE METAL-OXIDES-SEMICONDUCTOR TRANSISTORS - Google Patents

Abstract

Usage: for the field of microelectronics. The essence of the utility model is that the radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors contains blocks of address shapers, blocks of buffer shapers of data, a control circuit, an output resolution circuit, also contains two drives, two detection blocks and error correction, a block of address and control signal generators, which is connected to drives, which are connected to error detection and correction blocks, which are single with blocks of buffer shapers of data, the outputs of which are outputs of the device, and the outputs of blocks of address shapers and control circuits are connected to the inputs of the block of shapers of address and control signals, the output of which is connected to the input of the output resolution circuit, the outputs of which are connected to the inputs of blocks of buffer shapers of data, each drive is made in the form of a matrix of memory cells and contains blocks consisting of basic subunits that contain bit sections of the main bits and times in-line sections of control bits that relate to different words and are structurally arranged in such a way that the bits of one word are spaced apart by a distance sufficient to exclude multiple failures in the bits of the data bus belonging to one information word. Effect: providing the ability to increase resistance to single failures when exposed to individual nuclear particles (VLF). 3 s.p. f-ly, 2 ill.

Description

The utility model relates to the field of microelectronics, namely, to radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors, and can be used in the design, using nanoscale technologies of bulk silicon, ultra-large integrated circuits (VLSI) designed for avionics, aerospace and other applications.

Closest to the claimed utility model is a storage device described in US patent 8,116,164 B2. This storage device is selected as a prototype of the claimed utility model.

The disadvantage of the storage device of the prototype is the absence of error detection and correction blocks in the drives, which leads to a decrease in the failure tolerance of these blocks.

The technical result of the utility model is the creation of radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors with a tunable organization with increased resistance to single failures when exposed to individual nuclear particles (VLF), while there are no multiple failures in the data bus discharges related to one information word, due to the location of error detection and correction units outside the drives, as well as due to the diversity of times poisons one word at a distance sufficient to avoid multiple failures in the data bus bits belonging to the same information word.

The technical result achieved is achieved by creating a radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors containing blocks of addressable drivers, blocks of buffer data drivers, a control circuit, an output resolution circuit, and other g os with the fact that it also contains two drives, two error detection and correction units, a block of address and control signal conditioners, which is connected to drives that are connected to error detection and correction locks, which are connected to blocks of buffer shapers of data, the outputs of which are the outputs of the device, the outputs of blocks of address shapers and control circuits connected to the inputs of the block of shapers of address and control signals, the output of which is connected to the input of the output resolution circuit, the outputs of which are connected with inputs of blocks of buffer shapers of data, with each drive made in the form of a matrix of memory cells and contains blocks consisting of basic subunits, which e do not contain bit sections of the main bits and bit sections of the control bits, which relate to different words and are structurally arranged in such a way that the bits of one word are separated by a distance sufficient to exclude multiple failures in the bits of the data bus belonging to one information word.

In a preferred embodiment, the device comprises four blocks of address formers, with each address generator includes a detector for changing the address.

In a preferred embodiment of the device, the first drive corresponds to the low byte of the word, and the second drive corresponds to the high byte of the word, and each drive is made in the form of a matrix of memory cells and contains 8 blocks consisting of 16 basic sub-blocks that contain 12 bit sections, of which 8 sections of the main categories and 4 sections of the control categories.

In a preferred embodiment, the device contains the discharge sections of the main discharges and the discharge sections of the control discharges, which refer to different words, while between adjacent sections there is a solid p + 2 μm wide region of substrate binding to the ground, and the minimum distance between unicast cells is 64 μm.

For a better understanding of the claimed utility model, the following is a detailed description with the corresponding graphic materials.

Figure 1. The scheme of radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors with a capacity of 16 Mbit with a tunable organization, made according to the utility model.

FIG. 2. The scheme of storage of radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors containing blocks, sub-blocks and sections of memory cells, made according to the utility model.

Items:

1 - the first drive;

2 - the second drive;

3 - blocks for detecting and correcting errors;

4 - block shapers address and control signals;

5 - blocks of buffer data shapers;

6 - blocks of address formers;

7 is a control diagram;

8 - output resolution scheme;

9 - drive blocks;

10 - subunits of drives;

11 - drive sections.

Let us consider more similarly the embodiment of the claimed utility model shown in FIG. 1 and FIG. 2. Radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors contains two drives 1, 2, two blocks 3 for detecting and correcting errors, block 4 formers of address and control signals, blocks 5 for buffer shapers of data, blocks 6 address shapers, control circuit 7, output resolution circuit 8, drive units 9, drive subunits 10, drive sections 11. The block 4 of the shapers of the address and control signals is connected to the drives 1, 2, which are connected to the blocks 3 for detecting and correcting errors, which are connected to the blocks 5 of the buffer shapers of data, the outputs of which are the outputs of the claimed device. The outputs of the blocks 6 of the address drivers and the control circuit 7 are connected to the inputs of the block 4 of the drivers of the address and control signals, the output of which is connected to the input of the circuit 8 for resolving the outputs, the outputs of which are connected to the inputs of the blocks 5 of the buffer data drivers. Each drive 1, 2 is made in the form of a matrix of memory cells and contains blocks 9, consisting of basic subunits 10, which contain bit sections 11 of the main bits and bit sections 11 of the control bits, which refer to different words and are structurally arranged so that the bits of one the words are spaced a distance sufficient to avoid multiple failures in the bits of the data bus related to one information word.

Radiation-resistant static random access memory (Fig. 1, 2) on complementary metal-oxide-semiconductor transistors (hereinafter RAM) contains two independent drives, the first NK0 drive 1 and the second NK1 drive 2, having a capacity of 1MCH12. The first drive HK0 corresponds to the low byte of the word, and the second drive HK1 corresponds to the high byte of the word. Each of the two drives 1, 2 contains 8 blocks 9 with 128KCH12 organization, built on the basis of 10 basic subblocks with 8KCH12 organization, containing 8 sections 11 of the main bits, and 4 sections 11 of the control bits. All address block formers 6 contain address change detectors, due to which the mode of asynchronous address reading of data in RAM is implemented, as well as asynchronous write to change the address, which allows you to quickly fill the drive with a constant, for example, a logical zero to “clear” it.

Between adjacent sections 11 of the drive of the base subunit 10, there is a solid p + 2 μm wide region of substrate binding to the ground, and the minimum distance between unicast cells of sections 11 is quite large - 64 μm, which ensures the absence of multiple failures in one word. This, in combination with additional binding of the substrate to the zero potential bus and the n-pocket, the supply voltage in each cell almost completely suppresses multiple failures in one byte when exposed to single nuclear particles (VLF) and ensures that the RAM is insensitive to the “snap” effect.

The location of the blocks 3 for detecting and correcting errors outside of drives 1, 2 allows to achieve a higher fault tolerance of these blocks compared to their placement directly in drives 1, 2 in the base sub-blocks 8KCh12 with strict restrictions on the size of transistors.

Although the embodiment of the utility model described above was set forth to illustrate the claimed utility model, it is clear to those skilled in the art that various modifications, additions and replacements are possible without departing from the scope and meaning of the claimed utility model disclosed in the attached utility model formula.

Claims (4)

1. Radiation-resistant static random access memory (RAM) on complementary metal-oxide-semiconductor transistors containing blocks of address shapers, blocks of buffer shapers of data, a control circuit, an output resolution circuit, characterized in that it also contains two drives, two detection blocks and error correction, block of address and control signal generators, which is connected to drives, which are connected to error detection and correction blocks, which are connected to buffer blocks data shapers, the outputs of which are the outputs of the device, the outputs of the blocks of address shapers and control circuits connected to the inputs of the block of shapers of address and control signals, the output of which is connected to the input of the output resolution circuit, the outputs of which are connected to the inputs of the blocks of buffer shapers of data, each the drive is made in the form of a matrix of memory cells and contains blocks consisting of basic subunits that contain bit sections of the main bits and bit sections of the control bits that relate to different words and are structurally arranged in such a way that the bits of one word are separated by a distance sufficient to exclude multiple failures in the bits of the data bus related to one information word. 2. The device according to p. 1, characterized in that it contains four blocks of address formers, each address former contains a detector for changing the address. 3. The device according to claim 1, characterized in that the first drive corresponds to the low byte of the word, and the second drive corresponds to the high byte of the word, with each drive being made in the form of a matrix of memory cells and contains 8 blocks consisting of 16 basic subunits that contain 12 bit sections, of which 8 sections of the main bits and 4 sections of the control bits. 4. The device according to p. 1, characterized in that it contains the discharge sections of the main discharges and the discharge sections of the control discharges, which refer to different words, while between adjacent sections there is a continuous p + region of binding of the substrate to the ground with a width of 2 μm, and the minimum distance between unicast cells is 64 microns.

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