RU186859U1 - Multiservice router - Google Patents

Abstract

The utility model relates to data transmission systems, in particular to a modular, scalable structure for building routers of fast Ethernet networks accessing a common data distribution bus. A multiservice router comprising a switching unit and a route processor connected by first inputs / outputs, characterized in that an additional ternary associative memory is inserted into it, the output of which is connected to the third input of the route processor; a first processor module, the first input / output of which is connected to the third input / output of the switching unit; a second processor module, the first input / output of which is connected to the second input / output of the switching unit; a high-speed packet data processing module with a non-blocking high-speed FPGA-based switching matrix, the first output of which is connected to the second input of the first processor module, the second output to the second input of the second processor module, and the third output to the second input of the route processor; the first COM port, the input / output of which is connected to the third input / output of the first processor module; a second COM port, the input / output of which is connected to the third input / output of the second processor module; the first Ethernet port, the input / output of which is connected to the fourth input / output of the first processor module; a second Ethernet port, the input / output of which is connected to the fourth input / output of the second processor module; N SFP modules, the inputs / outputs of which are connected, respectively, with N inputs / outputs of the route processor; a synchronization module, the first output of which is connected to the fifth input of a high-speed packet data processing module with a non-blocking high-speed FPGA switching matrix (FPGA), and the second output is connected to the fourth input of a high-speed packet data processing module with a non-blocking high-speed FPGA switching matrix (FPGA) . 1 s.p. f-ly, 2 ill.

Description

The utility model relates to data transmission systems, in particular, to a modular, scalable structure for building routers of fast Ethernet networks accessing a common data distribution bus.

The closest technical solution is the device described in http://www.conlex.kz/arxitektura-marshrutizatora/ - prototype.

This router contains a switching unit, a route processor, interconnected inputs / outputs, and input and output ports.

The input port performs the functions of the physical layer, completing the input physical line of the router. It also provides the link layer functions necessary to interact with the link layer functions on the other side of the communication line. It also performs the functions of searching and promoting data, so that a packet forwarded to the switching unit of the router appears at the output from the port from which it follows. Control packets (for example, packets containing RIP, OSPF, or BGP information) are moved from the input port to the route processor. In practice, several ports are often combined on one channel card of the router.

The switching block connects the input ports of the router with its output ports.

The output port stores packets forwarded to it through the switching block, and then transmits packets on the output line. The output port performs the functions of the physical and channel layers, the inverse functions of the input port. In the case of a bi-directional communication line (that is, when the line transmits data in both directions), the output port of the communication line, as a rule, is paired with the input port of this line, located on the same channel card.

A routing processor acts as a routing protocol, processes route information, and also performs network management functions in a router.

The purpose of the utility model is to ensure reliable and continuous determination of the current time and generation of 10 MHz and 1 Hz signals synchronized with the assigned system time scale.

This goal is achieved in that in a device containing a switching unit and a route processor, interconnected by first inputs / outputs, characterized in that it additionally includes a ternary associative memory, the output of which is connected to the third input of the route processor; a first processor module, the first input / output of which is connected to the third input / output of the switching unit; a second processor module, the first input / output of which is connected to the second input / output of the switching unit; a high-speed packet data processing module with a non-blocking high-speed FPGA-based switching matrix, the first output of which is connected to the second input of the first processor module, the second output to the second input of the second processor module, and the third output to the second input of the route processor; the first COM port, the input / output of which is connected to the third input / output of the first processor module; a second COM port, the input / output of which is connected to the third input / output of the second processor module; the first Ethernet port, the input / output of which is connected to the fourth input / output of the first processor module; a second Ethernet port, the input / output of which is connected to the fourth input / output of the second processor module; N SFP modules, the inputs / outputs of which are connected, respectively, with N inputs / outputs of the route processor; a synchronization module, the first output of which is connected to the fifth input of a high-speed packet data processing module with a non-blocking high-speed FPGA switching matrix (FPGA), and the second output is connected to the fourth input of a high-speed packet data processing module with a non-blocking high-speed FPGA switching matrix (FPGA) .

Comparison with the prototype shows that the inventive device is characterized by the presence of new units and their connections between them. Thus, the claimed device meets the criterion of "novelty."

Comparison of the proposed solution with other technical solutions shows that the listed elements used in the blocks are known, however, their introduction in the indicated connection with the other elements leads to reliable and continuous determination of the current time and the generation of signals of 10 MHz and 1 Hz synchronized with the assigned system timeline. This confirms the conformity of the technical solution to the criterion of "significant differences".

In FIG. 1 shows a general block diagram of the proposed device, which includes a route processor 1, switching unit 2, a module for high-speed processing of packet data with a non-blocking high-speed switching matrix based on FPGAs 3, processor module 1 (2) 5, ternary associative memory 4, COM port 1 (2) 8, Ethernet port 1 (2) 7, N SFP modules 9, synchronization module 6.

In FIG. 2 - disclosed the structure of the synchronization module.

The device operates as follows.

Routing in IP networks is a process of sending data packets based on the study of service information in the packet header, modification of a part of service information, and forwarding of the packet to the desired port. From the point of view of the router, data packets can be divided into two types: service packets (routing, control, monitoring, diagnostics protocols) designed to be processed directly by processor module 5 and transit packets, which are subjected to the routing process.

The main function of routing data packets in the device is performed by the route processor. The trip processor is a dedicated processor designed and optimized for data packet processing operations. A special program is executed on this processor in an infinite loop, analyzing the contents of the packet (packet header, and, in certain cases, the packet body), modifying the packet header and forwarding. When forwarding a packet through a specific port, the route processor is guided by the routing table. This table is formed using manual configuration of routes, or using dynamic routing protocols.

The processor module 5 is responsible for the formation of the routing table. Dynamic routing processes are started on this module. The module also configures the routing processor functions, collects statistics, provides communication with control systems and processes service packets.

The PCI bus is used to configure the trip processor. Ethernet is used to forward service packets.

This device contains two processor modules 5, working in hot standby. For switching control signals from the active module to the route processor, switching unit 2 (PCI switch) is used. For sending service packets to both processor modules 5, a high-speed packet data processing module with a non-blocking high-speed FPGA 3 switching matrix is used.

To speed up the search process in the routing table, a special memory is used, the so-called ternary associative memory 4.

When the device boots, the processor module 5 communicates with neighboring devices via dynamic routing protocols, and a routing table is formed. After the table is formed, the processor unit 5 converts this information for storage in the ternary associative memory 4.

The input / output ports are slots for SFP modules 9. SFP modules convert signals received from copper or optical communication lines into a format suitable for processing by a route processor.

When a data packet arrives from the SFP 9 module, the route processor analyzes the packet header. Service packets are redirected to the processor module 5, for transit packets, a correspondence search is performed in the routing table stored in a simplified form in the ternary associative memory 4. After that, the transit packet is forwarded through the corresponding port.

For the initial configuration or direct control of the device, serial COM ports 8 and Eth 7 ports are provided, which are connected directly to the processor modules 5.

The use of a high-speed packet data processing module with a non-blocking high-speed FPGA 3 switching matrix provides the necessary flexibility in the development of hardware logic for processing network traffic, as well as the possibility of implementing additional functionality when changing the competitive environment without changing the device architecture.

Synchronization module 6 is designed to reliably and continuously determine the current time and output signals of 10 MHz and 1 Hz to the module for high-speed processing of packet data with a non-blocking high-speed switching matrix based on FPGA 3.

Thus, the introduction of new elements provides continuous access to the communication router and the expansion of the functionality of the router in the continuous adjustment of the accuracy of the synchronization signal both in frequency and phase.

Claims (2)

1. A multiservice router comprising a switching unit and a route processor connected by first inputs / outputs, characterized in that an additional ternary associative memory is inserted into it, the output of which is connected to the third input of the route processor; a first processor module, the first input / output of which is connected to the third input / output of the switching unit; a second processor module, the first input / output of which is connected to the second input / output of the switching unit; a high-speed packet data processing module with a non-blocking high-speed FPGA-based switching matrix, the first output of which is connected to the second input of the first processor module, the second output to the second input of the second processor module, and the third output to the second input of the route processor; the first COM port, the input / output of which is connected to the third input / output of the first processor module; a second COM port, the input / output of which is connected to the third input / output of the second processor module; the first Ethernet port, the input / output of which is connected to the fourth input / output of the first processor module; a second Ethernet port, the input / output of which is connected to the fourth input / output of the second processor module; N SFP modules, the inputs / outputs of which are connected, respectively, with N inputs / outputs of the route processor; a synchronization module, the first output of which is connected to the fifth input of a high-speed packet data processing module with a non-blocking high-speed FPGA switching matrix (FPGA), and the second output is connected to the fourth input of a high-speed packet data processing module with a non-blocking high-speed FPGA switching matrix (FPGA) . 2. The device according to p. 1, characterized in that all its elements are made using digital technology.

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