RU1837270C - Device for taking square root of sum of squares of two values - Google Patents

Abstract

The invention relates to computer engineering and automation and can be used in analog computers, as well as in automation systems, for example, for calculating the length of a two-dimensional vector from its components. The device for extracting the square root from the sum of the squares of two values contains five extraction units of module 1-5, a minimum signal extraction unit 6, a maximum signal extraction unit 7, an inverter 8, a divider 9, and four adders 10-13. 1 silt

Description

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The invention relates to computer technology and automation, it can be used in analog computers, as well as in automation systems, for example, to calculate the length of a two-dimensional vector from its components.

The purpose of the invention is to improve accuracy,

The drawing shows a block diagram of a device.

The device comprises module isolation units 1-5 (first to fifth, respectively), a minimum signal extraction unit 6, a maximum signal extraction unit 7, an inverter 8, a voltage divider 9, adders 10-13 (first to fourth, respectively).

The device operates as follows.

The inputs of the first and second module isolation blocks, which are the inputs of the device, are supplied with the input signals X and Y, respectively. At the output of the block. In this case, an IXI signal is generated, and at the output of block 2, an IYI signal. These signals are fed to the inputs of the maximum signal extraction unit 3 and to the inputs of the maximum signal extraction unit 4. Thus, a signal is generated at the output of block 3

m min (| Xl, IYI),

(D

and at the output of block 4 - a signal

M max (| Xi, IYI). (2)

These signals are fed to the first and second inputs of the first adder 10, respectively.

The signal M also goes to the input of the inverter 8, the output signal - M of which is supplied to the input of the voltage divider 9.

At the first, second, and third outputs of the voltage divider 9, signals -tiM, -taM, -1zM are generated, respectively, arriving at the first inputs of the second, third, and fourth adders 11, 12, 13, respectively.

The second inputs of these adders are combined and connected to the output of the minimum signal extraction unit 6. Therefore, at the output of the second adder 11, an m-tiM signal is generated, at the output of the third adder 12, an m-taM signal, and at the output of the fourth adder, an m-tsM signal. Blocks 3-5 separate modules of the corresponding signals: at the output of block 3, an Im-tiM i signal is generated, at the output of block 4, an m-t2M I signal, and at the output of block 5, an Im-taM I signal. We denote by Si the summation coefficient of the first adder 10 at the ith input (1 1,2,. ,, 5). Since the outputs of the modules 3, 4, 5 of the allocation module are connected respectively to the third, fourth and fifth inputs of the adder 10, a signal Z defined by the formula will be generated at its output

10

Z Sim + S2M + S3 lm-tiM | +

+ SA I m-taM I + 85 I m-taM I

 Vx2 + Y2 (3)

The coefficients ti, ta, t3, and Si, Sa, ..., Ss are selected from the condition of minimum error. At ti 0.21875, t2 0.4535, 13 0.7239, Si 0.379469161, Sa 0.878765278, 84, 0.093961610, Ss 0.073033935.53

0.104376657 maximum relative error in calculating the quantity

by the formula (3), defined by the formula

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does not exceed 0.293%. The table below shows the values of 5 for various combinations of X and Y in the 0.1 segment in increments of 0.1.

Thanks to the introduction of a number of new elements and new functional relationships, the accuracy of determining the result of the proposed device is significantly higher (about 1.7 times) than the accuracy of the prototype.

Claims (1)

SUMMARY OF THE INVENTION A device for extracting the square root of the sum of the squares of two quantities, comprising the first and second module extraction units, the inputs of which are the device inputs, and the outputs are connected to the inputs of the minimum signal extraction unit and to the inputs of the maximum signal extraction unit, the outputs of which are connected respectively to first and second the first inputs of the first adder, as well as voltage divider, characterized in that, in order to increase accuracy, the second, third and fourth adders, the third, fourth and fifth blocks of the module isolation and the inverter connected to the output of the maximum signal extraction unit and the output are introduced into it to the input of the voltage divider, the first inputs of the second, third and fourth adders are connected to the corresponding outputs 518372706 voltage divider, second inputs of the third, fourth and fifth allocation blocks are dined and connected to the output of the module vde-module, the outputs of which are connected to the minimum signal, and the outputs, respectively, to the third, fourth and fifth connected to the inputs respectively third-inputs of the first adder.