RU1833915C - Device to display symbols on tube screen - Google Patents

Abstract

Usage: automation and computer technology, output systems of various graphic symbols. The inventive device contains 2 counters (1, 2), 4 delay elements (6, 7, 9, 10), 3 OR elements (4, 5, 15), 1 AND element (17), 1 register (3), 1 read-only memory block (8), 1 pulse generator (11), 1 decoder

Description

The invention relates to automation and computer engineering and can be used for. outputting various graphic symbols synthesized from decomposition elements of a small-format television raster onto the cathode ray tube screen using the data received in a digital binary code.

The purpose of the invention is to simplify the device.

In FIG. 1 is a structural diagram of a device; in FIG. 2 - diagrams of signals explaining the operation of the device; in FIG. 3 is a schematic diagram of a shifter.

The device contains the first 1 and second 2 counters, register 3, the first 4 and second 5 OR elements, the first 6 and second 7. delay elements, a block 8 of read-only memory, the third 9 and fourth 10 delay elements, an 11 pulse generator, decoder 12, first 13 and second 14 code-voltage converters, third 15 OR element, shifter 16 and 17 I.

Slider 16 comprises: first 18, second 19, third 20, fourth 21 and fifth 22 differentiating elements 23 OR. Counter 1 is intended for temporary storage of the initial code equivalent of a symbol sufficient for sampling in block 8 of read-only memory the code equivalent of a symbol in the form of a small-format television raster, after which counter 1 is used to generate the voltage Ux (t), which scans the CRT beam along the lines of small-format television raster and sample output signal wires of the decoder 12, that is, this counter also combines the functions of the register. The first control input of the counter 1 is connected to the output of the element 4 OR, the second to the output of the delay element b, the counting to the output of the generator 11, the information inputs of the counter 1 are information inputs of the device, the outputs of the counter are connected to the address inputs of block 8, while the first three exits

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the counter is connected to the inputs of the decoder 12 and the converter 13 code - voltage,

The counter 2 is designed to ultimately generate a voltage Uy (t), which shifts the CRT beam between the lines of a small-format television raster, and to generate a signal at the time the symbol is displayed. The first input of this counter is connected to the output of the OR element 5, the second - to the first input of the OR element 4 and to the sixth output of the decoder 12, the zero output of which is not used, the three outputs of this counter are connected to the inputs of the converter 14 code - voltage, fourth the output of counter 2 is the fourth output of the device and is connected to the second input of the OR element 5 and to the input of the generator 11.

Register 3 is designed to send a symbol in the form of a small-format television raster from block 8 of the parallel code to form a sequence of backlight pulses representing a serial symbol code in the form of a small-format television raster. Case resolution is m -n

5 7 - 35.

The OR element 4 is intended to perform a logical disjunction operation with respect to two input signals.

The OR element 5 is intended to perform a logical disjunction operation with respect to two input signals.

The delay element b is intended to delay the input signal while the counter 1 is reset to zero.

The delay element 7 is designed to delay the input signal during the time of sending to the counter 1 at the information inputs of the initial code equivalent of the symbol {Vi}. Its input is connected to the output of the element.

6 delays, and the output is to the input of the delay element 9 and to the control input of block 8.

The read-only memory unit 8 is intended for storing parallel character codes included in the volume of the displayed alphabet in the form of a small-format television screen. Its address inputs are connected to the outputs of counter 1, the control input is to the output of the delay element 7, and the outputs are connected to the information inputs of register 3.

The delay element 9 is designed to delay the input signal while sampling the code equivalent of the symbol in block 8. Its input is connected to the output of the delay element 7, and the output to the third input of the OR element 4, to the third control

the input of the register 3 and the input of the delay element 10.

The delay element 10 is designed to delay the input signal while the code equivalent of the symbol is sent from block 8 to register 3, Its input is connected to the output of the delay element 9, and the output to the first input of the generator 11.

The 11 pulse generator is designed

to generate pulses that determine the operation of the device as a whole,

Decoder 12 is designed to generate rectangular pulses taken from the first five of its outputs, and

5 control signal taken from its sixth output. In this case, the zero output of the decoder is not used.

The code-voltage converter 13 is designed to generate a voltage Ux (t) by the input code of the CRT beam driver, which ultimately moves the electron beam in the plane of the tube screen along the lines of a small-format television screen.

5 Converter 14 code voltage

it is intended for generating, by the input code of the CRT beam control beam, a voltage Uy (t), which ultimately shifts the electron beam in the plane of the screen on the CRT between the lines of a small-format television screen.

Element 15 is designed to perform a logical disjunction operation with respect to five input signals. His

5, the inputs are connected to the first five outputs of the decoder 12, the zero output of which is not used, and the output to the first input of AND element 17.

The motor 16 is designed to generate signals, under the influence of each of which the contents of the register 3 is shifted by one bit. Its inputs are connected to the first five outputs of the decoder 12, the zero output of which is not

5 is used, and the output to the second control input of register 3,

Element 17 AND is intended to perform a logical conjunction operation with respect to two input signals.

The differentiating elements 18-22 are designed to generate short-term pulses corresponding to the trailing edge of each of the rectangular pulses taken from the first five outputs of the decoder 12, the zero output of which is not used. The input of element 18 is connected to the first output of the decoder 12, element 19 to the second, element 20 to the third, element 21 to the fourth and element 22 to n, and the output of each of

of these elements is connected respectively to the first, second, third, fourth and fifth inputs of the OR element 23, which is designed to perform a logical disjunction operation with respect to the five input signals.

The device operates in the following sequence. The signal UR, arriving at the control input R from the buffer memory unit (which is not shown in the drawing), is supplied to the control inputs of the first 1 and second 2 counters and register 3 and resets them to zero. The signal UR (Fig. 2) is supplied to the inputs of the counters 1 and 2 through the first 4 and second 5 OR elements.

The signal UR also arrives at the input of the delay element 6, in which it is delayed by the time counter 1 is reset to zero. From the output of element 6, a signal is taken which is supplied to the control input of counter 1, and the original code equivalent of the symbol to be displayed is written to it from the buffer memory unit.

The signal Uv from the output of element 6 is fed to the input of the delay element 7, which is delayed by the time {Vi} is sent to counter 1. The signal Uv is removed from the output of element 7, which is supplied to the control input of the read-only memory 8 a choice is made at the address located in counter 1 of the code equivalent of a symbol in the form of a small-format television raster, since the outputs of counter 1 are closed to the address inputs of block 8.

The signal Uv from the output of element 7 is also supplied to the input of the delay element 9, in which the code equivalent of a symbol in the form of a small-format television screen is delayed for sampling in block 8. From the output of element 9, an ISC signal is fed, which is fed to the recording control input of register 3, and the code equivalent of a symbol in the form of a small-format television raster from block 8 is sent to register 3. In addition, the signal from the output of element 9 is supplied to the input of element 4 OR passes through it and resets counter 1 to zero.

The signal Uc., From the output of element 9 is also supplied to the input of the delay element 10, the output of which is removed by the signal U3an, which is supplied to the start input of the generator 11. Pulses VG are taken from the output of the generator 11. which go to the counting input of the counter 1 operating in the addition mode. At element 10, the signal is delayed while the code is being written from block 8 to register 3, which is longer than the counter 1 reset time to zero.

The first three outputs of counter 1 are connected to the inputs of decoder 12. Since the content of counter 1 increases from pulse to pulse VG, rectangular pulses Vi, Vz, Uz, V4, Vs. are taken from the outputs of decoder 12, the zero output of which is not used. When the contents of counter 1 becomes six, the signal Uec of the sixth output of the decoder 12 through the OR element 4 resets counter 1 to zero.

The first three outputs of counter 1 are connected to the inputs of the first 13 code-voltage converter, from the output of which the voltage Ux (t) is removed, which ultimately scans the CRT beam along the lines of a small-format television screen.

The signal Ue from the sixth output of the decoder 2 is supplied to the counting input of the counter 2 and increases its content by one. The outputs of counter 2 are connected to the inputs of the second 14 code-voltage converter, from the output of which the voltage Uy (t) is removed, which displaces the CRT beam between the lines of a small-format television raster.

The voltage Ux (t) and Uy (t) are supplied through the respective amplifiers to the CRT deflection system, under the influence of the field of which its beam is deployed along the lines of a small-format television raster. The first five outputs of the decoder 12 are closed to the inputs of the OR element 15, from the output of which a pulse Uis equal to the duration of the total pulse duration Ui, ..., U5 is taken. In addition, these outputs of the decoder 12 are connected to the inputs of the shifter 16, from the output of which signals Uie corresponding to the trailing edge of the pulses UiUs are removed. The signals U16 from the output of the shifter are connected to the second control input of register 3. Each Die signal causes the contents of register 3 to be shifted by one bit.

The output of the last bit of the register 3 is connected to one of the inputs of the element 17 AND, to the other input of which the signal U is from the output of the element 15 OR. As a result, the backlight pulses Uz, which are fed to the CRT control electrode, are removed from the output of the element 15 AND, thereby achieving the illumination of the decomposition elements of the small-format television raster at the points, the combination of which is a displayed symbol adequate to {Vj}. In FIG. 2 backlight pulses Uz are shown in relation to the upper two lines of the small-format digit 5 (Vzs) from a television raster.

When the contents of counter 2 becomes eight, a signal is picked up from its fourth output, which is fed through OR element 5 to the input of counter 2 and resets it to zero. In addition, the signal from the fourth output of the counter And goes to the generator 11 and disrupts its generation.

The signal recorded from the fourth output of counter 2 is indicated in FIG. 1 Uw. This signal is sent to the buffer memory unit, informing it of the end of the symbol mapping process.

The operation of the shifter 16 is as follows.

The rectangular pulses Vi, V2, Uz, V4 and Vs from the first, second, third, fourth and fifth outputs of the decoder 12 are supplied to the inputs of the first 18, second 19, third 20, fourth 21 and fifth 22 differentiating elements. A signal corresponding to the trailing edge of the input pulse is taken from the output of each of these elements.

The outputs of the elements 18 ... 22 are shorted to the inputs of the OR element 23, from the output of which the shift signals Vie are taken.

The technical and economic efficiency of the device consists in its simplification, as well as in reducing the volume of the buffer memory unit and in reducing the resolution of the first counter, which simultaneously functions as an input register.

Claims (2)

SUMMARY OF THE INVENTION 1. A device for displaying symbols on a cathode ray tube (CRT) screen, comprising a register, first and second counters, first and second code-voltage converters, a decoder, first, second and third delay elements, first and second OR elements and a read-only memory unit, the outputs of which are connected to the information inputs of the register, the first input of the first OR element is the control input of the device connected to the input of the first delay element, the output of which is connected to the input of the second element latency, one of the outputs of the first counter is connected to the inputs of the decoder and the first code-voltage converter, the outputs of the group of the second counter are connected to the inputs of the second code-voltage converter, the outputs code-voltage converters are the outputs of the deviating voltages, respectively, at the x and y coordinates of the device, the output of the first element OR connected to the reset input of the first counter, characterized in that, in order to simplify the device, it contains a third OR element, an AND element, a fourth delay element, a pulse generator, and shifter. the inputs of which are connected to the outputs of the decoder group connected to the inputs of the third element OR, the output of which is connected to the first input of the element And, the second input of which is connected to the output of the register, the output of the element AND is the output of the device backlight signal, the output of the second delay element is connected to the input of the third delay element and the control input of the memory block, whose address inputs are connected to the outputs of the first counter, whose information inputs are inputs Device symbol code, countable  the input is connected to the output of the pulse generator, and the control input is connected to the output of the first delay element, the output of the third delay element is connected to the second input of the first OR element, the input of the fourth delay element and the input register write control, the shift control input of which is connected to the output of the shifter, and the reset input is to the control input of the device connected to the first input of the second OR element, the second input which and the stop input of the pulse generator are connected to the output of the second counter, the control input of which is connected to the output of the second OR element, and the counting input is connected to the output of the decoder, connected to the third input of the first OR element, the output of the fourth delay element is connected to the start input of the pulse generator, the output of the second counter is the signal output. End of display of the device. 2. The device according to claim 1, characterized in that the shifter contains five differentiating elements, the inputs of which are inputs of the shifter, and the outputs are connected to the inputs of the OR element, the output of which is the output of the shifter. FIG. 7 Us Jcl P and, Fig.Z Editor Compiled by V. Govorov Tehred M. Morgenthal k Proofreader I. Shulla