RU1818636C - Device for multichannel magnetic recording and playback of signals having correction of time distortions - Google Patents

Abstract

The invention relates to magnetic recording, and in particular, to devices for correcting temporary distortions that occur during the recording-reproduction process, and may find application in precision magnetic recording devices. The aim of the invention is to increase the accuracy of the correction of temporal distortions in multichannel magnetic recording. SUMMARY OF THE INVENTION: the device comprises input buses, adders, recording amplifiers, recording heads of information signals, a recording head, reference signals, a reference signal generator, two low-pass filters, two frequency dividers in the recording channels. 3 ill.

Description

The invention relates to magnetic recording, in particular to devices for correcting temporary distortions arising during recording and reproduction, and may find application in analog magnetic recording devices for accurate magnetic recording.

The aim of the invention is to increase the accuracy of the correction of temporal distortions of information signals in multichannel magnetic recording.

Figure 1 shows the structural diagram of the proposed device; figure 2 - the relative position of the reference signals in the frequency domain; Fig. 3 is an exemplary embodiment of a buffer storage device.

The structural diagram of the device (Fig. 1) contains in the recording channels input buses 1 of information signals connected via series-connected second adders 2 and amplifiers 3 to the recording heads 4 of the recording information and reference signals to the recording medium 5, and the reference signal recording head 6 is connected to the output of the generator 7 of the reference signals through a series-connected recording amplifier 8, a third adder 9, a fifth low-pass filter 10 and a second frequency divider 11. Moreover, the second inputs of all adders 2 and 9 of the recording channel are combined are connected and connected to the output of the reference signal generator 7 through a sixth low-pass filter 12 and a third frequency divider 13 connected in series, and in the playback channel of the information signal reproducing head 14, they are connected to the output by a bus 15 in each channel of the information signal through series-connected playback amplifiers 16

00

k

00 (X SL

and

information signals, a delay line 17, a first low-pass filter 18, an analog-to-digital converter 19, a buffer storage device 20, a digital-to-analog converter 21, and a second bandpass filter 22, the output of information signal reproducing amplifiers 16 in each channel of the information signal being connected to second inputs an analog-to-digital converter 19 and a buffer storage device 20 through a tenth low-pass filter 23 connected in series, a second phase detector 24, a fourth low-pass filter 25, an adjustable attte nuator 26, first adder 27, first voltage controlled oscillator 28, first bandpass filter 29 and first pulse shaper 30, the output of the first voltage controlled oscillator 28 being connected to the second input of the first adder 27 through the first divider 31 connected in series frequencies, a first phase detector 32 and a third low-pass filter 33. The output of the digital-to-analog converter 21 is connected to the second input of the adjustable attenuator 26 through a second low-pass filter 34, a frequency detector 35, a quadratic detector 36, and an amplifier 37 connected in series. In addition, the output of the reference signal generator 7 is connected to the third input of the buffer storage 20 of each channel information signal, and the reference signal reproducing head 38 located between the information signal reproducing heads 14 is connected to the second input of the second phase detector and 24 of each channel of the information signal through a series-connected reference signal reproducing amplifier 39, a ninth low-pass filter 40 and a phase shifter 41. In addition, the output of the reference signal reproducing amplifier 39 is connected to a threshold device 42 and a high-pass filter 43, the output of which is connected with the second input of the first phase detector 32 of each channel of the information signal through the second pulse shaper 44 and the switch 45 connected in series, and the second input of the threshold device 42 is dined with the output of the reference voltage source 46. In this case, the output of the threshold device 42 is connected to the second input of the switch 45, in addition, the output of the amplifier 16 for reproducing an information signal recorded on a track adjacent to the reference signal recording track is connected to the third input of the switch 45 via consistently

connected by a seventh low-pass filter 47, a third phase detector 48, an eighth low-pass filter 49 and a second voltage controlled oscillator 50, the output of which is also connected to the second input of the third phase detector 48 through a fourth frequency divider 51, and a second buffer storage output 52 20 of one of the channels of the information signal is used

to control the speed of the drive motor in playback mode.

The device operates as follows.

Information signals (ICs) are supplied to the first inputs of adders 2 from input buses 1, and an auxiliary low-frequency reference signal (LFCH), a signal output from the reference signal generator 7, a third frequency divider 13, and a sixth low-pass filter 12, are fed to their second inputs. The sum of the ICs and LFCH is amplified in the recording amplifier 3 and recorded by the recording head 4 on the recording medium 5. The output signal of the reference signal generator 7, the second frequency divider 11 and the fifth low-pass filter 10 are formed by a high-frequency reference signal (LFCH). Signals LFOS and VChOS arrive at the inputs of the third adder 9, from its output - to the amplifier 8

reference signal recordings are further recorded on the recording medium 5 by the magnetic head 6 of the reference signal recording.

Filters 10 and 12 serve to isolate the first harmonic from the output signals of the dividers 11 and 13 in order to eliminate the possibility of spurious combinational components when summing and recording signals. Magnetic head 6 recording support

signals is recorded on a track located in the middle part of the medium, next to the nth recording channel IC (IC + LFCH), where the channel number m is determined with the total number of recording channels n according to the formula

m

Jji

2

with an even number of p.

fifty

And according to the formula m

n + 1

with odd p.

The choice of the relative position of the LNF, RFL and IC in the frequency domain (Fig. 2) should be such that the spectra of the LNF and VChOS (curves 1 and 2 in Fig. 2, respectively) are within the frequency response of the magnetic recording apparatus (curve 3 on figure 2), did not overlap due to the action of the parasitic FM, arising due to oscillations

carrier speeds, and, in addition, the LFAS and IC spectra (curve 4 in Fig. 2) should not overlap.

After reproducing an information signal in each channel, the signal read by the playback head 14 is amplified by the playback amplifier 16, delayed by a delay line 17, which equalizes the time spent by the information and reference signals at the inputs of the analog-to-digital converter 19, the first low-pass filter 18 is intended to limit the spectrum at the input of the analog- digital converter 19. After conversion in the analog-to-digital converter 19 information signal with the frequency of the control signal take in Borok Tg 3fa. where fe is the upper frequency in the spectrum of the information signal, the digital code is written to the buffer, the drive 20. Since the control signal is formed from the reference signals subject to the same temporal distortions as the information signal, and reading from the buffer storage is carried out with a stable frequency Tschit. generated by the generator 7 of the reference signal and equal to the average value of the frequency TD. then, after converting the code words read from the buffer storage device 20 into an analog form in a digital-to-analog converter 21 and filtering it with a band-pass filter 22, a signal with significantly less time distortion than in the reproduced information signal is fed to the output bus 15 of the device. The control signal of the analog-to-digital converter 19 is generated from the RFES reference signal of the reference signal channel as follows. After reproducing the sum of the reference LFCH and VChOS reference signals by the heads 38 and amplifying them with playback amplifiers 39, they are separated by frequency using the ninth low-pass filter 40 and the high-pass filter 43, respectively.

Next, a pulse signal is generated from the RFES signal with the help of the second driver 44, which, through the switch 45, is fed to frequency multipliers made on the basis of the PLL in each channel of the information signal.

PLLs consist of a first phase detector 32. a third low-pass filter 33, a first adder 27, a first voltage-controlled oscillator 28, a first frequency divider 31. To ensure the equality of the average frequencies of writing and reading from the buffer storage, the frequency multiplier by the PLL determined by the division coefficient of the first frequency divider 31, is selected equal to the division coefficient of the second frequency divider 11, and the magnetic recording apparatus must have a system for controlling the average speed l, wherein the control signal is generated on bus 52 an information Kanakh) catching device. The output signal of the voltage-controlled generator 28, after filtering by the band-pass filter 29 and forming from the output signal of the filter 29 using a pulse shaper 30

5 is fed to the sampling control input of the analog-to-digital converter 19 and the write control input of the buffer storage 20.

The extraction of an error signal proportional to the MVI in each channel of the information signal is carried out using the second phase detector 24. At its first input, a low-frequency filter is filtered from I With the tenth filter

5 low frequencies 23, and to the second input - the LFOS signal recorded in the channel of the reference signal, highlighted by the ninth filter, lower. frequency 40 and phase shifted phase shifter 41, which is necessary to set the operating point of the phase detector 24 in the middle of the linear section. From the output of the phase detector 24, the signal through the fourth low-pass filter 25 and an adjustable attenuator 26 is fed to

5 another input of the first adder 27 in the PLL loop. The cutoff frequency of the lowpass filter 25 is equal to the upper frequency in the MVI spectrum. Adjustable attenuator 26 has the ability to initially adjust the transmission coefficient. When the control input is turned off during the device setup process, its transmission coefficient is individually controlled in each channel in order to achieve a minimum VI in the output signal of the device. Then connect the input. control (thereby closing the feedback loop) and subsequently during operation of the device, the minimum VI at the output of the device under the influence of destabilizing factors is set automatically.

A feedback circuit is connected between the output of the digital-to-analog conversion. the slider 21 and the control input of the attenuator 26, operates as follows. Due

5, the non-idealization of the correction of the VI signal of the LFER at the output of the digital-to-analog converter 21 has residual VIs manifesting itself as a parasitic frequency modulation of the signal (IFM). The output information signal also has such an MFM. Dedicated

the second low-pass filter 34 LFN with FFM is fed to the frequency detector 35, which emits a signal proportional to the FFM LFN, i.e. residual VI. It is detected and filtered using a quadratic detector 36, which generates a constant voltage output proportional to the residual VI. After amplification by an amplifier 37, this voltage controls the gain of the adjustable attenuator 26, through which a signal proportional to MVI is supplied to the input of the adder 27 of the PLL loop. generating a control signal for writing to the buffer storage 20. Moreover, the control signal is phased so that as the MVI increases, the attenuator transmission coefficient 26 increases, but decreases as it decreases.

Thus, the following feedback is introduced, which allows tuning the efficiency of MVI correction automatically when the geometric parameters of the heads are changed, when recording and playing on various magnetic recording devices, when the parameters of the tape drive are changed.

In order to prevent device malfunctions under the influence of LAM, the impact of which may be most susceptible to RFES, its replacement is provided in case of loss.

The replacement is carried out multiplied by the required number of times LFOS recorded in the channel of the reference signal, therefore, having the same VI as the VChOS. Since the LFAS is recorded in the low-frequency region of the AFC frequency response, the effect of PAM on it is much less than on the LFV. Replacement occurs when a control signal appears at the output of threshold device 42, one of which receives an RFE, and the other from a reference voltage source 46; a threshold level slightly exceeding the noise level in the channel of the reference signal. Thus, while the RFES level is above the threshold level, it is supplied to the output of the switch 45. When the RFES level decreases below the threshold. After that, the switch 45 is switched and the LFCH multiplied by the PLL circuit, consisting of the third phase detector 48, the tenth low-pass filter 49, the second generator controlled by voltage 50, and the fourth frequency divider 51 The multiplication factor FAK K is equal to the division coefficient of the frequency divider 51 and is determined by the formula

to fBHOC

thnchos

where f vchos and fHHOC are the frequencies of the high-frequency and low-frequency reference signals, respectively.

Recording amplifiers 3 and 8 are made on operational amplifiers x (op amp) of type K1407UD1. The reference signal generator 7 is made on a high-stability (±) quartz oscillator GKVO-P-10-1 Sonet TsL2.210.060 TU, frequency dividers 11, 13 and 51 - on programmable integrated meters such as K155IE7, low-pass filters 10, 12, 18, 23 , 25. 33, 34, 40, 47 and 49 devices, the high-pass filter 43, as well as the band-pass filters 22 and 29 are made according to the schemes of active RC filters with inverse Chebyshev approximation to the K1407UD1 op-amp, the adders 2, 9 and 27 - on the K1407UD1 type op-amp according to the scheme of a summing amplifier, information reproduction amplifiers 14 and 16 reference 39 signals They are installed on a K 140UD1 op amp, a delay line 17 is made on a 528BR1 type discrete analog integrated delay line, an analog-to-digital converter 19 is on a K 1113PV1 chip, a digital-to-analog converter 21 is on a K594PA chip, pulse shapers 30 and 44 are on integrated comparators of type K521CAZ, generators controlled by voltages 28 and 50 are on the K531GG1 microcircuit, phase detectors / 24, 32 and 48 are made, for example, according to the circuit shown in Fig. 6.60 in the book. V. Manasevich. Frequency synthesizers. Theory and design. M .: Svyaz, 1979, p. 288, an adjustable attenuator 26 on the KPZOZOE field-effect transistor, the frequency detector 35 is a 155AG1 single-vibrator and a low-pass filter on an K1401UD1 op-amp, connected in series, a quadratic detector 36 is assembled on a 525PS2 multiplier and a low-pass filter on an Outip K1401UD1 amplifier, connected 37 - to the K1407UD1 type op amp, the reference voltage source 46 - to the K140UD7 type op amp according to the compensation voltage stabilizer circuit, the phase shifter 41 is made according to the phase link circuit to the K1407UD1 op amp, switch 45 is made chip type K590KI2.

A possible embodiment of the buffer storage device 20 (block diagram) is shown in FIG. The digital code of the information signal from the analog-to-digital Converter 19 is stored in the operational

a storage device (RAM) made on the chips KR 537RU10. The write and read addresses of the code on the OPC are formed by the counters of write and read addresses. As address counters, counters with initial installation of a code of type K155IE7 were used. The initial shift between the write and read addresses is carried out by the initial setting circuit, the address switching at the address inputs of RAM is performed using the address multiplexer. The address multiplexer circuitry furthermore provides priority for reading information from RAM and while recording and reading signals arrive, delays the write signal until the end of the read cycle. In order for the device to function normally, it is necessary to ensure that the average recording and reproducing speeds in the magnetic recording apparatus are equal. For these purposes, a code subtractor and a digital-to-analog converter have been added to the buffer storage of one of the device channels. Since the read address counter counts the pulses from the highly stable reference oscillator 7, and the write address counter counts the pulses generated from the multiplied reproduced reference RFES signal subject to the instability of the carrier movement during playback, the digital code at the output of the code subtractor will be proportional to the changed carrier speed at reproduction. Using a digital-to-analog converter, this code is converted to an analog voltage and, through an output bus 52 for controlling the speed of the medium, is transmitted to the speed control unit (not shown in Fig. 1).

Recording on the carrier the sum of two reference signals on one channel of the device and the sum of the low-frequency reference signal and the information signal on the remaining channels eliminates the effect of inter-channel time shifts on the correction accuracy and, therefore, improves the accuracy of the correction of time distortions in each channel compared to a similar device 3-4 times. In addition, the lateral recording density is increased. Formula A is a device for multichannel magnetic recording and reproduction of signals with correction of time distortions, comprising a reference signal generator, a reference signal recording amplifier connected to a reference signal recording head, in each information signal recording channel, an information signal input bus connected through an information signal recording amplifier with an information signal recording head, a reference signal reproducing head 5 and a amplifier connected in series reproducing the reference signal, the output of which is connected to the input of the phase shifter, and in each channel for reproducing the information signal, there are sequentially connected the head for reproducing information signals, an amplifier for reproducing information signals, a delay line, a first low-pass filter, an analog-to-digital converter, a buffer storage, and digital-to-analog a converter and a second low-pass filter, an output bus, a first phase detector connected in series, a third low-pass filter, often t, the first adder, the first voltage-controlled oscillator, the first band-pass filter and the first pulse shaper, connected to the control inputs of the analog-digital output

5 a converter and a buffer storage device, a first frequency divider connected between the input of the first phase detector and the output of the first voltage controlled oscillator, the second phase detector,

0 connected by the output to the input of the fourth low-pass filter, and by one input to the output of the phase shifter. characterized in that, in order to increase accuracy, introduced for the recording channels of the reference signals

5 a second frequency divider and a fifth low-pass filter connected in series, a third frequency divider and a sixth low-pass filter connected in series to each recording channel of information signals — a second adder through which an input bus of information signals is connected to an input of an amplifier for recording information signals, reference signal recording channel - the third sum is 5 torr, connected to the input of the reference signal recording amplifier by one input and another by the output. the input of the second adder - to the output of the sixth lower filter their frequencies, another input - to the output of the first filter

0 low frequencies, and the inputs of the first and second frequency dividers are connected to the output of the reference signal generator and the clock

the input of the buffer drive of each channel of reproduction of information

5 signals, for the information signal reproducing channels, a seventh low-pass filter is connected in series, the input of which is connected to the output of the information signal reproducing amplifier from the carrier track adjacent to the reference signal recording track, a third phase detector, an eighth low-pass filter, a second generator, voltage-controlled, and a switch connected to another input of the first phase detector in each information signal reproduction channel by the output, the fourth divider a circuit connected between the output of the second voltage-controlled oscillator and the other input of the third phase detector, a ninth low-pass filter through which the output of the reference signal reproducing amplifier is connected to the input of the phaeo-amplifier, serially connected high-pass filter and a second pulse shaper, an output connected to the second input of the switch, a reference voltage source, a threshold block connected between the output of the reference voltage source and the third input of the switch,

dU-o3km- /

and another input connected to the inputs of the ninth low-pass filter and high-pass filter, and a control bus is connected to the additional output of the buffer storage device, a tenth low-pass filter connected between the input of the delay element and the other input of the second phase

detector, connected in series with a frequency detector, connected to the output of the second low-pass filter, a quadratic detector, an amplifier and an adjustable attenuator, the other input of which

connected to the output of the fourth low-pass filter, and the output to another input of the first adder in each information signal reproducing channel, and a second band-pass filter connected between the input of the second low-pass filter and the output bus.

1st channel of the information signal

1 .. t-th channel, information signal