RU1812516C - Adaptive device for frequency measuring - Google Patents

Abstract

The invention can be used in devices for measuring the frequency of quasi-determined signals. The purpose of the invention, improving the accuracy of frequency measurement, is achieved by that. that electronic switches, a clock, a waiting multivibrator, a voltage inverter, integrators, analog-to-digital converters, voltage modulators, comparator units, analog multipliers, reference voltage units, and a phase detector are introduced into the adaptive frequency measuring device. The device also contains a bandpass filter, a delay line, phase detectors, a phase shifter. 2 ill.

Description

The invention relates to techniques for radio measurements and can mainly be used in devices for measuring the frequencies of quasi-determined signals with a large dynamic range of amplitudes of the input signals, as well as for communication systems in automatic frequency control.

The purpose of the invention is to improve the accuracy of measuring frequency and quasi-determined signals with a small signal to noise ratio and an unknown dynamic range of amplitudes of the input signals.

In FIG. 1 is a structural diagram of an adaptive frequency measuring device; in FIG. 2 - time diagrams of voltages that explain the principle of operation of the device; in FIG. 3 is a discriminatory characteristic of an adaptive frequency measuring device.

By introducing the blocks of the first electronic key, the clock generator, time synchronization of the operation of all blocks of the device as a whole on the analysis interval is achieved, blocks of the multivibrator, second electronic key, voltage inverter, fourth electronic key, fifth electronic key and third electronic key integrators of the device and preparing them for the next clock cycle, the blocks of the fourth integrator and the second voltage module driver evaluate the amplitude the signal in the upper channel, and the third integrator and the first driver of the voltage module in the lower channel, which is a necessary operation for adapting the device, the blocks of the first and second comparators and reference voltages form the value of the quantized control voltage and thereby the installation of voltage quanta of the first and second analog-to-digital converters.

The adaptive frequency measuring device comprises in series a first electronic key 1, a strip

y eat

filter 2, delay line 3, the input of which is connected to the first input of the first phase detector 4 and phase shifter 5, the output of the delay line 3 is connected to the second inputs of the first 4 and second 6 phase detectors, the output of the clock generator 7 is connected to the second input of the first electronic key 1 and the inputs of the standby multivibrator 8, the second electronic key 9, the voltage inverter 10, the first output of the standby multivibrator 8 is connected to the input of the fourth electronic key 11, and the second output to the input of the fifth electronic key 12, the output is inv the voltage torus 10 is connected to the input of the third electronic switch 13, the output of which is connected to the second input of the second integrator 14, with the output of the second electronic switch 9 and the second input of the first integrator 15, the output of which is connected to the first input of the first analog-to-digital converter 16, the output of the first 4 of the phase detector is connected to the first input of the fourth integrator 17, the output of which is connected to the input of the second driver of voltage module 18, the output of the second phase detector 6 is connected to the first input of the third integrator 19, the output of which is connected to the input of the first driver of the voltage module 20, the second inputs of the third 19 and fourth 17 integrators are connected to the parallel connected outputs of the fourth 11 and fifth of 12 electronic keys; the output of the first driver of voltage module 20 is connected to N inputs of the second block of comparators 21, and the output of the second driver of voltage module 18 is connected to N inputs of the first block of comparators 22, N outputs of which are connected to N inputs of the m-address first analog multiplexer 23, N outputs the second block of the reference voltage 21 is connected to N inputs of the second analog multiplexer 24, to the information inputs of which are connected N outputs of the second block of the reference voltage 25, N outputs of the first block of the reference voltage 26 are connected to the information ion inputs of the first analog multiplexer 23, whose output is connected to a second input of the first analog-to-digital converter 16; the output of the second integrator 14 is connected to the first input of the second analog-to-digital converter 27, the second input of which is connected to the output of the second analog multiplexer 24, the outputs of the first 23 and second 27 analog-to-digital converters are connected to the first AND second inputs of the third phase detector 28.

The device operates as follows.

An input signal that is a continuous quasi-harmonic oscillation

n (twfumBxcos (+ y)., Tc. 1o ,, Tc

where is the input signal amplitude, d) p is its central frequency and initial phase,

We assume that UmBX 6 UmexmlrvLWrn,% with G ftfccmln. COocmax P 6 - I, Jl.

The input signal arriving at the first electronic switch 1, where it is formed using a frequency synthesizer, which is tuned with frequency steps equal to the bandwidth of the band-pass filter (2), and with an intermediate frequency equal to the center frequency of the band-pass filter (2), the duration of the frequency analysis the step is equal to Ta Tc - and coincides with the duration of the time gates of the clock pulse generator 7 (a) entering the second input of the electronic key (1). Since the input part, consisting of a synthesizer and mixer, is inherent in all single-channel frequency measuring devices operating in

a wide range of frequencies, then these blocks in the structure of the device are not entered. At the same time in the bandpass bandpass filter 2 may be present no more than one signal. After bandpass filtering in 2 signal

arrives at the first input of the first phase detector 4 and has the form

u1Fd (g) um1 {sb8 ((Vos1), t (0, Tc).:,. and to the first input of the second phase detector 6 through the phase shifter to

UafDU Um2 COS ((Woe t ++)

 Umasin (Woc t 4- # 2).

In order to form a discriminatory characteristic, Uex (t) enters the delay line 3 with the delay value Тлз, the value of which is selected from the condition that Глс is longer than the correlation time of the interference, but less than the correlation time

taking into account a given band of a band-pass filter 2. After that, at the second inputs of the first phase detector 4 and the second phase detector 6, we respectively obtain:

U30A (t) Um3COS (ftloc (t + ГЛЗ) + (), Щфдф ((t + Тле) + 0 Then the response of the first 4 and second 6 phase detectors is equal, respectively:

CBfd UmsCOS (Woe Тлз. Ubfd UmoSln Woe Тлз Transmission coefficients 4 and 6 are chosen so that Um5 Ume. Then after the first 15 (e) integrator and the second integrator 14 (f) we get

UMHTI Ta Um2 COS Ufcc pz, UnHT2 TaUm2Sln ftJoc pz,

taking into account that the impulse response of the ideal integrator is 1 / Ta, then

UHHTI UmCOS Wbc ls. 11int2 UmsSin OJoc TLS

At the same time, the signal from the clock generator is fed to the input of the second electronic key 9 (c), which is closed during the operation of the first 15 and second 14 integrators Ta, after inverting to 10 (b), the third electronic key 13 (d) opens for the recovery time of the first 15 and second 14 integrators. Thus, the blocks 9, 10, 13 provide the timing of the operation of the integrators 14.15: at the time points Ta, the integrators 14 and 15 integrate, and at the time TB are restored. Obviously, those are “Ta. To ensure adaptation of the dynamic range of the discriminatory characteristic, a simultaneous estimation of the amplitude is performed. For this, the voltage from the output of the first 4 and second 5 phase detectors is supplied to the third 19 and fourth 17 integrators with constant integration TI2 THI Ta, i.e. at the output of the fourth and third integrators, we have

U4M Ti4 Um4COS Woe lz i iZi - Teese Um3 S-ln OJoc Tle,

where Um4 is the amplitude estimate. Um3 estimate of the amplitude of Um2- at Т $ $ Тиз ТИ2

 That. Um4 and Um3 are the same as Um2- BUT DISP there are more estimates in this case, because the constant integration of the third and fourth integrators is less than the constant integration of the first and second integrators. The fulfillment of the condition TI2 Ta in principle, because his message makes it possible to obtain an estimate of the amplitude faster in time and thereby provide the necessary time for adaptation and analysis of the device. Taking into account the impulse response of an ideal integrator, we obtain

1) 4 and Um4COS (the TP, U3M Um3SinCOocTn3.

Since 1) 4i and Uzi, depending on the value of QJoc, they can have different signs, then a modular evaluation of the amplitude occurs. todes, i.e. at the output of the units for forming the voltage module 20 and 18, we obtain, respectively

UB 11Mi 1 IUm4COS LcTls,

UH | U3Hl lUm5 81p MosGlz1 i

where I I denotes the operation of forming the module. The work of the integrators, the third 19 and the fourth 17, are synchronized by the clock generator 7.

Timing diagrams showing the synchronization of processes in time are shown in FIG. 2, where the standby multivibrator 8 (g) is triggered by a rising edge

pulses in the clock generator 7; the signal from one shoulder of the waiting multivibrator (g) opens the fourth electronic key 11 (s), and from the other shoulder closes the fifth electronic key 12 (k) and

5 thereby controls the turn-on time of the integrators 19 (l) and 17 (m) and their reset. The outputs of the blocks forming the voltage module 20 and 18 are connected to the N inputs of the first block of comparators 22 and second

0 of the comparator unit 21, the first and second comparator units 21, 22 depending on the magnitude of UB and UH, which are compared with the voltage Uoi - .. Uo2, Uo2 ... Uo3. UON-I ... UON and issue a logical unit on one of

5 inputs of the analog multiplexer 23 (24), for example, if block 22 (g) worked, then the following code will be on the outputs of the comparator 22 0100, .. 0, then the voltage from the block will be output 23 (the first block of the reference voltage ) proportional to the estimate of the signal amplitude. The lower channel works similarly. Moreover, the number of voltage levels of the second block of reference voltages 25 and the first block of reference

5 voltage 26 is selected from the condition of an allowable error of approximation of the discriminatory characteristics (Fig. 3 and) of a given input dynamic range of amplitudes. The number of gradations of the reference

The voltage 0 of blocks 25 and 26 is equal to the number of comparison levels of comparators 21 and 22.

Thus, the output of the first analog multiplexer 23 is generated from the first block of reference voltages 26

5, a control signal that is input to the installation input of the first analog-to-digital converter 16, as a result of which the dynamic range 16 (Fig. 3) is adapted to the signal level with

0 output of the first integrator 15, proportional to the measured frequency. Similar operations take place in blocks 21,24,25 and 27. As a result, in the third phase detector 28, the responses of the first 16 and second 27 analog-to-digital converters are divided and a functional transformation of the arctangent type takes place.

The beneficial effect of the invention is as follows.

When measuring the center frequency of the signals about a, in a wide instantaneous band of Ohms, it is of great interest to receive weak signals when the input signal-to-noise ratio in power

„PVC NmAfn

where Pc is the signal power;

he 2 Nm Afn is the interference power. The root-mean-square error of estimating the frequency of harmonic signals is defined as

 .

qA;

2AGLZOD

dvkh2UDtpta V1 + 2qBX2

TLS is the delay time in the delay line;

Ta is the time of integration (analysis).

In order to reduce the influence of the input signal Pc on the error value 7f, various normalizations are used, for example, a limiter or amplifier with AGC at the input of autocorrelation frequency discriminators or a quadrature processing device with a quadrature component division device. However, the use of a limiter or amplifier with AGC for normalization is advisable only at qBx2 1. When the stabilization of the signal level Pc is still ensured. Since at qBx2 1 the stabilization level is determined mainly

noise power b2 and at the output of the limiter the signal-to-noise ratio qubix

2

 pct, then the effect is not eliminated

signal level at 0g, which makes such an operation unacceptable.

Normalization using quadratures and a divider is more suitable, since the division operation is carried out after integration, which significantly reduces the effect of noise. A drawback of this normalization option is the occurrence of significant hardware errors due to a zero drift in the DC amplifier, which are used to increase the effect level at the integrator output. To eliminate this drawback, it is advisable to use an analog-to-digital converter after filtering the voltages at the output of the phase detectors of the autocorrelation frequency discriminator with quadrature processing, which can significantly reduce the hardware error

input of an adaptive frequency measuring device.

In FIG. 3 shows a positive branch of discriminatory characteristics,

implemented on an analog-to-digital converter. Given the dynamic range D Umax - Umin in the frequency band fmax and the value of the permissible error, approximately equal to Лпах, the outcome

from the value of Umin determine Amin. Due to the fact that when receiving weak signals qex2 1 at the output of qewx2 qux phase detectors. those; a threshold effect is manifested, which leads to a broadening of the output dynamic range compared to the input dynamic range. This circumstance with a fixed step and the number of bits of the ADC leads to an increase in the methodological error due to the inconsistency of the quantization step and the permissible change in the signal level. In the proposed adaptive frequency measuring device, a rapid evaluation of Pc and measurement of the quantization step are carried out, ensuring guaranteed accuracy of the frequency measurement. For example, if D is 2.56 V, the number of bits is pr 8, i.e. the number of levels is 28 256, then D U 2.56

256

 0.01V 10mV npifl steepness discrete5

0

5

0

5

the response characteristic S - D / fmax (fmax 256 kHz, S 0.01 V / kHz); those. 10 mV corresponds to 1 kHz, thus the accuracy of the frequency measurement is 1 kHz. If the dynamic range is reduced by 10 times, i.e. D 0.256 V, then at pr 8, m 256, AD 10 mV S 0.001 V / kHz, hence the increase in error is 0.01 / 0.001 10 times. If the slope is adapted with a simultaneous estimation of Pc, then an increase in the error in measuring the frequency does not occur over the entire allowable dynamic range of amplitudes of the input signals.

Formula Adaptive frequency measuring device comprising a first phase detector, a second phase detector, a delay line, a band-pass filter, a phase shifter, a delay line output connected to the second inputs of the first and the second phase detectors, the phase shifter output is connected to the first input of the second phase detector, the input is connected to the output of the bandpass filter and the input of the delay line, the output of the bandpass filter is connected to the first input of the first phase detector, characterized in that, in order to increase

accuracy of frequency measurements, the first, second, third, fourth and fifth electronic keys, a clock generator, a standby multivibrator, a voltage inverter, the first and second, third and fourth integrators, the first and second digital-to-analog converters, the first and second drivers are introduced into it voltage module, first and second analog multiplexers, first and second reference voltage blocks and a third phase detector, the input of the first electronic key being the input of the device and the output connected to the input of the strip filter, the output of the clock generator is connected to the input of the standby multivibrator and the inputs of the second electronic switch and inverter, the output of the first phase detector through the first integrator is connected to the first input of the first analog-to-digital converter and directly to the first input of the fourth integrator, the output of the second phase detector through the second integrator connected to the first we enter the second analog-to-digital converter and directly with the first input of the third integrator, the outputs of the fourth and fifth e ics keys are combined and connected to the second inputs of the third and fourth integrators, a first output monostable multivibrator coupled to the input of the fifth electronic

key, and the second output is with the input of the fourth electronic key, the output of the third electronic key is connected to the second inputs of the first and second integrators and the output 5 of the second electronic key, and the input is with the output of the voltage inverter, the inputs of the first and second voltage module shapers are connected respectively with the output of the third integrator and the output

0 of the fourth integrator, the outputs of the first and second shapers of the voltage module are respectively connected to the inputs of the second and first blocks of the comparators, the information inputs of the first analog

5 multiplexers are connected to the outputs of the first block of reference voltages, and the control inputs are connected to the outputs of the first block of comparators, the information inputs of the second analog multiplexer are connected to the outputs of the second block of reference voltages, and the control inputs are connected to the outputs of the second block of comparators, the output the first analog multiplexer is connected to the second input

5 of the first analog-to-digital converter, and the output of the second analog multiplexer is connected to the second input of the second analog-to-digital converter, while the first and second inputs of the third phase detector are connected to the outputs of the first and second analog-to-digital converters, respectively.

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