RU1793389C - Digital phase meter for determining rotor unbalance phase - Google Patents

Description

VI Yu

OJ CJ 00

Yu

2

The invention relates to measuring technique and can be used for non-contact measurement of the phase imbalance of rotors, including rotors of motor bearings rotating in a non-contact gas-magnetic suspension.

The closest known one is a digital phase meter with a constant measuring time, containing two drivers, the inputs of which are inputs of the phase meter, a trigger with separate inputs connected to the outputs of the drivers, a counter whose input is connected to the trigger output via two matching circuits, a generator pulses, the output of which is connected to the control input of the first matching circuit, the time is the master frequency divider, the input is connected to the output of the master oscillator, and the output is with the control input of the second circuit coincidence. - --i::;

A disadvantage of the known digital phase meter is the low reliability of measurements in the non-contact determination of the initial position of the rotor by an optoelectronic sensor with reflection of the optical beam due to the fact that optical inhomogeneities on the rotor surface (scratches, roughness, abrasions, glare, etc.) are perceived by the sensor as false marks and distort the measurement results /

An object of the invention is to increase the reliability of determining the phase of rotor imbalance by selecting signals in a reference channel.

This goal is achieved by the fact that in the digital phase meter containing the first and second drivers, the first trigger, the first and second logic gates And, the pulse generator, the time setting of the divider and the first binary counter, an optoelectronic sensor for the initial position of the rotor connected to the input of the first driver is entered, consisting a compensation unit from a diode photodetector connected through a first resistor to a power source and a diode emitter connected through a second resistor to an output of a pulse generator the phase shift of the selector and the signal selector, the first input of which is connected to the output of the first driver, the second input is the output of the pulse generator, and the first output is the first input of the first trigger, the second input of which is connected to the output of the phase shift compensation unit, the first input of which is connected with the output of the second driver, the second input with the output of the pulse generator, the third, fourth and fifth inputs, respectively, with the first, second and third inputs of the signal selector.

In FIG. 1 is a functional diagram of a digital phase meter for determining the phase of rotor imbalance; Fig. 2 is a functional diagram of a signal selector; in FIG. 3 is a functional diagram of a selector phase shift compensation unit; on the

FIG. 4 is a timing chart.

The digital phase meter for determining the phase of rotor imbalance (Fig. 1) contains a first driver 1, connected via an input to an optoelectronic sensor 2 of the initial rotor position, namely a diode photodetector 3, through a first resistor 4 connected to a power source and optically coupled to 5 diode emitter, sequentially

0 connected to the second resistor 6, the second driver 7, the pulse generator 8, the signal selector 9, equipped with two inputs 10 and 11 and three outputs 12,13,14, and the first input 10 of the selector 9 is connected to the output of the first driver 1, and the second its input 11 is connected to the output of the pulse generator 8 and to the second resistor 6 of the optoelectronic sensor 2. block 15 compensation of the phase shift of the selector,

0 equipped with five inputs 16, 17, 18, 19, 20 and one output, and the first input 16 of block 15 is connected to the output of the second driver 7, its second input 17 is connected to the output of the pulse generator 8, the third

5 18, the fourth 19 and fifth 20 of its inputs are connected respectively to the first 12, second 13 and third 14 outputs of the signal selector 9, the first trigger 21, S-input connected to the first output 12 of the selector 9

0 signals and an R-input connected to the output of the selector phase shift compensation unit 15, a time divider 22, an input connected to the output of the 8 pulse generator, the first two-input logic element And 23, the first input connected to the direct output of the first trigger 21 and the second the input - with the output of the 8-pulse generator, the second two-input logic element AND 24, the first input connected to the output of the first logical element And 23, the second input - the output time of the master divider 22, and the output - the path C-input of the first binary 25 counter.

5 The signal selector 9 (Fig. 2) contains the third two-input logic element And 26, the first and second inputs of which are respectively the first 10 and second 11 inputs of the selector 9, the first logic element is FORBID 27, the direct input is connected

Gnn with the output of the third logical

element And 26, the second binary counter 28, a clock C-input connected to the output of perzogo logic element 27 FORBIDDEN,

1 P-transfer path connected to the other input of this element, the first ode to

a novibrator 29, the input connected to the output of the transfer of the second binary counter 28, the fourth multi-input logically them in two

Bbin

house

) element And 30, inputs connected to

second outputs of bits of the second

4-point counter 28, D-trigger 31, with the input connected to the second third logical element And 26, and

ins | a D-input connected to (its inverse output, the third binary counter 32, a С-input connected to the direct output of the O-trigger31, an installation R-input connected to the DM output of the third logical element And 26, and a P-transfer output connected to installation R-input of the second binary counter a 28, and the output of the first one-shot 29 is the first output

top

12 selectors 9 signals, the output of the four-25 logical element And 30 - its second

output 13, the output of the third logical element And 26 -4 its third output 14.

The phase shift compensation unit 15 of the selector (Fig. 3) contains a reverse counter 33, a second RS trigger 34, the S input of the Dporo cat is the first input 16 of block 15, the installation R input is connected to the output of the P transfer of the reverse counter 33, IE the output is connected to the control input U of this counter, the direct output is connected to the first input of the fifth two-input logic element And 35, the second input of which is the second input 17 of block 15, and the output is connected to the first input flON of the first logic element OR 36, output connected to the clock C-input roar a counter 33, the second input connected to the output of the sixth two-input logic element AND 37, the first input of which is connected to the direct third RS-flip-flop 38, the installation R-input of which is connected to the output of the second logical element OR 39, the first and second inputs of which are the third 18 and fourth 19 inputs of block 15, respectively, and the S-input of the third RS-Trigger 38 is the fifth input 20 of this block, the seventh two-input logic element AND 40, the output connected to the fixed R-input of the reverse counter 33 first entry it is connected to the direct output of the fourth RS-flip-flop 41, the installation R-input of which is connected to the nef input of the second logical element OR 39, the S-input is connected to the output of the second logic element BAN 42, the direct input of which is connected to the S-input of the third RS flip-flop 38, and the inverse input is connected to the direct output of the fourth RS flip-flop 41, the second one-shot 43, the input connected to the P-transfer output of the reverse counter 33, and the output of the second one-shot 43 is the output of block 15, the second input of the sixth logic element And 37 with union of a second input of the fifth AND gate 35, the second input of the seventh AND gate 40 is connected to a second input of the second OR gate 39,

As an example in FIG. 4 shows true mark 44 and false marks 45, 46.

Digital phasometer works as follows.

The radiation flux of the diode emitter 5 of the optoelectronic sensor 2, modulated by the frequency of the 8 pulse generator, is reflected by the diode photodetector 3 when reflected from the true mark 44. The electrical signals of this signal, which are fed to the input of the former 1, provide the output of the last series of pulses whose frequency coincides with the frequency generator 8 pulses, and the duration of the series is determined by the duration the label 44 passes the zone of the optoelectronic sensor 2. This series of pulses is fed to input 10 of the signal selector 9 , Which is the first input of the third AND gate 26. The pulses of the generator 8 are received at the second input of this element, which is the second input 11 of the signal selector 9. The third gate And 26 passes only those pulses from the series arriving at its first input that match in time with the pulses of the generator 8, modulating the radiation of the diode emitter 5 (see Fig. 4). Thus, random signals excited by interference and not coinciding with the pulses of the generator 8 are suppressed by the third AND gate 26.

From the output of the third logical element AND 26 of a series of pulses through the first logical element, the PROHIBIT 27 is supplied to the clock C-input of the second binary counter 28, whose capacity is less than the number of pulses in the series, determined by the frequency TGN of the 8 pulse generator, with an angular size of o. reflective marks on the rotor and the rotational speed n of the rotor, and can be found from the relation

M gfGN

When the second binary counter 28 is filled, at its output of the P-foam, a signal appears that starts the first single-vibrator 29, the pulse at the output of which is the first output 12 of the signal selector 9, corresponds to the passage by the label 44 of the zone of the optoelectronic sensor 2, but shifted in phase relative to the start of the label (see Fig. 4). At the same time, the signal from the P-transfer output of the second binary counter 28 is fed to the inverting input of the first logic element BAN 27, prohibiting the further passage of signals through this element and blocking the operation of the second binary counter 28.

The second binary counter 28 is reset to the zero state by the third binary counter 32, whose clock input C through the D-flip-flop 31, which is a frequency divider, is connected to the second input of the third logical element And 26 (with the output of the 8 pulse generator), and the installation R-input is connected to the output of the third logical element And 26. When passing through the last series of pulses, the pulse frequency at the R-input of the third binary counter 32 is twice the pulse frequency at its clock C-input, therefore this counter does not may t fill up. At the end of the series of pulses at the output of the third AND gate 26, the third binary counter 32 ceases to be reset to the zero state and is filled with pulses arriving at its clock (counting) C input. When the third binary counter 32 is filled, the signal from its P-transfer output is fed to the installation R-input of the binary counter 28, resetting the latter to the zero state and preparing the signal selector 9 for further operation. In this case, a signal appears at the output of the fourth logical element And 30 (at the second output 13 of the signal selector 9), which is a decoder of the zero state of the second binary counter 28.

The duration of false signals due to reflecting optical inhomogeneities on the surface of the rotor (false mark 45 of Fig. 4) is much shorter than the duration of true signals corresponding to mark 44 on the rotor. Therefore, a series of pulses at the output of the third logical element And 26 when passing false signals is much shorter than a similar series when passing true signals, and therefore the second binary counter 28 cannot be filled when passing false signals and at the output 12 of the selector the signal is not detected is.

If the time interval between the end of the false and the beginning of the true signal is less than the filling time of the third binary counter 32, the second binary counter 28, after passing the false signal, is not reset to zero, and the information recorded therein leads to a random phase shift of the signal by the output P-transfer of the second binary counter 28 and the output of the first one-shot 29.

The first of a series of pulses appearing at the output of the third logical element And 26, which is the third output

5 14 of the signal selector 9, entering the fifth output 20 of the selector phase shift compensation unit 15, which is the S-input of the third RS-flip-flop 38, sets the latter to a single state,

Logic level 0 from the direct output of this trigger goes to the first input of the sixth logical element AND 37, allowing passage through the second input of the last, which is the second input of block 17

5 15 compensation of the phase shift, the pulses of the generator 8, which through the first logical element OR 36 are fed to the clock C-input of the reverse counter 33. In this case, the second RS-trigger 34 is located in

0 to the zero state, and the logic level 1 from its inverse output, arriving at the control input U of the reverse counter, provides filling of this counter with pulses arriving at its clock input C (in the summing mode),

At the same time, the first of a series of pulses at the output of the third logical element And 26 through the third output 14 of the signal selector 9, the fifth input 20 of the phase shift compensation unit 15 and the second logic element is PROHIBITED 42 is fed to the S-input of the fourth RS-flip-flop 41, setting it to single state. Logic level 1 from the direct output of the fourth RS5 trigger 41 is fed to the inverting input of the second logic element, FORBID 42, blocking the further passage of pulses through this element, and to the first input of the seventh logical element AND 40,

0 allowed the passage through the last signal of the zero state of the second binary counter 28 formed by the fourth logical element AND 30.

If a series of pulses at the output of the third5 of its logical element And 26 is caused by a false signal of sensor 2 (false label 45, Fig. 4), the second binary counter 28 is reset to zero before filling, and the signal of its decoder is zero (fourth logical element And 30) through the fourth

the stroke 19 of the block 15 compensation of the phase shift of the selector is fed to the second input of the Seventh logic element And 40. resetting the reverse counter 33 and (through the second logic element OR 39) to the R-input of the third RS-flip-flop 38, setting the latter to the zero state and prohibiting the passage of the pulses of the generator 8 to the clock C-input of the reverse counter 33.

If a series of pulses at the output of the third AND gate 26 is caused by the true signal of the sensor 2 (true label 44 of Fig. 4), the second binary counter 28 is filled. a signal arriving at its R-transfer output and at the output of the first one-shot 29 arrives (through the first output 12 of the signal selector 9 and the third input 18 of block 15) to the R-input of the fourth RS flip-flop 41, setting it to zero V prohibiting thereby resetting to zero the reverse counter 33, and (through the second logical element OR 39) to the R-input of the third RS-flip-flop 38, setting it to zero and prohibiting the passage of the pulses of the generator 8 to the clock C-input reversible counter 33. Thus, the true signal of the sensor 2 OEC prints a parallel write to the second binary counter 28 and the reverse counter 33 (in the summing mode) of the same binary number, after which both counters are stopped, the output of the first of them shows a signal that has a phase shift relative to the beginning of the true tag , and the second of them stores information on the magnitude of this phase shift.

If the true signal of sensor 2 is interrupted by an optical inhomogeneity on the reflective mark (false mark 46. Fig. 4), then the series of pulses at the output of the third logic gate And 26 is interrupted for the duration of the false mark 46. When this occurs, the second binary counter1 stops 28 without resetting it to the zero state and continuing the counting with the second binary .1m counter 28 after restoring the pulses at the output of the third logical element And 26 (after passing the false label 46). In this case, the phase shift of the signal of the first one-oscillator 29 relative to the beginning of the true mark 44 is increased by the stop time of the second

ds

personal counter 28. The reversing counter to 33 starts in the summing mode

Oh

.with the second binary counter 28 and stops by the re-signal of the latter, and the reverse counter 33 does not stop during the intermediate stop of the second binary counter 28. Thus, the binary number written to the reverse counter 33 at the time of its stop exceeds the binary number, recorded in the second binary 5 counter 28, by the number of pulses received on the clock input of the reverse counter 33 during the intermediate stop of the second binary counter 28 with a false mark 46, and the binary the number recorded in the reversible counter 33 corresponds to the phase shift of the transfer signal of the second counter 28 and the signal of the first single-vibrator 29 relative to the beginning of the true mark 44.

5 The imbalance signal, coming through the second driver 7 to the first input 16 of the phase shift compensation unit 15 of the selector and to the S-input of the second RS-flip-flop 34, puts this trigger into a single state 0. In this case, the logic zero level from the inverse output of the second RS flip-flop 34, entering the control input U of the reverse counter 33, puts this counter into subtraction mode. Simultaneously level

5 logical 1 from the direct output of the second RS-flip-flop 34, entering the first input of the fifth logical element And 35, allows passing through this element and through the first logical element OR 36 pulses 0 of the generator 8 to the clock C-input of the reverse counter 33. After subtracting from the reversible counter 33 the number of pulses recorded in it in the summing mode at the P-transfer output of this

5 of the counter, a signal appears that enables the second RS-flip-flop 34 to be brought into a zero state, than the selector phase shift compensation unit 15 is prepared for further work, and triggering

0 second one-shot 43. In this case, the phase shift of the output pulse of the first one-shot 29 relative to the beginning of the true mark 44 (relative to the signal of the sensor 2 of the initial position of the rotor) and phase

5, the shift of the output pulse of the second one-shot 43 relative to the imbalance signal supplied to the input of the second driver 7. are the same.

The pulse of the first one-shot 29, the output of which is the first output 12 of the signal selector 9, is fed to the S-input of the first trigger 21 and puts it in a single state. In this case, the logic level is 1 from the direct output of the first trigger

5 21 enters the input of the first logical element And 23, allowing passage through its second input and through the second logical element And 24 pulses of the generator 8, arriving at the clock C-input of the first binary counter 25, and the time zadayuschego divider 22, the input connected to the output of the generator 8. pulses, and the output connected to the second input of the logic element And 24, provides the formation of a constant measurement time.

The pulse of the second one-shot 43, the phase shift of which in relation to the pulse of the first one-shot 29 is equal to the phase of the rotor unbalance, enters (through the output of the phase shift compensation block 15 of the selector) to the R-input of the first trigger 21, transferring the latter to the zero state and prohibiting further passage of the Inventions 1. A digital phase meter for determining the phase of rotor imbalance, comprising the first and second formers, the input of the last of which is the measuring input of the phase meter, the first trigger, the first and second logs the logical elements And, a pulse generator, connected to the input by the time of the master divider, and the first binary counter, the direct output of the first trigger connected to the first input of the first logical element And, the second input of which is connected to the output of the pulse generator, and the output to the first input the second logical element And, the second input of which is connected to the output by the time of the master divider, and the output - with the counting input of the first binary counter, characterized in that, in order to increase the reliability of determining the phase of the rotor unbalance and by selecting signals in the reference channel, an optoelectronic rotor initial position sensor connected to the input of the first driver is introduced into it, consisting of a diode photodetector connected through a first resistor to a power signal source, and a diode emitter connected through a second cut br with the output of the pulse generator, a phase shift compensation unit for the selector and a signal selector, the first input of which is combat with the output of the first driver, the second input of which is with the output of the pulse generator, and the first output - to the first input of the first flip-flop, a second input coupled to the output of the phase shift compensation selector having a first input connected to the output of the second shaper, the second input - with the output of the pulse generator, third, fourth and fifth outputs of respectively the

pulse generator 8 to the clock C-input of the first binary counter 25. In this case, the information recorded in the first binary counter 25 corresponds to the phase of the rotor unbalance.

Thus, the introduction of a signal selector and a selector phase shift compensation unit makes it possible to isolate the true and suppress false signals of the optoelectronic sensor of the initial position of the rotor, thereby increasing the reliability of measuring the phase of the rotor unbalance, the object of the invention is achieved and its positive effect is achieved.

....

with the first, second and third outputs of the signal selector.

2. The phasometer according to claim 1, with the fact that the signal selector contains the third and fourth logical elements AND, the second and third binary counters, the first one-shot, the first logic element is FORBID and the D-trigger whose clock input is connected to the second input of the third logical element AND, the first and second inputs of which are the first and second inputs of the selector respectively, the first output of the signal selector is the output of the first one-shot, the input of which is connected to the P-transfer output of the second binary counter inverse the binary outputs of which are connected to the corresponding inputs of the fourth logical element AND, the output of which is the second output of the signal selector, the third output of which is connected to the output of the third logical element AND, with the direct input of the first logical element is FORBID and with the setting R-input of the third binary counter, the transfer output P of which is connected to the installation R-input of the second binary counter, the clock C-input of which is connected to the output of the first logic element BAN, inverse input cerned connected to the input of the first monostable multivibrator, counting the C-input of the third binary counter connected to the direct output of D-flip-flop, an inverse output of which is connected to its D-input information.

3. The phasometer according to claim 1, with the fact that the selector phase shift compensation unit contains a reversible counter, the fifth, sixth and seventh logic elements AND, the second logic element is FORBID, the second, third and fourth

RS triggers and a second one-shot. ESCHEDO which is the output of the unit, and the input is connected to the transfer output P of the reverse ego counter and the installation R-input of the second RS-flip-flop, the first S-input of which is the first input of the block, the direct output of the second RS trigger connected to the first

the soda of the fifth logical element AND, the second input of which is connected to one of the inputs of the sixth logical element And and is the second input of the block, the outputs of the fifth and sixth logical elements AND are connected respectively to the inputs of the first logical element OR, the output of which is connected to counting C-input of the reverse-t gs counter, the control input of which is connected to the inverse output of the second R 5 trigger, and the installation R-input is connected to the output of the seventh logical element And,

the first input of which is connected to the direct output of the fourth RS-trigger and the inverting input of the second logic element is FORBID, the output of which is connected to the installation S-input of the fourth RS-trigger, the installation R-input of which is the third input of the block and connected to the first input of the second OR gate, the second input of which is the fourth input of the block and connected to the second input of the seventh logical element AND, the direct input of the logic element is FORBID is the fifth input of the block and is connected to the installation S-input the third RS-flip-flop, the installation R-input of which is connected to the output of the second logical element OR, and the direct output - to the second input of the sixth logical element I.