RU1789970C - Step engine multichannel control device - Google Patents

Abstract

The invention relates to automation and can be used in automated control systems. The aim of the invention is to expand the scope. For this purpose, a device containing a system data bus, a control unit for the windings of stepper motors, control controllers, each of which contains a program control unit, a read-only memory program block, the first and second programmable timers, a parallel control interface, a command register, a register is entered statuses, interrupt controller, system controller, address decoder, random access memory block and AND-NOT group of elements. In the device, one controller simultaneously controls three stepper motors, and at the same time six or more in complete autonomy and with high speed. 7 silt. 1 tab.

Description

With

with

The invention relates to automation and can be used in automated control systems based on digital computers or microprocessor sets.

A multi-channel device for controlling stepper motors is known, comprising a system data, address and control bus, a control interface adapter (register), a comparison unit, a step counter, a decoder, two triggers, a pulse generator, an NAND element, the interface adapter being connected first outputs bit with the first inputs of the comparison unit connected by the second input to the output of the pulse counter, the pulse generator is connected by the output to the first input of the AND-NOT element,

connected by the output to the output of the pulse counter, and the second input to the output of the first trigger connected by the first input to the Run bus, and the second input to the output of the comparison unit and the first input of the second trigger connected to the output from the Ready bus, and the second input to with the Record bus and with the first input of the interface adapter.

The disadvantage of such a device is the inability to simultaneously control two or more stepper motors, since the number-pulse code from the control interface is processed only by the motor whose number is indicated in the control word.

Closest to the proposed solution is a multi-channel device XI 00

h y

3

in for controlling stepper motors, comprising a system data bus, addresses and controls, a control interface, control units of the windings of the stepper motors. The control interface is multi-channel, each channel of which includes a programmable input / output unit for parallel information and a programmable timer. The program, mirrored input / output blocks of parallel information with the corresponding inputs are connected to the system bus. In each control channel, a program control unit, a memory unit, a second programmable timer, a reception register, the information inputs of which are connected to the corresponding outputs of the first programmable timer and a programmable input-output block of parallel information, and the outputs of the reception register and memory unit are connected to information the inputs of the program control unit, the outputs of which are connected to the control inputs of the second programmable timer, the first output of which is connected to the synchronization inputs and the first programmable timer and with one information input of the reception register, the second output - with the other information input of the reception register, the third output - with the control input of the first channel of the second programmable timer, with the information input of the programmable input-output block of parallel information and with the system bus.

In this device, each channel of the control interface, hereinafter referred to as the control controller, serves only to work out the number of steps entered from the system bus into the first programmable timer. All parameters determining the operation of the stepper motor are entered from the side of the system bus. The controller can control only one drive at a time, the law of acceleration and braking of the stepper motor is hard-coded in the controller ROM.

The aim of the invention is to expand the scope of application.

To achieve this goal, a device containing a system data bus, a control unit for the windings of stepper motors, control controllers, each control controller comprising a program control unit, a read-only memory block, first and second programmable timers, a parallel control interface, a command register , state register, interrupt controller, system controller, address decoder, random access memory block, group of AND-NOT elements, and synchronization inputs of the first timer are connected with the clock output of the program control unit, the control inputs of the first timer are connected to the control inputs of the second timer and to the first group of outputs of the parallel control interface, the outputs of the first timer are connected to the synchronization inputs of the second timer, to the first group of interrupt request inputs of the interrupt controller and the first group the inputs of the block of elements AND NOT, the outputs of the second timer are connected to

5 by the second group of interrupt request inputs of the interrupt controller and the second group of inputs of the NAND block of elements, the third group of inputs of which is connected to the second group of outputs of the parallel control interface and are the first group of outputs of the control controller, which are connected to the group of enable inputs of the control unit of the step windings engines, the outputs of the block of elements AND NOT

5, the third group of outputs of the parallel interface are, respectively, the second and third groups of outputs of the control controller, which, respectively, are connected to the groups of clock inputs and

0 select the direction of the control unit of the windings of stepper motors, the interrupt request output of the interrupt controller is connected to the system controller of the same name, read and write outputs

5 program control blocks are connected to the inputs of the system controller of the same name, the output of the system controller is written to the memory connected to the write control input of the RAM block,

0 system controller output Reading from the memory is connected to the inputs of the RAM and read-only memory blocks of the same name, the output of the system controller is written to the input devices5 output is connected to the inputs of the interrupt controller, the first and second timers, the parallel control interface and the state register, output a system controller reading from an I / O device is connected to the inputs of the interrupt controller, the first and second timers, the parallel control interface, and the com register ND inputs Register selection device commands and register

5 states are connected to the first output of the address decoder, the remaining outputs of the address decoder are connected to the corresponding inputs. Selection of the device of RAM and read-only memory blocks, interrupt controller, first and second timers, parallel control interface, the corresponding outputs of the bits of the address of the program control block are connected with address inputs of RAM and read-only memory blocks, interrupt controller, parallel control interface, first and second timers, with address inputs by the address decoder, the control inputs of the address decoder are connected: one to the unit potential bus, the other two to the zero potential bus, the outputs of the data bits of the program control unit are connected to the inputs of the bits of the data of the system controller, the outputs of the bits of the data of which are connected to the outputs a block of read-only memory of the program, register of commands and with inputs of bits of data of the block of random-access memory, controller of interrupts, first and second timers, parallel control interface and state register, output of the signal, the strobe of the program control unit is connected to the input of the system controller of the same name, the outputs of the bits of the state register data and similar inputs of the command register are connected to the system bus to which the input of the register of the command register and the input of reading the state register are connected.

In the inventive multi-channel device, one controller simultaneously controls three stepper motors, and not simultaneously six or more, in the mode of complete autonomy and with high speed.

In FIG. 1 shows a structural diagram of a device; in FIG. 2 is a schematic diagram of a command register 1 and a state register 2; in FIG. 3 is a schematic diagram of a program control unit 3, a system controller 4, and a decoder 5; in FIG. 4 is a schematic diagram of a random access memory block and a read-only memory program block; in FIG. 5 is a schematic diagram of an interrupt controller, programmable timers, a parallel control interface, a group of AND-NOT elements; in FIG. b - an enlarged structural diagram of the programs of work of the control controller; in FIG. 7 - a sequence diagram of the operation of timers. . The device contains control controllers, each of which contains a command register 1, a state register 2, a program control block 3, a system controller 4, an address decoder 5, a random access memory block 6, a read-only memory program block 7, an interrupt controller 8, the first 9 and second 10 programmable timers, a parallel control interface 11 and a group of AND-NOT elements 12. The device also contains a system data bus 13 and a control unit 14 for the windings of the stepper motors.

5 The command register 1 and the state register 2 are used to exchange the controller with the system bus 13. Commands are entered into the command register 1 from the system bus side, as well as the operational information necessary for the controller to operate. Through the state register 2, the controller confirms the correctness of the reception of commands, and also fixes its state during operation,

15 In the instruction register 1, writing is done from the side of the system bus, and reading is from the side of the controller. The state register 2 is written by the controller, and read by the system bus.

The program control unit 3 (Fig. 3) consists of a single-chip microprocessor (DD2) and a clock generator (DD1).

5 The DD2 microprocessor reads the instructions on the ROM, following the actions specified in them.

The DD1 clock generator provides synchronous operation of the micro-0 processor and other controller nodes by generating signals F1, Ф2, STSTB, Ф2ТТ1.

System controller 4 (DD4, Fig. 3) provides the formation and buffering of 5 control signals: reading the MEMR memory; write to MEM; reading I / O devices 1 / OR; write to I / O devices 1/0; confirmation of interruption 1 TA.

Decoder 5 (DDZ, Fig. 3) generates 0 device selection signals.

The controller memory consists of a random access memory unit 6 (DD1, Fig. 4) and a program read-only memory block 7 (DD2, Fig. 4).

Block 7 stores the program of work of the controller 5, a table of settings for the operation of stepper motors.

Block 6 provides temporary storage of intermediate results of calculations, as well as operational information received from the system bus.

Interrupt controller 8 (DDZ, Fig. 5), the first and second programmable timers 9, 10 (DC1. DD2, Fig. 5), parallel

5, an interface 11 (DD4, FIG. 5) and a group of AND-NOT 12 elements (DD5, DDb, FIG. 5) are used to control the stepper motors. With their help, signals are generated with a duration of 0.5 µs and a programmable interval between them.

The correspondence of the inputs and outputs of blocks 1-12 and the signals of microcircuits is presented in the table.

The single-chip microprocessor (DD2, Fig. 3) has a 16-bit address bus and an 8-bit data bus. An address bus provides addressing of external memory and input / output devices.

The bits AO ... A10 are connected to the address inputs of block b of random access memory (DD1, Fig. 4) and address 2048 cells.

The bits AO ... A12 are connected to the address inputs of the block 7 of the read-only memory of the program (DD2, Fig. 4) and address 8196 cells. The three high-order bits of the address bus A12 ... A15 go to the digital inputs of the address decoder 5 (DDZ, Fig. 3) and, depending on the state of these buses, one of the outputs of the decoder 5 generates a logical level O - the choice of devices, which arrives at the inputs of selectable microcircuits.

With this organization of the decoder 5, the entire address space of the microprocessor (64 Kbytes) is divided into 8 blocks of 8 Kbytes.

The program read-only memory block 7 occupies the address space O ... 1FFF and is selected by the signal from the zero output of the decoder 5.

The RAM block 6 is 2000 ... 27FFF, and is selected by the signal from the 1st output of the decoder 5.

The signals from the outputs 2,3, 4,5, 6 of the decoder 5 are used to select one of the input / output devices of the interrupt controller 8, timers 9.10, parallel interface 11, command register 1 and state register 1.

The last output is used to address two registers 1, 2, which is possible due to the fact that register 1 of the command is only readable, and information is only written to register 2 of the state.

The data bus (DO ... D7) provides two-way exchange of microprocessor information with memory and input / output devices during data and command processing.

Signal TWO (DD2, FIG. 3) - Read - an output signal indicating that the data bus is in receive mode, i.e. the microprocessor is awaiting data from memory or input / output devices.

Signal WR (DD2, Fig. 3) - Record - an output signal indicating that the microprocessor has provided information to the data bus for writing to memory or input / output devices.

Signals DO. ,, D7, DB1N and WR arrive at the inputs of the same system controller 4 (DD4, Fig. 3).

At the beginning of each machine cycle, the microprocessor sets status information on the data bus that reports the type of current operation. By the signal STSTB coming from the clock generator (DD1, Fig. 3) to the input of the system controller 4, the status information of the system controller 4 is stored.

In the presence of the corresponding status information and signal DB1N, the system controller 4 generates control signals :.

MEMR - Read Memory,

I / OR - reading an input-output device;

NTA - acknowledgment of interruption.

Similarly control signals;

MEMW - write to memory;

G / OW - Recording to I / O devices is the result of a logical combination of status information and a microprocessor WR signal.

From the system controller 4, data bus signals and control signals are supplied to the memory chips and input / output devices.

The first and second programmable timers 9, 10 (DD1, DD2, Fig. 5) form programmable time delays and consist of three independent identical programmable 16-bit subtracting counters.

The exchange of information between timers 9, 10 and the microprocessor is carried out via the data bus DO ... D7 by the control signals WR and RD.

The address bits AO, A1 determine the number of the counter that is being accessed.

CE is a chip choice. As long as the chip is not selected, no write or read operations are possible on it.

CLKO, CLK1, CLK2 - input signals for synchronizing the operation of counters. For timer 9 (DD1, Fig. 5), the clock signals are F2TTC pulses coming from a clock generator (DD1, Fig. 03). For timer 10, synchronization signals are output from timer 9.

GO, G1, G2 - input signals that enable the operation of counters. These enable signals come from the outputs of the parallel interface 11 PCO. PC1, PC2 (DD4, Fig. 5).

OITO, OIT1, OIT2 - output signals of timer counters.

The programmable timer chip is programmed by writing control words into it that determine the mode, load order, type of count. After programming, the timer is ready to perform tasks related to the countdown. Each of the counters can work in one of six modes,

Counters of timer 9 are programmed to the frequency generator mode, timer 10 to interrupt the terminal count.

Programmable interrupt controller 8 serves up to eight microprocessor interrupt requests from external devices

DO ... D7 - data bus. Provides two-way exchange of information between the microprocessor and the chip.

CS is the chip selection of the programmable interrupt controller 8. The presence of an outside signal allows access to the chip.

WR - recording input allows you to write words from the data bus to the controller 8 interrupt initialization commands and operations.

The read RD input allows the chip to send the contents of the interrupt request register, work register, serviced requests, mask register, binary decimal interrupt request code to the data bus.

AO address input allows two internal registers to be addressed to the interrupt controller in programming mode.

INT - the output of interrupt requests. .

INTA - acknowledgment of interruption.

Three INTA pulses coming from the system controller 4 causes the controller chip 8 to issue interrupts to the data bus of the three-byte CALL command.

IRO ... R7 - Interrupt requests from external devices are sent to these inputs. In our case, signals from the outputs of the timer 9 and 10 pass through 6 inputs.

The interrupt controller 8 allows the interruption of the main microprocessor program by one of the requests received at the inputs of PO .. F P7. In addition, it allows you to:

a) reading pending and serviced requests, masking any request input;

b) unmasking the request blocked by the served request with a higher priority level;

c) interruption of the service subroutine upon receipt of a request with a higher priority level;

РСО .., RS2

d) storage and erasure according to the program of any served request.

e) a cyclic shift of the priority ring of incoming requests.

Upon receipt of interrupt requests, interrupt controller 8 determines which of the incoming requests has the highest priority and issues an INT signal to the microprocessor. Upon receipt of an interrupt acknowledgment chip at the INTA input, the chip issues a three-byte CALL command, two bytes of which represent the address of the service routine of the device that sent the request.

In this case, upon completion of the current instruction, the microprocessor stores the contents of the instruction counter and proceeds to the address of the interrupt service routine. After executing the subroutine, it returns to continue execution of the interrupted program.

Interrupt controller 8 can operate in several modes that are set by software. The priority setting algorithm is also set programmatically. Priorities assigned to external devices can be changed during program execution.

The programmable parallel control interface 11 comprises three 8-bit registers PA, PB, and PC, with which it is possible to organize unidirectional synchronous and asynchronous, as well as bidirectional exchanges. . The operation mode is programmed by recording the control word. In this device, all three registers are programmed to issue information.

DO ... D7 - the data bus provides two-way exchange of information between the microprocessor and the microcircuit;

CE - microcircuit selection allows access to the microcircuit;

WR - recording input allows writing data and data control registers from the data bus;

RD - read input allows the chip to output register contents to the data bus;

AO, A1 - address inputs, allow you to address registers when issuing information and recording control words during programming.

register outputs

The device operates as follows.

When the power is turned on, the microprocessor of the program control unit 3 starts to work according to the program recorded in the memory block 7, the first command is selected from the cell with the address 0000. The initialization block is located in the initial addresses of the block 7, during which timers 9, 10 are programmed , parallel interface 11, interrupt controller 8, after which the microprocessor switches to polling the contents of instruction register 1. Having received a command from the system channel, the microprocessor starts to execute the subroutine mu control the operation of one, two or three stepper motors.

Three timer counters 9 are programmed to give short pulses with a variable interval between them, and three timer counters 10 count the total number of movement steps (Fig. 7).

The necessary settings are entered into the counters of the timer 9, a high level is set at the enable inputs GO, G1. G2, and the inputs CLKO, CLK1, CLK2 receive the counting pulses Ф2ТТ1 from the program control unit 3 (Figs. 3 and 4).

After counting the delay at the outputs of the counters of timer 9 (DD1, Fig. 5), pulses are generated that are fed to the inputs of the interrupt request 1R of the interrupt controller 8 (DDZ, Fig. 5). At the output of the interrupt controller 8 (DDZ; Fig. 5), an interrupt request 1 T is generated, which is fed to the input of the microprocessor of the program control unit 3 (DD2, Fig. 3). The microprocessor finishes executing the current instruction and enters interrupt mode. From the system controller 4 (DD4,

Claims (1)

SUMMARY OF THE INVENTION A multi-channel stepper motor control device comprising a system data bus, a stepper motor winding control unit, control controllers, each control controller comprising a program control unit, a read-only memory program, first and second programmable timers, a parallel control interface, a command register characterized in that, in order to expand the scope of application, a state register, interrupt controller, system MODULES, defig. 3) the interrupt confirmation signal 1 TA is fed to the input of interrupt controller 8 (RS, Fig. 5). The microprocessor of the control unit 1 begins to process this request, as a result of which a new setting is entered into the timer counter 9, etc. At the same time, pulses from timer 9 (DD1, Fig. 5) are received at the synchronization inputs of timer 10 (DD2, Fig. 5), which counts their number and at the outputs of which (DD2, Fig. 5) it has pulses of a duration equal to the operating time of the corresponding stepper motor. At the end of the calculation of the total number of steps interrupt requests are also generated (RS); Fig. 5). The parallel interface 11 (DD4, Fig. 5) controls the operation of the timers on the permission inputs GO, G1, G2 (DD1, DD2, Fig. 5), and also generates signals directly reverse outputs of the port RV (DD4, Fig. 5) and work permit corresponding engine - outputs of the port of RA (DD4, Fig. 5). Each channel can be used to work not just one but several stepper motors in case they do not work simultaneously. This possibility for using each channel for two engines is realized by a group of elements NAND-12 (DD5, DD6, Fig. 5), the two inputs of which receive pulses from the outputs of the timers 9, 10, and the third inputs are given permissions from the six outputs of the port PA of the parallel interface 11. After running each stepper motor, information on completion of work is recorded in the state register 2. The device allows the use of, for example, dl. 2 simultaneously working stepper motors have three controllers instead of nine according to the prototype scheme. address encoder, random access memory block, group of NAND elements, the synchronization inputs of the first timer connected to the clock output of the program control unit, the control inputs of the first timer connected to the control inputs of the second timer and the first group of outputs of the parallel control interface, the outputs of the first timer connected to the synchronization inputs of the second timer, with the first group of interrupt request inputs of the interrupt controller and the first group of inputs of the NAND element block, the outputs of the second timer are connected they are connected to the second group of interrupt request inputs of the interrupt controller and the second group of inputs of the NAND block of elements, the third group of inputs of which is connected to the second group of outputs of the parallel control interface and is the first group of outputs of the control controller that are connected to the group of enable inputs of the control unit of the step windings motors, the outputs of the NAND block of elements and the third group of outputs of the parallel interface are respectively the second and third groups of outputs of the control controller, which respectively connected to the groups of inputs for clocking and selection of the direction of the control unit of the windings of the stepper motors, the interrupt request interrupt controller output is connected to the system controller output of the same name, the read and write outputs of the program control unit are connected to the system controller inputs of the same name, the output of the system controller Write to memory connected to the write control input of the RAM block, the output of the system controller. Reading from the memory is connected to the inputs of the same name readable and read-only memory of the program, the output of the system controller Writing to the input-output devices is connected to the inputs of the interrupt controller, the first and second timers, the parallel control interface and the state register, the output of the system controller Reading from the input-output devices is connected to the inputs of the same name interrupt controller, first and second timers, parallel control interface 1.1-1.8 1.9-1.16 1.17 1.18 1.19 1.20 2.1-2.8 2.9-2.16 2.17 2.18 2.19 2.20 3.1-3.16 3.17-3.24 3.25 System bus side data input The output of the device selection signal from the control controller Signal Input Read System bus side device select signal input Signal output Record Data output Data input Controller input signal input of the device Signal input Record Signal input from the system bus side Signal input Read Address bit output Data input / output Signal output Read laziness and the register of commands, inputs The choice of the device of the register of commands and the state register is connected to the first output of the address decoder, the remaining outputs of the address decoder are connected to the corresponding inputs The choice of the device blocks of RAM and read-only memory, interrupt controller of the first and second timers, parallel control , the corresponding outputs of the bits of the address of the program control unit are connected to the address inputs of the blocks of RAM, interrupt controller, parallel interface The control box, the first and second timers, with the address inputs of the address decoder, the control inputs of the address decoder are connected one to the unit potential bus, the other two to the zero potential bus, the outputs of the data bits of the program control blocks are connected to the inputs of the bits of the system controller , the outputs of the data bits of which are connected to the outputs of the read-only memory block of the program of the command register and to the inputs of the data bits of the random access memory block, interrupt controller, first and second timers, pairs allele interface for control and status register, the strobe signal output of the program control unit is connected to the system controller input of the same name, the status register data outputs and similar command register inputs are connected to the system bus to which the command register write input and the status register read input are connected niy. Signal Name Block entry and exit number s: 26 3.27 3.28 3.29 4.1-4: 8 4.9-4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.24 5.1-5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 6.1-6.11 6.12-6.19 6.20 6.21 6.22 7.1-7.13 7.14-7.21 7.22 7.23 8.1-8.8 8.9-8.11 8.12-8.14 8.15 8.16 8.17 8.18 8.19 8.20 9.1-9.8 9.9-9.11 9.12-9.14 9.15-9.17 9.18 9.19 9.20 9.21 9.22 10.1-10.8 10.9-10.11 10.12-10.14 10.15-10.17 10.18 Signal Output Clock output Signal Input Interrupt Request T TV signal output - status strobe Data input / output Data input / output Signal Input Read. Signal Input Recording Signal output Interrupt confirmation Signal output Read memory Signal output Write to memory Signal output I / O device recording Status Gate Signal Input Address bit input The choice of registers P to / Pc. Selecting a read-only memory block RAM block selection Choosing a Parallel Management Interface Interrupt Controller Selection First timer selection Second timer selection Address bit input Data input / output RAM block select signal input Signal Input Memory Read Signal input Write to memory Address bit input Data output Operation signal input of the read-only memory block Signal Input Memory Read Data input / output Interrupt Request Inputs Interrupt Request Signal Output Signal Input Interrupt Confirmation Signal input I / O device recording Device Select Signal Input Signal Input Read I / O Devices AO address zero bit input Data input / output Timer Counter Control Inputs Timer Counter Outputs Timer counter clock inputs Signal Input Read I / O Devices Signal input I / O device recording AO address zero bit input Device Select Signal Input Input of the first bit of the bus address A1 Data input / output Timer counter clock inputs Timer Counter Control Inputs Timer Counter Outputs ° A UDGERG9 -. ,, - .. Table continuation Signal Name Block entry and exit number 10.19 10.20 10.21 1.0.22 11.1-11.8 11.9-11.14 11.15-11.20 11.21-11.23 11.24 .11.25 11.26 1.1.27 11.28 12.1-12.6 12.7-12.9 12.10-12.12 12.13-12.18 Signal Input Read I / O Devices Input of the first bit of the bus address A1 Signal input I / O device recording Device Select Signal Input Data input / output Signal output PR-reverse - control controller output Signal output Resolution - control controller output Timer Control Outputs Device Select Signal Input Cooler bit input of AO address bus Input of the first bit of the bus address A1 Signal Input Record to I / O devices. Signal Input Read I / O Devices Parallel Interface Inputs Inputs from the first timer Inputs from the second timer T output signals - control controller output I AM 02 gY V Table continuation The name of the signal. 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