RU1786679C - Device for transmission o digital information - Google Patents

Abstract

The invention relates to communication technology and can be used in digital information transmission systems, automated control and monitoring systems. The purpose of the invention is to increase the noise immunity of a digital information transmission system. The transmission system comprises, on the transmitting side 1, a parallel to serial code converter 4, an encoder 5 and a transmitter 6, a word length generator 7, a clock pulse generator 8, a code sensor 9. The receiver side 2 includes a receiver 10, a decoder 11, a serial to parallel converter 12, a memory register 13 and a write pulse generator 14. In a digital information transmission system, by using the self-synchronizing biphasic unipolar code Manchester-P, synchronization pulses are extracted from the data stream, which makes it possible to increase noise immunity. 2 s.p. f-ly, 5 ill. ate with

Description

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The invention relates to communication technology and can be used in digital information transmission systems, in automated control and monitoring systems.

A known system for transmitting digital information over a fiber-optic communication channel, the transmitting side of which contains an information source, a code base converter, code group and secondary clock converters, a three-position bi-pulse signal generator, an input unit, and a receiving side, an output unit, a storage device, a converter chopper, secondary clock selector, code group clock extractors, threshold generators, decision node, code base inverter, primary clock extractor s and consumer information.

The disadvantages of this system are its low noise immunity, due to the instability of the parameters and low noise immunity of the filter circuits, drives and rectifiers, as well as the significant redundancy and complexity of the system nodes, which also reduces the noise immunity of the system and its reliability. Information at the input and output of the system exists in serial code.

The closest is a technical solution containing a transmitting and receiving device connected by a communication line. The transmitting device consists of a parallel to serial code converter (multiplexer), a word length generator (counter, key, one-shot, AND-OR-NOT element, AND element), a clock generator, transmitter, and a receiving device from a receiver, a decoder (block sync pulses, shift register, AND elements, counter, trigger), serial-to-parallel code converter (decoder), memory register and write pulse generator (trigger, AND elements).

One of the disadvantages of this technical solution is its low noise immunity due to the presence of clock generators on both the transmitting and receiving sides, and the need for this to automatically adjust the phase and purity of the controlled generator (on the receiving side), in which the frequency difference and the error of the phase mismatch of the generators become close to zero, which is necessary to increase the allowable period of operation of the system without losing synchronization.

Insufficient noise immunity is also determined by the presence of a wired communication line, subject to the influence of interference and electromagnetic interference, and 5 by the use of a non-jamming code for transmitting information.

i

The purpose of the invention is to increase the noise immunity of a digital transmission system

0 information.

This goal is achieved in that in a digital information transmission system comprising, on a transmitting side, a series-connected converter

5 parallel code to the serial, encoder and transmitter, as well as a word length generator, the output of which is connected to the control input of the encoder, whose clock input and the C-input of the length generator

0 words are connected to the output of the clock generator, the low-order information input of the parallel-to-serial code converter is connected to the common bus at the receiving Side 5. serial-connected receiver, decoder, serial-to-parallel converter and memory register, as well as a write pulse generator , the output of which is connected to the C-input of the memory register according to the invention on the transmitting side, the encoder is made in the form of series-connected element And, the first D-trigger, the first of the element EXCLUSIVE OR, the second D-trigger, and

5 of the second element EXCLUSIVE OR, while the output of the AND element through the element is NOT connected to the C-input of the second D-trigger; the other input of the second EXCLUSIVE OR element is connected to the direct

0 by the output of the first D-flip-flop, the inverse output of which is connected to its D-input, the first and second inputs of the AND element being the control and clock inputs of the encoder, respectively, the other input of the first element EXCLUSIVE OR is the information input of the encoder, and the output of the second element EXCLUSIVE OR - by the encoder output, as well as a code sensor is introduced, the outputs of which are connected to the D-inputs

0 word-length driver, the output of which is connected to the V-input of the parallel code to serial converter, the S-input of which is connected to the common bus, the output of the clock generator is with

5 With the C-input of the parallel code converter into serial, on the receiving side, the clock output of the decoder is connected to the C-input of the serial code converter into parallel and with the input of the write pulse generator.

The goal is also achieved by the fact that the word length generator consists of a reversible counter, the information inputs of which are information inputs of the word length generator, the first and second AND-NOT elements, the OR element, D-trigger, whose direct output is the output of the word length generator and is connected to the first input of the second AND-NOT element, the inverse output is with its D-input and the first input of the first AND-NOT element, and the C-input is with the output of the OR element, the first input of the OR element is connected to the output of the reversible counter, and its second entrance - output of the first AND-NO element and C-. - by the input of a reversible counter, the subtracting input of which is connected to the output of the second NAND element, the second inputs of the first and second NAND elements are interconnected and are the C-input of the word length former. The R-input of the reversible counter is connected to a common bus, and the write pulse generator consists of an element And, the first input of which is an input of this former, which is connected through a series-connected element Н Е and a delay element to the second input of this element And, whose output is through the filter is connected to the output of the recording pulse generator.

In patent studies, such transmission systems were not identified, which confirms the novelty of the claimed technical solution. Patent studies have shown that the combination of common and distinctive features exhibits new properties:

the ability to transmit information using the self-synchronizing biphasic unipolar Manchester P code, which allows to extract clock pulses from the data stream and thereby eliminate both the clock generator on the receiving side and the problems associated with the synchronization of the generators, and therefore with loss synchronization;

providing galvanic isolation in the communication channel using a fiber optic communication line;

the possibility of automatic, without changing the circuitry, using, for example, a computer, changing the bitness of the transmission system, and as a result, the transmitted digital information, which is achieved by changing the dividing factor of the word shaper using the code sensor and selecting the number of registers of the parallel to serial converter certain redundancy of bits,

wherein the unused bits of these registers are connected to a common bus.

These properties allow to obtain a positive effect, which consists in increasing the noise immunity

system, its simplification and versatility.

In FIG. 1 is a functional diagram

information transfer systems; in FIG. 2 is a functional diagram of a word former; in FIG. 3-5 - time diagrams of the operation of the transmitting, receiving sides and the shaper of the word length, respectively, The digital information transmission system consists of the transmitting side 1 and

5 of the receiving side 2 connected by a communication line 3. The transmitting side 1 comprises a series-connected converter 4, parallel to serial, encoder 5 and transmitter 6,

0 word length former 7, whose output is connected to the control input of encoder 5, whose clock input and C-input. Word length former 7 is connected to the output of clock generator 8,

5 information input of the least significant bit of the parallel-to-serial code converter 4 is connected to the common bus, as well as the code sensor 9, the outputs of which are connected to the D-inputs of the length former 7

0 words, the output of which is connected to the V-input of the parallel code converter 4 to serial, the S-input of which is connected to a common bus, the output of the 8 clock pulse generator is connected to the C-input of the parallel code converter 4 to serial.

In this case, the encoder 5 contains series-connected elements And 15, the first D-trigger 17, the first element EXCLUSIVE OR 19, the second D-trigger 18, the second element EXCLUSIVE OR 20, while the output of the element And 15 through the element NOT 16 is connected to the input of the second D-flip-flop 18, the other input of the second element EXCLUSIVE OR OR 20 is connected to the direct output of the first D-flip-flop 17, whose inverse output is connected to its D-input. The first and second inputs of AND element 15 are the control and clock inputs of encoder 5, respectively, the other input of the first EXCLUSIVE OR 19 element is the information input of encoder 5, and the output of the second EXCLUSIVE OR 20 element is the output of encoder 5.

5 Moreover, the shaper 7 of the word length contains a reverse counter 25, the information inputs of which are the information inputs of the shaper 7 of the layer length, the first 26 and second 27 NAND elements, OR element 28, D-flip-flop 29, whose direct output is the output of the former 7 is the length of the words and is connected to the first input of the second element AND-NOT 27, the inverse output is with its D-input and the first input of the first element И-Н Е 26, and the C-input is with the output of the element OR 28, the first input of which is connected to the output of the reverse counter 25, and the second input with the output of the first elem entent AND 26 and the C-input of the reversible counter 25, the subtracting input of which is connected to the output of the second AND-NOT 27 element, the second inputs of the first 26 and the second 27 AND-NOT elements are interconnected and are the C-input of the word length generator, The R input of the counter 25 is connected to a common bus.

The receiving side 2 comprises a receiver 10, a decoder 11, a serial to parallel converter 12, a memory register 13, as well as a write pulse generator 14, the output of which is connected to the C-input of the memory register 13, the clock output of the decoder is connected to C - the input of the converter 12 of the serial code in parallel and with the input of the driver 14 of the write pulse.

In this case, the write pulse generator 14 consists of an element And 21, the first input of which is the input of the former 14, which is connected through a series-connected element HE 22 and the delay element 23 to the second input of the element And 21, the output of which through the filter 24 is connected to the output driver 14 of the recording pulse.

As converters 4 and 12 of parallel code to serial and serial to parallel, shift registers of series K531, 155, etc. are used.

As a memory register 13, EXCLUSIVE OR elements 19 and 20, AND elements 15 and 21, AND-NOT elements 26 and 27, NOT elements 16 and 22, OR elements 26, D-flip-flops 17, 18 and 29, reverse counting - Chika 25, delay element 23 can also be used chips of the series K531, 155 and others.

As transmitter 6 and receiver 10, for example, optical transmitting modules POM-3 ODO.201.008 TU and receiving PROM-3 ODO.202.005 TY, respectively, can be used. The filter 24 can be performed, for example, according to a single-link Shevkopl scheme with V.V. .

The decoder 11 may be performed, for example, according to the scheme.

Shaper 7 code can be performed, for example, in the form of a keypad typed floor switches-for manual

operating mode, and for automatic - in the form of an output register of a digital computer or hard logic.

The clock generator 8 can be performed, for example, on the basis of the circuit shown in Fig. 2.38, p. 81 manuals Processor A 131-15. Manual . Part 3. Electrical processor circuits. 3.031.027 RE2.

The system operates as follows. When the device is turned on on the transmitting side 1, the D-flip-flops 17 and 18 are set to the zero state, the word-length driver 7 is set to the state in which O is present at its output. This state is the initial one. In this case, the element And 15 is closed and the logical information is recorded (Fig. 3, a) in the register of the input shift converter 4 (D0-Dn), and the division coefficient selected in accordance with the required bit grid of the system is entered into the shaper 7 word lengths on inputs (D0 ... Dm) from. sensor 9 code. On the trailing edge of the write pulse, the output of the word length generator 7 shows a single signal level, which goes to the V-input of the register of the shift converter 4 and opens the And 15 element, to the first input of which the clock pulses arrive. In this case, the clock pulses arriving at the C-input of the register of the shift converter 4 shift the previously recorded information along their leading edge, and the pulses arriving at the C-input of the driver 7 of the word length subtract the entered information from the sensor 9 of the code. From the output of element And 15, the sequence of clock pulses is fed to the input of the first D-trigger 17 and the element is NOT 16 (Fig. 3, b). From the output of the register of the converter 4 shift code NRZ (Fig. 3, d) is fed to the first input of the first element 19 EXCLUSIVE OR. A signal from the direct output of the first D-flip-flop 17 arrives at its second input (Fig. 3c). From the output of the first element 19, an EXCLUSIVE OR signal (Fig. 3, h) is fed to the D-input of the second D-flip-flop of the receiver 10 (Fig. 3, h) and is written to it at the trailing edge of the clock pulses (Fig. 3, d). At the output of the second D-flip-flop 18, a signal is generated (Fig. 3e), which is added modulo 2 with the signal from the output of the first D-flip-flop 17 at the output of the second element 20 EXCLUSIVE OR forms the Manchester-P code (Fig. 3, g ) In the generated Manchester – P code, the low order (Do) is the service –– start and is 0. The remaining bits (Dr – Dn)

are informational. The S-input of shift register 3 is connected to a common bus so that logical O is pushed into the high-order bit. In this case, at the last step of the formation of the Manchester-P code, there is a logical O at the output of shift register 3 (Fig. 3, a) along the trailing edge of the nth clock pulse, the same logic level is recorded in the second D-flip-flop 18 as at the direct output of the first D-flip-flop 17 (Fig. 3e),

Thus, between the last bit of one code message and the first bit of the next code message there will be a pause for one or one and a half periods of the clock frequency, depending on the value of the last bit of information (Fig. 3g). In addition, at the last clock cycle of the Manchester-P code generation, an overflow pulse of the word length generator 7 is generated. On its trailing edge, a logical O appears at the output of the word length generator 7, which closes the And element 15 and allows the recording of new information in the register of the shift converter 4 and rewriting of the division factor in the generator 7 of the word length with the next clock pulse. On its trailing edge, a logical 1 appears at the output of the word-length generator 7 and the cycle starts again. A pause formed between information words on the receiving side 2 is interpreted as a sign of the end of the word. The Manchester code - P is sent to the transmitter 6, which in this example converts the electrical signal into an optical signal and transmits it via fiber-optic communication line 3 to the receiver 10. From the output of the receiver 10, which converts the optical signal into an electrical signal, the Manchester code - P (Fig. 4.a) is supplied to the decoder 11, from the first output of which the NRZ code is removed (Fig. 4.6). and from the second - sync pulses (Fig. 4, c). On the shift register 12, the NRZ code is converted to parallel code. which is stored in the output register 13 of the memory. A write pulse arriving at the C-input of the memory register 13 is generated as follows. The clock pulses from the decoder 11 are fed to the first VHBD of the And 21 circuit and through the inverter of the element 22 and the delay element 23 to its second input (Fig. 4.d). The delay of the signal on the delay element 23 should be equal to the period of the clock frequency. At the same time, a write pulse (Fig. 4e) of the memory register 13 is generated at the output of element 1/1 21. Filter 24 serves to eliminate chips caused by the error of the delay element 23. Thus, at the output of the register 13, a parallel code is generated that is identical to the input information on the transmitting side 1. The word length generator 7 shown in FIG. 2, works as follows. In the initial state, the D-flip-flop 29 is set to O. In this case, the AND-HE 26 element is open, and the AND-HE 27 element is closed. The first clock pulse arriving at the second inputs of these elements appears at the output of the AND-NOT 26 element, arrives at the C-input of the reversible counter 25 (Fig. 5c), and enters the setting at the information inputs (Do-Dm) into it. through the OR element 26, it enters the C-input of the D-flip-flop 29 and sets its reverse edge to 1. In this case, the AND-NOT 26 element closes, and the AND-HE 27 element opens and the clock pulses (Fig. 5, a) are fed to the subtracting input of the reverse counter 25 (Fig. 5, d) through the NAND element 27. From the output P of the reverse counter 25, an overflow pulse (Fig. 5d) is fed through the OR element 28 to the C-input of the D-trigger 29, sets it to O and the cycle repeats again. Thus, from the output of the D-flip-flop 29, a shift recording signal (Fig. 5,6) is generated at the V-input of the register of the shift converter 4, which controls the operation of the And element 15 and the specified shift register, as described above.

Claims (3)

As shown by an experimental verification, the claimed technical solution transmits the shortcomings of the above devices and, in comparison with the prototype, allows transmitting information using the Manchester-P code containing clock pulses in the information data stream, and thereby exclude it as a clock generator on the receiving side, and the problems associated with the desynchronization of the operation of the generators, and hence with the loss of synchronization; provide galvanic isolation in the communication channel using a fiber optic communication line together with a transformer; to obtain a universal information transmission system that can change the bitness of the transmitted information without changing the circuitry when changing the number code set in the code sensor. SUMMARY OF THE INVENTION 1. A digital information transmission system comprising, on a transmitting side, a parallel-to-serial-to-serial-to-serial-converter, encoder and transmitter, as well as a word and word shaper whose output is connected to a control input of the encoder, whose clock input and the C-input of the length shaper words are connected to the output of the clock pulse generator, the low-order information input of the parallel-to-serial code converter is connected to the common bus, and on the receiving side it is connected to reconciled receiver, decoder, serial to parallel converter and memory register, as well as a write pulse generator, the output of which is connected to the C-input of the memory register, characterized in that, in order to increase the noise immunity of the digital information transmission system, on the transmitting side, the encoder is made in the form of series-connected AND element, the first D-trigger, the first EXCLUSIVE OR element, the second D-trigger and the second EXCLUSIVE OR element, while the AND element is output through the element NOT connected to the C-input of the second D-flip-flop, the other input of the second EXCLUSIVE OR element is connected to the direct output of the first D-flip-flop, the inverse output and the D-input of which are interconnected, the first and second inputs of the AND element being are the control and clock inputs of the encoder, respectively, the other input of the first EXCLUSIVE OR element and the output of the second EXCLUSIVE OR element are respectively the information input and output of the encoder, as well as a code sensor whose outputs are connected to the corresponding D-inputs form l the length of words whose output is connected to the V-input of the parallel code to serial converter, the S-input of which is connected to a common bus, the output of the clock generator is connected to the C-input of the parallel code converter to serial, and on the receiving side, the clock output of the decoder is connected to the C-input of the serial code converter to parallel and to the input of the recording pulse generator, 2. Pop system. 1, characterized in that the word length shaper is made in the form of a series-connected reverse counter, an OR element and a D-trigger, the inverse and direct outputs of which are connected respectively to the first inputs of the first and second AND-NOT elements, the output of the first AND element - NOT connected to another input of the OR element and to the C-input of the reversible counter, the subtracting input of which is connected to the output of the second AND-NOT element, and the information inputs of the reversible counter and interconnected second inputs of the first and second The NAND elements are respectively the information and C-input of the word-length formulator, the output of which is the inverse output and the D-input of the D-flip-flop connected to each other, and the R-input of the reverse counter is connected to a common bus. 3. Pop system, 1, characterized in that the recording pulse generator is made in the form of series-connected HE elements, a delay element, an AND element and a filter, the other input of the And element being connected to the input of the HE element and being an input of the recording pulse generator, the output of which is the output of the filter, kJffff.S L6 L-L-PL ... GT Fig L ... and uh ... uh eagle Fie 5 3mS w GT and -c