RU1784982C - Power supply voltage control device - Google Patents

Abstract

The device for monitoring the voltage of the power supply relates to computer technology and can be used to quickly monitor the voltage values on the output buses of the secondary power sources of technical means of high-speed computers and automation systems. An object of the invention is to increase the noise immunity and accuracy of a voltage monitoring device. The device comprises an input-output unit 1, an analog-to-digital conversion (ADC) unit 2, an analog signal switching unit 3, a normalization unit 4, consisting of a group of nodes 4.1-4.56 normalizing signals of negative polarity and a group of nodes 4.57-4.64 normalizing signals of positive polarity, and an analog-to-digital conversion unit start unit 5. 2 s.p. fg / ibi, 6 ill.,.; .-. - -:

Description

The invention relates to computer technology and can be used for operational control of the voltage value on the output buses of secondary power sources of technical equipment of an electronic computer, computer systems, and automation systems.

The purpose of the invention is to increase the noise immunity and accuracy of a device for monitoring the supply voltage.

In FIG. 1 is a block diagram of a device (an example embodiment of a device for monitoring the supply voltage on 64 output buses); in FIG. 2 is a diagram of a trigger unit of an analog-to-digital conversion unit; FIG. 3 is a diagram of a normalization block; in FIG. 4 is a diagram of a block for switching analog signals; in FIG. 5 is a diagram of an input / output unit; on fmg. 6 is an algorithm for measuring voltage controlled on output buses of secondary power sources.

The device for monitoring the supply voltage (Fig. 1) contains an input-output unit 1, an analog-to-digital conversion (ADC) unit 2, an analog signal switching unit 3, a normalization unit 4, consisting of a group of nodes 4.1-4.56 normalizing the negative field signals the sizes and groups of nodes 4.57–4.64 normalization of signals of positive polarity, node 5 for starting the analog-to-digital conversion unit, address input 6, control input 7, gate input 8 and output 9 of the device control result, address output 10, control Outputs 11.12 of block 1, you 13 od completion of conversion start input 14, digital output 15 and an analog input unit 2 16, group of information outputs 17, 18 unit 4, a group of information inputs 19 the device,

The start-up unit 5 of the analog-to-digital conversion unit (Fig. 2) contains a trigger 20, a resistor 21, a capacitor 22 and an AND-NOT 23 element.

Block 4 normalization (Fig. 3) contains a group of nodes 4.1-4.56 normalization of signals of negative polarity and a group of nodes 4.57-4.64 normalization of signals of positive polarity, each of the nodes 4.1-4.56 contains an operational amplifier 24, a capacitor 25, resistors 26, 27, 28.29, each of the nodes 4.57-4.64 contains an operational amplifier 30, a capacitor 31, resistors 32, 33, 34.

Block 3 switching analog signals (Fig. 4) contains analog multiplexers 35 ... 41, 42, 43, operational amplifier 44 and resistors 45, 46.

Block 1 I / o (Fig. 5) contains the element NOT 47, registers 48, 49, multiplexers 50, 54, the decoder 55 and the element AND 56.

The input-output unit 1 is designed to receive and store information received from the service processor via the address input 6 and control input 7 buses, to decrypt the address code of the secondary power supply, the voltage of which is controlled by the formation of control signals, and also multiplex output information for transmission it to the interface of the service processor through output 9 of the result of the control device.

Block element 47 of block 1 generates a gate signal to trigger output multiplexers 50-54. Registers 48, 49 are used to store information received via input buses 6 and 7. The decoder 55 serves to generate a signal controlling the operation of block 3 at the output 11. The Y-NOT 56 element generates a signal controlling the node 5 at the output 12.

The analog-to-digital conversion unit 2 can be performed, for example, on an integrated circuit of type 11 08 PV 1.

Block 2 generates at the output 15 a digital code corresponding to the voltage currently being supplied from analog input 16.

Block 3 switching of analog signals, depending on the signals coming from outputs 10, 11 of block 1, connects one of the information outputs of the groups of information outputs 17.18 of block 4 to the analog input 16 of block 2. “„

Multiplexers 35 through 43 of the analog signals of block 3, in accordance with the signal code on the output buses 10, 11 of block 1, connect one of the 64-bit information outputs of the output groups of the outputs 17, 18 of block 4 to the output 16.

The operational amplifier 44, included in the repeater circuit, acts as a matching buffer between the output of the multiplexer 43 and the analog input 16 of unit 2.

Block 4 of signal normalization is intended to bring the values of the monitored voltages supplied to the information inputs from 19.1 to 19.65 of the device and having different values and polarity to the normalized voltage value of positive polarity.

In block 4, each of the nodes 4.1-4.56 normalization of signals of negative polarity using the operating

amplifier 24, resistors 26-29 provides inversion and scaling of the corresponding analog signal with a scale divider 26, 27, Capacitor 35 increases the noise immunity of the node.

Each of the nodes 4.57-4.64 normalization of signals of positive polarity with the help of operational amplifier 30 and resistor 34 connected according to the repeater circuit, as well as the voltage divider on resistors 32, 33 provides scaling of the corresponding analog input signal, as well as matching with block 3 The capacitor 31 increases the noise immunity of the node.

Node 5 is designed to generate a signal at input 14 of block 2 to trigger it upon receipt of a control signal from output 12 of block 1 and its automatic reset when a signal is received to complete the conversion from output 13 of block 2.

In node 5, the resistor 21 and the capacitor 22, included at the input of the AND-23 element, provide a time delay for the generated signal to start the ADC unit 2 for the time necessary to complete the transients in block 3 when the address of the corresponding secondary power source is sampled, voltage on the output buses, which is monitored. Trigger 20 upon receipt of the output of block 13 of the logic 0 signal switches node 5 to its initial state.

The introduction of node 5 eliminates the restart of block 2, which increases the accuracy of monitoring the device if the duration of the trigger signal at the control output 12 of block 1 is longer than the analog-to-digital conversion time.

The signal at the input 14 of block 2 starts it, and the signal from the output 13 of the conversion of block 2 resets the trigger 20 of node 5 to its initial state.

The groups of information outputs 17, 18 of block 4 provide the connection of groups of nodes 4.1..4.56 of normalization of signals of negative polarity and groups of nodes 4.57 ... 4.64 of normalization of signals of positive polarity to the corresponding inputs of block 3.

The operation of the proposed device in the mode of monitoring the voltage on the output buses of the secondary power sources is carried out as follows.

After turning on the device for monitoring and supplying voltage to the information inputs from 19.1 to 19 64 nodes

4.1-4.54 voltages arrive, the values of which must be controlled

Each of the normalization nodes 4.1-4.64 scales the controlled voltage to the level and polarity at which the analog-to-digital conversion is carried out in the linear region of the ADC operation of block 2.

At the command of the operator, the service processor starts to execute the VOLTAGE CONTROL program, the block diagram of the algorithm of which is shown in FIG. 6.

From the output of the service processor interface through inputs 6 and 7 of the device, the code

5 addresses of the secondary power source, the voltage of which is monitored, and the control code for the operation of block 2 of the ADC are supplied to the inputs of the register 48 l 49 of the block, respectively, and stored in them when

0 a gating signal appears at input 8 of the device.

Decryptor 55 converts the high order bits of the controlled voltage address code received from the service processor into

5, a signal whose bits from the first and eighth through the buses of the control output 11 of block 1 are supplied to the RESOLUTION inputs of multiplexers 35 ... 41,42 of block 3, respectively. From the output 10 of block 1, the lower bits of the address code go to the address inputs C1, C2, C3 of the multiplexers 35 ..41, 42, and the high bits go to the control inputs, address inputs C1, C2, C3 of the multiplexer 43 of the block 3.

5 As a result, the controlled voltage from the corresponding bus of the secondary power source, the address of which was received at input 6 of block 1 from the output of the service processor interface, enters the corresponding normalization node 4.1 ... 4.64 through one of the information inputs of the device 19.1-19.64 . From one of the information outputs of the groups of outputs 17 and 18 of block 4, the controlled voltage 5 passes through block 3 to input 16 of block 2.

The second and fifth bits of the control code from the output of the register 49 and the gate signal from the input 8, arriving at the inputs of the AND-NOT 56 element, form a control signal for the node 5 at the output 12 of the block 1.

On this signal, the trigger 20 of node 5 is switched from logical 0 to logical 1. arriving at the inputs of the element

5 AND NOT 23. Moreover, the logical 1 signal goes directly to the first input of element 23, and to the second input through a chain formed by resistor 21 and capacitor 22. This creates a time delay of (2-3) 10 s between the signal at the gate

the input 8 of the device and the signal generated at the input 14 of the unit 2, which serves to start it.

A time delay is necessary in order for the start of unit 2 to occur after the completion of the transient processes occurring in the unit 3 of the analog signal switch when the address of the secondary power source, the voltage of which is controlled, is selected.

After the end of the analog-to-digital conversion process, the END OF TRANSFORMATION signal from the output 13 of block 2 resets the trigger 20 of node 5 to its initial state, which blocks the restart of block 2 until the next control signal arrives from the service processor. Measurement result in digital binary code (10 bits) Dow) is stored in the output register of block 2 of the ADC, while the first to fifth bits are fed to the first inputs of multiplexers 5Q-54, respectively, and the sixth to tenth bits are fed respectively to the second inputs of the multiplex lexors 50-54,

After a time T 5 10 s after a gating signal (0.8-1.0) 10 s is received at the input 8 of the device, the service processor reads the measurement result from the output 9 of the device.

The address code received at input 6 of block 1 is stored in register 48 of block 1, from the output of which the fifth, sixth, and seventh bits of the address code are fed to the inputs of AO A1 A2 multiplexers 50 ... 54, respectively. The gate signal from input 8 of unit 1 through the inverter 47 is fed to the RESOLUTION inputs of multiplexers 50 .., 54 and, opening them, provides the output of the measurement result code to the output 9 of the device.

The service processor, in accordance with FIG. 6 by an algorithm, calculates the arithmetic mean code of the measured voltage and compares it with the codes of the upper and lower limits of the permissible voltage deviation stored in the ROM. If the tolerance is exceeded, the service processor stores the address of the monitored secondary power supply, the voltage of which is monitored. The voltage value obtained during the measurement, which is displayed on the display screen of a computer console with increased brightness.

Then, the service processor executes the unscaling microprogram, multiplying the code of the obtained measurement result by the corresponding coefficient determined by the constructive address

secondary power source. When executing this firmware, the service processor uses the address and scaling table

coefficients for all monitored voltages, which is stored in the ROM of the service processor

After converting the result to a decimal code and storing it in the RAM of the processor, the service processor goes to the address of the next monitored secondary power supply, repeating the above procedures.

Checking all the addresses that

5 are stored in the ROM, the service processor executes the microprogram for outputting the result of the voltage control on the secondary power supply buses of the computer hardware to the screen of the remote display.

0

Claims (3)

SUMMARY OF THE INVENTION 1. A device for monitoring the supply voltage comprising an input / output unit, an analog-to-digital conversion unit, an analog signal switching unit, and a normalization unit, the address, control, and gate inputs of the input / output unit being respectively address, control With the building and building inputs of the device, the address output of the input-output unit is connected to the first control input of the analog signal switching unit, characterized in that, in order to increase the noise5 immunity and accuracy , the start-up unit of the analog-to-digital conversion unit is introduced into the device, and the normalization unit contains a group of nodes for normalizing signals of negative polarity and a group 0 nodes of normalization of signals of positive polarity, and the information output of the input-output block is the output of the result of the control of the devices, the first and second control outputs of the block 5 input-output are connected respectively to the second control input of the analog signal switching unit and the first control input of the start unit of the analog-to-digital conversion unit, the second control input and output of which are connected respectively to the output of the conversion end and the start input of the analog-to-digital conversion unit , digital output and analog input 5 of which are connected to the information input of the input-output block and the output of the analog signal switching block, respectively, the outputs of the negative polarity normalization nodes are the first group of information outputs of the normalization block to connect the analog signals to the first group of information inputs of the analog signal switching outputs, the outputs of the positive signal normalization nodes the polarities are the second group of information outputs of the normalization block for connecting to the second group of information inputs and switching of analog signals, the group of information inputs of normalization block is connected to the inputs of nodes normalize signals of positive and negative polarities and is a group of information inputs of the device. 2. The device according to p. 1, with the proviso that the start-up unit of the analog-to-digital conversion unit contains a trigger, a resistor, a capacitor and an NAND element, the trigger installation input being the first, and the reset input is the second control inputs of the node, the trigger output is connected to the first output of the resistor and the first input of the AND-NO element, the second input of which is connected to the second MJBU input of the resistor and the first terminal of the capacitor connected by the second terminal to the node zero bus, the output of the NAND element is the node output. 3.Pop device. 1, characterized in that in the normalization unit, each of the nodes of normalization of signals of negative polarity of the group of nodes contains an operational amplifier, a capacitor and four resistors, the inverse input of the operational amplifier through the first resistor connected to the first output of the capacitor and the group of information inputs of the unit, and through the second resistor connected to the output of the operational amplifier, the direct input which, through the third resistor is connected to the second output of the capacitor and the bus circuit of the device ground, the output of the operational amplifier is connected to the first group of information x outputs of the block and through the fourth resistor - with a zero node bus, each of the nodes of normalization of signals of positive polarity of the group of nodes contains an operational amplifier, a capacitor and three resistors, and the direct input of the operational amplifier through a parallel connected capacitor and the first resistor is connected to the ground circuit bus devices and through the second resistor is connected to the group of information inputs of the block, the inverse input of the operational amplifier is connected to its output, which is connected to the second group of information the outputs of the block and through the third resistor is connected to the zero bus node. 12 s "0.2 "RA.S {jfWfincf):;. ZstanoBShb Havia- loyal controlled asras Cut order ZYGYSK PCP i Lagging lags  with L It was considered by the CoC to be the result of measurements .-:: /.; -. Fill the result code with the pre-existing ansiemia: .... Si no && 6 Vyiis lithuania. arshrmetiy value a piece of chalk Record the counterhydrography. aor. with porish. opkocrn. posss Vmnoshshpr koz cf. know on kozfsch. scale a birr banz Irea & Razo & At 6 Besdtiny Code Record 6 Rfln IzmRENIP results Behind (IcOHEiT) V., s