RU1781820C - Device of or phase automatic frequency control - Google Patents

Abstract

The use of a communication technique, a device for adjusting the frequency and phase of a signal Summary of the invention: a phase-locked loop contains a digital phase detector, averager, first and second multipliers, first and second adders, a digital-to-analog converter, a controlled generator, a register, a delay unit per clock element EXCLUSIVE OR, first and second switches, a subtractor and an additional register. The device has three control branches, combined on the second adder, which allows to increase the accuracy of synchronization. 1 silt

Description

The invention relates to communication technology and can be used in devices for automatically adjusting the frequency and phase of signals.

The aim of the invention is to improve the accuracy of synchronization.

The drawing shows a structural electrical diagram of a phase-locked loop

The phase locked loop device comprises a digital phase detector 1, averager 2, first and second multipliers 3 and 4, first and second adders 5 and 6, a digital-to-analog converter 7. controlled generator 8, register 9, delay unit 10 per clock element EXCLUSIVE OR, the first and second switches 12 and 13, the subtractor 14 and the additional register 15

The device operates as follows. Digital phase discriminator 1 measures the phase difference between signals

UBX and higher, and averager 2 averages the measured value over a time equal to the sampling period. Then, the average value of the phase difference enters three parallel branches. The first branch, called proportional, consists of the second multiplier 4. This branch determines the filtering properties of the phase-locked loop (UHF), and the effective filtering of the input phase fluctuations takes place at K1 values substantially less than unity. The second branch, called the integral, consists of the first multiplier 3, the first adder 5 and the register 9, called the integral. This branch provides astatism and determines the transition time. UVAF is stable at K2 " Ki. Therefore, in those cases where the averaged phase difference is less than the reciprocal of K2, then in fact the property of astatism is not manifested without the introduction of a third branch, and in the presence of a difference of hours VI

With

from

The phase error established with phase will be equal to the order of 1 / Kz.

The algorithm of the third branch is that with the constant sign of the averaged phase difference at each sampling period, the content of the subtractor 14 modulo increases by one, and the sign of the magnitude at the outputs of the subtractor 14 is such that this phase difference is compensated after appropriate frequency control. When the sign of the averaged phase difference is changed, the output of the subtractor 14 is reset to zero. Thus, the third parathyroid branch is a relay accumulation register (additional register 15), which is reset as soon as the accumulation target is reached, i.e. the phase difference is reduced to zero. In this regard, the third branch analyzes only the high order bit of the code of the averaged phase difference in block 10, this bit is recorded, which was fixed in the previous sampling period. If on both inputs of the element EXCLUSIVE OR 11 there is a unit, i.e. phase 1) Out. more than phase UBX., then the unit code from the first information input of the first switch 12 is fed to the inputs of the subtracted subtractor 14, reducing the addition from the third branch at the output of the second adder b. If zero occurs on both inputs of the EXCLUSIVE OR 11 element, then code -1 is switched to the inputs of the subtracted subtractor 14 from the second information input of the first switch 2, if the signals at the inputs of the EXCLUSIVE OR are different, then the output of the additional register 15 is switched to the inputs of the subtracted subtractor 14 as a result of which the outputs of the subtractor 14 are reset to zero

Claims (1)

The claims A phase locked loop device comprising connected in a ring a digital phase detector, an averager, a first multiplier, a first adder, a second adder, a digital-to-analog converter and a controlled generator, as well as a second multiplier included between the output of the averager and the second input of the second adder, and a register included between the output of the first adder and its output, the second input of the digital phase detector being the input of the device, characterized in that, in order to improve the accuracy of synchronization, a delayed block connected in series per clock and EXCLUSIVE OR element connected in series by the subtracter and additional register, as well as the first and second switches, the input of the delay unit per clock, the second input of the EXCLUSIVE OR element and control input of the first switches are connected to the high-order output of the averager; the first information input of the first switch is a code input. +1, its second information input is code -1, and its output is connected to the first information input of the second switch, the second information input of the second switch and. the input of the reduced subtractor is connected to the output of the additional register, the control input of the second switch is connected to the output of the EXCLUSIVE OR element, and the output of the second switch is connected to the input of the subtracted subtractor, the output of which is connected to the third input second adder. i 3Tfc 1 io cm fit /  A CNl I hh PS-D I