RU1777148C - Computing system - Google Patents

Abstract

The invention relates to computer technology and is intended for use in high performance multiprocessor computer systems. The purpose of the invention is to increase productivity in scalar and vector computations and to reduce the time for executing control actions. The system is made in the form of the following device modules - 1-1-1-8 of the general random access memory, cent

Description

Figure 1

ralny processors 2-1-2-16 and processors 3-1-3-8 input-output. The central control unit of the system comprises program control units made in the form of control computers 5-1-5-8 and a commutator 4 of communication lines. The presence of connections between the modules of the system type each with each

The invention relates to computer technology and can be used in the design of high-performance multiprocessor computer systems.

The purpose of the invention is to increase productivity in scalar and vector computations and to reduce the time for executing control actions.

In FIG. 1 is a structural diagram of a computing system; in FIG. 2 is a structural diagram of a central processor; in FIG. 3 - structure of the control word of the central processor; in FIG. 4 is a block diagram of a buffer instruction memory device, a control device, a buffer data memory device, and a control block of the buffer instruction memory device; in FIG. 5 is a structural diagram of a data switch; in FIG. 6 is a block diagram of an indexing block; in FIG. 7 is a structural diagram of a block for translating a mathematical address into a physical one; in FIG. 8 is a block diagram of a block of subprograms; in FIG. 9 is a structural diagram of an arithmetic logic device; in FIG. 10 is a block diagram of a communications switch of a central control unit of a computer system; in FIG. 11 is a block diagram of an interface device; in FIG. 12 is a block diagram of a data call-record block; in FIG. 13 is a structural diagram of a control computer operation algorithm.

The computing system (Fig. 1) is made in the form of the following modules of the shared memory devices 1-1 -1-8, M 16 central processors 2-1 - 2-16, N 8 input-output processors 3-1 - 3-8 , a commutator of 4 communication lines, K 8 software control blocks made in the form of control computers 5-1-5-8, for example, of the type EC-1845. In addition, the system contains an address and numeric bus 6 for exchanging information between central processing units and shared RAM devices 1, a command and numeric bus 7 for exchanging information between all central processors 2, and allows achieving the object of the invention with high reliability and survivability of the system by redundant modules. The presence of control computers 5 allows the system to have manual and automatic control of the system. 1 s.p. f-ly, 13 ill.

I / O processors 3, communication channels 8 for exchanging information between input / output processors 3, external storage devices, devices

I / O and data line processors, control bus 9 for transmitting interrupt signals between central processors 2, input / output processors 3 and devices 1

shared RAM, bus 10 and 11 exchange through a switch 4 communication lines between all processors, devices 1 of the shared RAM and control computers 5.

The central processor (Fig. 2) comprises an instruction buffer memory device 12, a control device 13, a data buffer memory device 14, a data switch 15, an arithmetic logic device 16,

data call-record block 17, indexing block 18, associative storage device 19, mathematical address to physical translation unit 20, interface device 21, local random access memory device 22, input / output switch 23, subroutine block 24, block 25

control the buffer memory device

commands, bus 26 - 1-26-4 data output in

buffer instruction memory device 12, data buffer memory device 14, associative memory 19 and subroutine block 24, instruction fetch bus 27, unpacked command buses 28-1 to 28-7, data fetch bus 29, 30-1 buses

-30-2 issuing operands from the data switch 15, buses 31-1 -31-3 issuing the results of operations from the data switch 15, buses 32-1 - 32-2 of the results of the operations of the arithmetic-logical device 16 and

call-record block 17, data transfer bus 33 from call-record block 17 to indexing block 18, address and data output bus 34 to associative storage device 19 and translation unit 20

the mathematical address to the physical, the bus 35 for issuing the address to the associative memory device 19 and the block 20 for transferring the mathematical addresses to the physical, the bus 36 for issuing the data to the device 14 and the unit 24 for subprograms, the bus 37 for issuing the addresses and data for the interface device 21, the bus 38-1 - 38-2 of the initial installation, buses 39-1 - 39-3 of the output of block 24 of the subprograms, bus 40 for controlling the selection from the device 12 of the buffer memory of commands, bus 14 for issuing command addresses to the interface device 21, bus 42 for decryption lock commands by significance bits.

Four instruction registers 43-46 of instruction numbers, an associative memory unit 47, an instruction number counter 48, an instruction index counter 49, and four instruction index registers 50-53 are included in the control unit 25 of the buffer instruction memory device (Fig. 4).

The control device 13 (FIG. 4) includes a command decryption counter 54, four command decryption registers 55-58, a control register 59, an instruction sample shifter 60, an instruction decompression shifter 61, three unpacked command field adders 62-64, block 65 buffer memory of the decompressed command.

The data buffer unit 14 (Fig. 4) includes a significance bit memory block 66, a stack buffer memory block 67, a read buffer memory block 68, and an output buffer memory block 69.

The data switch 15 (Fig. 5) includes a result memory block 70, result registers 71, operand switch 72, and result switch 73.

Indexing block 18 (Fig. 6) includes eight identical indexing nodes 18-1 to 18-8, each of which contains a block 74 of the buffer memory of commands, a block 75 of the buffer memory of descriptors of arrays, a register of 76 increments of the base, a register of 77 of the base , adder 78 generating the current address, adder 79 generating the current index, adder 80 generating the address of the write to the read buffer memory unit, adder 81 generating the new base value;

The block 20 for translating the mathematical address into a physical one (Fig. 7) includes eight identical associative memory nodes 82-1 - 82-8 and a node 83 of the table of RAM pages.

Each associative memory unit 82 includes an input buffer memory unit 84, an adder 85 for generating the next page address, a data buffer unit 86, an associative memory unit 87 for matching mathematical and physical addresses, and an adder 88 for generating the physical word address. The node 83 of the table of pages of random access memory contains a register of 89 base pages, the adder

0

5

0

5

0

5

0

5

0

5

90 forming address2 of line Slit1. a page table memory unit 91.

Block 24 of the subprograms (Fig. 8) includes a command decoder 92, base registers 93, additional base registers 94, a buffer information block 95 of the connecting information, control registers 96, and adder 97.

The arithmetic logic device 16 (Fig. 9) comprises addition units 98 and 99, multiplication units 100 and 101, logical conversions 102 and 103, division unit 104.

The communication line switch 4 (Fig. 10) comprises a system module switch 105, a control adapter 106 and a control panel 107.

The interface device 21 (Fig. 11) comprises a memory query switch 108, a memory data receiving switch 109, a destination address block 110, and a control and interrupt adapter 111, an initial state block 112;

The data call-recording block 17 (Fig. 12) includes an input register block 113, an adder 114 for generating a memory access address, an adder 115 for comparing the index and size of the array, a unit for generating a recordable number 116, an output address register 117, an output register 118 numbers.

The computer system is controlled by the algorithm (Fig. 13). The program is managed by the standard operating system 119 of the host computer 5 and includes bpsc 120 operator commands, the operator unit 121, the dispatcher 122, the system control unit 123, the telemetry unit 124, the display unit 125, the display archive 126, the 127 unit testing, archive of 128 tests. block 129 registration.

The control and clock circuits are not shown in the description.

The computing system operates as follows.

An operator with any of the control computers 5-1 -5-8 (Fig. 1) via buses 10 and 11 through the switch 4 of the communication lines performs the initial installation of the system modules and downloads the initialization program for the promotion of the operating system in the device 22 local random access memory of all central processors 2-1 - 2-16, the central processor having the lowest number in the system (in the case of the maximum configuration is processor 2-1), via bus 7 initializes the input-output processor 3-1. having the lowest number in the system, after which the latter sends the operating system via external channels 8 from an external

a storage device into a common random access memory 1-1 to 1-8.

The transmission path from the I / O processor 3-1 via the bus 7 to the I / O switch 23 of the central processor 2-1 and via the interface device 21 via the bus 6 to the RAM device 1. After completing this transfer, all the central processors 3 load the operating system via bus b from the devices 1 of the common random access memory into their devices 22 - the local random access memory and initialize the communication channels 8 in all input / output processors 3.

Subsequently, the computer system operates automatically under the control of the operating system, receiving tasks via the exchange channels 8. Synchronization of the parallel operation of the system modules is carried out by means of the control bus 9 by transmitting interrupt signals. General RAM devices 1 are used to store large arrays and general data of parallel-running processes on different central processors 2. Program codes and local task data areas are loaded from external memory through channels 8 by input / output processors 3 via bus 7, switch 23 an input / output device and a coupler 21 in the device 22 of the local random access memory of the central processors 2.

The control program of control computers 5-1-5-8 via buses 10 and 11 through switch 4 periodically collects telemetric information about the state of the modules of the computer system and signals the operator about emergency situations and the final results of the survey. In the presence of emergency situations, the automatic diagnostics of the emergency module is performed, as well as, if necessary, the automatic reloading of the operating system from the external memory

The computer system management program is launched as a separate task. The operator command block 126 is called first. This block 120 interprets the commands of the computer system operator in the form of a job sequence for the dispatcher 122. In addition, the block 121 of the automatic computer system operator can be called from block 120, which provides automatic control with the specified control functions.

Dispatcher 122 provides on request from blocks 120 and 121 the call blocks 123,

124, 125, archive 126, block 127, and also interacts with the host computer operating system 118 when exchanging data via a communication link and with external host computer devices (printing, magnetic disk drives).

The system control unit 123 executes commands for initial installation of the modules (resetting, setting initial values to registers, switching configurations), as well as loading the operating system into the device 22 of the local random access memory of the central processor 2.

The telemetry unit 124 collects information on the state of the modules and the operating modes of the modules of the computer system in a given volume.

The indicating unit 125 displays on the alphanumeric display of the control computer the state of the circuits of the modules of the computing system. To this end, information from the display archive 124 uses information about the methods of admitting to the desired module circuits and the types of their reflection on the screen

5 display.

Test unit 127 provides a load of test suite computing system modules for monitoring and diagnosing malfunctions. The call of the tests is performed using the archive of tests 126, which is a reference to the placement of tests on the NMD of the host computer.

The registration unit I29 provides

5, displaying on the screen a display and printing out emergency states of the modules of the computer system and the results of checking their functioning.

The presence of the same type of modules in the computing system allows one to achieve high performance by organizing their parallel operation. Due to a change in the number of modules, it is possible to build complexes of various capacities as applied to specific conditions. An important consequence of the modular organization is the high structural reliability of the computing system due to redundancy of the same type of modules and

0 link structures of type each to each. If there is a sufficient reserve, the computing system is practically trouble-free, and the computing process is continuous, thanks to the dynamic reconfiguration equipment, which automatically excludes the faulty module from the working configuration and the corresponding support of the operating system, which allows continuing calculations on the changing composition of the working configuration due to dynamic control computer system resources.

The ability to create completely isolated subsystems and a modular organization of control elements (several control computers with switching means for controlling actions) allows carrying out restoration and maintenance work without disrupting the operation of the main computing process.

Each central processor 2-1 - 2-16 operates as follows.

The initial installation of the processor proceeds via bus 11 through the interface device 21. It includes loading the operating system program of the RAM device 22 and setting the registers of the subroutine blocks 24 through the buses 38-1 and 38-2 and controlling the buffer device 25 of the instructions.

Block 25 downloads the program code from the device 22. To this end, it issues requests on the bus 41 through the interface device 21 to the device 22. The program code from the device 22 through the interface device 21 via the bus 26-1 enters the buffer memory device 12 these teams. The control unit 25 via bus 40 controls the selection of program code from device 12. Via bus 27, it enters the control device 13.

The control device 13 on the bus 28-2 issues a command to the arithmetic logic device 16 on the bus 28-3 to the call data recording unit 17, on the 28-4 bus to the indexing unit 18 on the 28-5 bus to the 24 subroutine block and on the bus 28-6 per block. 25 control on the bus 28-1 reads the operands from the device 14 of the buffer data memory, on the bus 28-7 controls the operation of the data switch 15, providing data transfer on the bus 29 from the device 14 and on the bus 32-1 of the results of operations of the arithmetic logic device 16 and a call record record unit 17. Data is fed to the information inputs of the operands of the arithmetic logic device 16 and block 17 via buses 30-1 and 30-2, respectively. On the bus 31-2, the indicated data enters the data buffer device 14 and on the bus 31-3 to the subroutine block 24. The data necessary for the operation of the indexing unit 18 is transmitted through the data call-recording unit 17 via the bus 33.

The main purpose of block 17 is scalar accesses to the memory device 1 for reading and writing. In the case of reading data to the device 14, the block 17 on the bus 34 provides addresses to the associative memory device i9 and uno.v 20 .. the mathematical address is transferred to the physical address. Upon a successful search in the device 19, data on the bus 36 is transmitted to the device 14, in the opposite case, the converted physical address from the block 20 via the bus 37 goes to the interface device 21 and then to the device 22 of the local random access memory or via bus 6 to the device shared memory 1-1 to 1-8. Data

 from device 22 or devices 1-1 to 1-8

via bus coupler 21

26-2 entered into the device 14 buffer

memory data and bus 26-3 to the associative storage device 19 in order to reduce access time for them in repeated calls.

When writing to the memory, the block 17 receives the address of the record via bus 30-2 and the number being written via bus 31-1. Further, the address and number on the bus 34 are issued to the device 19 and block 20. Recording to the devices 1 and 22 is performed unconditionally, and to the device 19 only if there is a cell with

the specified record address.

Indexing unit 18 is an array element address generator. Before the cyclic section of the program, array descriptors are loaded to block 18 through the data call-recording block 17 to the base 33, which will be accessed in the cyclic program and the program for generating addresses of array elements (address change step for each array used). In the cyclic section of the program, by command received via bus 28-4 from the control device 13, the indexing unit 18 on the bus 35 provides the required addresses of the array elements to the device 19 and the block 20 in the same way as described above for the data recording calling block 18.

The central processor 2 uses the long command word architecture (see Fig. 3) and controls the operation of devices based on static scheduling during the program translation stage. The command in processor 2 has a variable length and can reach 36 bytes. The maximum length command may contain seven arithmetic-logical operations (two additions, two multiplications, two logical operations and one division), an operation for the indexing unit 18 and a control transfer operation. The address and floor control commands provide the selection of eight operands from device 14. transferring them and seven results of previous operations to arithmetic logic device 16, recording four results of operations to device 14.

The control device 13 each clock cycle can issue a maximally unpacked command on the bus 28-2 and thereby ensure full loading of a parallel fully segmented arithmetic logic device 16.

Most of the blocks in processor 2 and the communications between them are in parallel.

Thus, the interface device 21 provides, in each cycle, the reading of up to eight words of data and instructions and the writing of two data words of the device 1 or 22.

The device 12 of the buffer memory of commands is executed according to a two-port circuit; in each cycle, it ensures the recording of eight and the reading of sixteen words of program code.

The buffer data memory device 14 is implemented in a 16 port scheme and provides for reading and writing eight data words in each clock cycle.

The data switch 15 provides the transfer of fifteen operands on the bus 30-1 to the arithmetic logic device 16 and on the bus 30-2 to the data call-recording unit 17 and the four results of operations to the device 14 via the bus 31-2.

The device 16 and the call-record unit 17 each clock output seven results of operations to the data switch 15 via the bus 32-1.

The indexing unit 18 generates eight each cycle on the bus 35, and the call-recording unit 17 on the bus 34 has two memory access addresses.

The associative memory device 19 processes two each clock, and the block 20 translates the mathematical address into a physical eight memory accesses.

The control unit 25 generates calls for eight control words each clock and provides control transfer in one of the four branch directions without interruptions in the decryption of commands.

Block 24 of the subprograms performs the preparation of the address context of the three procedural transitions and procedural switching (changing the contact and calling the program code) without pausing decryption of commands.

Thus, the structure of the central processor 2, due to the substantially parallel organization, is oriented towards vector computing. At the same time, the architecture of the wide control word makes it possible to use a parallel processor structure to organize parallelization of scalar computations. This is facilitated by the presence of a data switch 15, which provides quick transfer of results as operands to subsequent operations (reducing the influence of data dependencies), branching in one of 4 directions and conditional execution of several parallel branches of the program (reducing the influence of control dependencies) , fast procedural transition without suspension of decryption.

Control transfer is carried out in two stages. At the first stage, according to the transition preparation command, the transition index memorizes one of the registers of the 4346 command number, searches for the given index in the associative storage node

47i, issuing to the corresponding register index 50-53 a jump address instruction for the device 12 of the instruction buffer memory.

In case of unsuccessful search, counter

48, the command number issues to the interface device 21 via bus 41 a series of requests for the entire program code page, after which the program code passes through the interface device 21 via interface 26 via bus 26-1 to the instruction buffer device 12.

The read addresses of the commands on the bus 40 are sent to the device 12 and provide, during one cycle, 16 command words to the corresponding command decryption register 55-58 of the control device 13. In addition, the address is sent to the instruction index counter 49 to generate subsequent program code addresses .

The control unit 25 of the instruction buffer memory device can receive three transition preparation instructions, which ensures, at the second stage, the program branching branches the program in one of 4 directions (one to failure and three to transition) without interruption of decryption, so the codes all 4 directions are on registers 55-58 of command decryption. The branching is performed using the control register 59, into which conditional signs of the control transfer calculated by the relation commands in the arithmetic-logic device 16 are loaded via the bus 32-2.

The program code is stored in a packed instruction buffer device 12. This means that in any wide command, an arbitrary part of fragments may be absent and significant fragments are placed without gaps. Information on

the composition of significant functions is set by the scale field of the wide command (Fig. 3) and is used with the engines 60 and 61 to select and unpack the control device 13 when forming the executive unpacked presentation of the command.

In the formation of the executive form of the team involved counter 54 decryption commands. It stores the command decryption tact number assigned to the team when scheduling the execution of commands at the broadcast stage. This number is the base address when forming on the adder 62 numbers of clock cycles for outputting the results of operations contained in the command and on the adder 63 addresses of the results of previous operations stored in the result memory block 70 and used in performing operations of the current wide command. On the adder 64, read addresses are generated from the stack buffer and read blocks 67 and 68. For this purpose, the base addresses are transmitted to the adder 64 via the bus 39-2 from the block 24 of the subprograms to the indicated blocks of the buffer memory 67 and 68,

The unpacked instruction enters the block 65 of the buffer memory of the unpacked command and then via bus 28-1 to the device 14 of the buffer data memory (read operands), to the data switch 15 (selection of results, switching of operands and results), to the device 16 and blocks 17.18,24,25 (operation codes and short constants from the program code). The need for block 65 is caused by the possibility of disrupting the synchronous schedule of execution of commands due to the variable time of the operations of reading data from the main memory to the device 14 of the buffer data memory.

In some cases, at the stage of translation, it is not possible to determine the place of a variable in a hierarchical organized random access memory (associative storage device 19, devices 22 and 1-1 to 1-K). In other cases, the location of the variable over time may vary according to the calculated conditions.

These cases lead to the fact that when trying to read the operands from the data buffer device 14, it may turn out that the data has not yet arrived. This leads to blocking of the next wide command in block 65 and stopping the conveyor one step below block 65. The blocking is issued via bus 42 as a result of the check

the presence of operands in block 56;

When data arrives, the lock is released, the operands are selected from blocks 67 or 68, and through block 69 are sent to bus 15 via bus 29.

The presence of two buffer units 67 and 68 of the read memory stack in the buffer data memory device 14 is caused by the need to ensure high efficiency under conditions of mixed scalar vector computations. When working with data arrays, the device 14 is an intermediate buffer between the main memory and the arithmetic logic device 16, where the data is received, as a rule, for a single use. When performing scalar calculations, the working set of variables (stack) is reused. Combining 67.68 blocks in one block dramatically degrades the performance of buffer memory in scalar computing due to the crowding out of scalar variables caused by array elements.

The data switch 15 contains an independently controlled operand switch 72 and a result switch 73. The need for two switches is explained by the fact that at the beginning of the execution of a wide command the task is to distribute the operands to the actuators of the arithmetic-logic device 16, and then, as the operations are completed, they switch seven possible results in 4 write channels to the buffer memory device 14 these data. The results switch 73 is controlled by the code fragment determining the switching and recording addresses of the data buffer device 14 stored in the buffer memory unit 65 of the unpacked instruction.

This allows you to perform procedural switching with the combination of the beginning of the execution of the instructions of the new procedure and the end of the execution of the instructions of the leaving procedure, because write addresses to the device 14 are generated in the control device 13 at the time of decryption of the next wide command.

The results memory unit 70 allows solving the problem of switching the results of the performed operations not only at the end of each operation, but also for a certain time interval, which facilitates scheduling the program at the broadcast stage. The delay in the use of the results is specified by the special field of the result of the wide command (Fig. 3).

The result register 71 serves to accelerate the transfer of parameters from the start procedure to the start. A common way to transfer parameters is to write to the given cell of device 14. In cases where the transmitted parameters are the last calculated results of the starting procedure, and the starting procedure uses the last transmitted parameters in the very first commands, decryption may be suspended due to a temporary absence parameters. The introduction of result registers by several clock cycles reduces the delivery of parameters to the procedure being launched.

When working with data arrays, a significant place in the program code is occupied by the calculation of the addresses of the elements of arrays. However, as a rule, for some vector formula, the law of calculating the addresses of the elements of the arrays remains constant. This property is used in the organization of block 18 indexing. To create a high rate of address generation, the indexing unit 18 contains eight parallel nodes 18-3-18-8, each of which has a block 75 of the buffer memory of the array descriptors and a block 74 of the buffer memory of the operations, the contents of which are entered outside the cyclic section of the program bus 33 from block 17 call-record data. In fact, block 74 contains a program for accessing array elements, descriptors of which are stored in block 75.

When executing a cyclic section of the program, the control device 13 on the bus 28-4 issues in the indexing block 18 the command number in block 74. Then, all eight nodes of the indexing block 18 at the given number execute the command for calculating the address of the array element. Depending on the algorithm, the contents of blocks 74 and 75 at nodes 18-1 - 18-8 may be the same or different. In the first case, a high rate of access to one data array is created, in the second, multiple data arrays are accessed in parallel.

The address of the array element is generated on the adder 73 by adding the base address of the array with the value of the current index over the array. At adder 79, the value of the current variable is generated for the next call to the array (the progression in the array is changed by a step) and is entered into the block 75 of the buffer memory of the array descriptors.

Adders 80 and 81 are used to form destination addresses at block 68 by a read memory buffer. To provide access to block 68, the movable base method is used when in the cyclic program the address of the loaded cell remains constant and the base address for

of this access node can change in each cycle by the increment step of the base.

To this end, base registers 77 and 76 and base increments are provided at each node of the indexing block 18. At adder 80, the current destination address is generated in block 68, and at adder 81, the current base value is modified per increment. The new base value is entered into the base register 77, and the generated mathematical address of the array element and the destination address via bus 35 from all nodes are output to the associative storage device 19 and the block 20 for translating the mathematical address into a physical one.

In order to maintain a high rate of memory accesses, the block 20 for translating a mathematical address into a physical one contains eight nodes 82-1 - 82-8, each. of which, using the associative memory unit 87, the correspondence of mathematical and physical addresses provides the required conversion.

Filling block 87 is of a preventive nature. To this end, block 87 is made in a two-port scheme, and in parallel with the search for a match string at a given address, a search for the next Line of the next mathematical page is performed. For scalar calls, this is a page

with the current mathematical address increased by one, and for vector calls it is increased by the step of moving through the array. The formation of the address of the next page is performed by adder 85.

If there is no required line in block 87, a request is issued to the node 83 of the RAM page table. Block 1 of the memory of the page table contains a complete table of correspondence of mathematical and physical

random access memory.

An address is generated on the adder 90

. the required row of the table, and executed

reading from the memory unit 91 of the page table memory.

When organizing the page table, compression methods (such as H-coding) are used, in connection with which secondary access from the output of block 91 to its own input is possible.

The selected correspondence line is entered into the associative memory block 87 of the given node 82. Thus, against the background of calls to the current mathematical page, the correspondence line is swapped for the next mathematical page.

The input buffer memory unit 84 serves to store requests in the event that a search is performed in the node 83 of the table of RAM pages for the current mathematical page. After it is called, requests to the associative memory block 87 are repeated.

Adder 88 serves to form the physical address of the word (the physical address of the current page and the address of the word inside the page are added).

The data buffer memory unit 86 serves to store data recorded in the main memory for the period of converting the mathematical address of the record to physical.

On bus 37, physical addresses and data (in the case of recording) are provided to the interface device 21.

The filling of the block 91 of the memory of the page table and the register 89 of the base page is done via bus 34 from the block 17 call-record.

A subroutine block 24 prepares and switches contexts during procedural transitions. In this case, base registers 93 define the context of the current procedure, additional base registers 94 serve to create the context of the called procedures, block 95 of the buffer memory of the connecting information for storing the dynamic history of calls to incomplete procedures, and control registers 96 contain system-wide registers (timer clock, configuration registers, etc.).

Procedural switching as well as internal procedure control transfers are performed in two phases. In the preparation phase, the context is copied from the main base registers 93 to the additional base registers 94, hidden in the block 95 of connecting information of the context registers to be corrected during the procedural switching, the memory is left out or the context of the called procedure is formed in the additional base registers 94, transmitting the descriptor of the program segment to the control unit 25 for pumping the code of the called procedure into the device 12 buffer memory commands and the control device 13.

In the switching phase, the prepared context is transferred to the base registers 93 and switching to decryption of the program of the called procedure in the control device 13 and the control unit 25. Return to the procedure is performed in the same way, except that context correction is performed from the binder buffer memory block 95

information.

A fundamental point in the organization of block 24 of the subprograms is its asynchronous work on the preparation of procedural switching against the background of execution

the portion of the program prior to the procedural switch. This is because the software implementation of the procedural switching requires a noticeable size of the program code and will cause the pipeline to stop due to the waiting for the arrival of the elements of the connecting information from the shared memory devices 1-1 - 1-8.

Using stewards 5-1 - 5-8

The computer, as a means of controlling and displaying the state of the computing system, provides the possibility, in addition to manual, of automatic control and signaling modes

 emergency conditions. Separation of computer system models into independent subsystems requires the presence of several control computers 5-1 - 5-8 computers and their means of switching with computing modules

system.

A communications switch 4 allows the connection of eight EC 545 type 5 host computers to all modules of a computing system.

Computer command control adapter 106 connects the bus of the communication line 10 of the computer 5 to the bus of the communication line 11 of a given module of the computing system. The connection is controlled by the control panel,

where the operator manually sets the allowed combinations of computer connections and system modules. This ensures that the computing system is divided into subsystems by controls. Further

with computer 5, during the initial installation of a given subsystem, a closed configuration is created.

The data call-record block 17 performs the operations of generating a mathematical address with writing the result to the buffer data storage device 14, accessing the devices 1-1 to 1-8. 19, 22 for reading and writing, as well as the transfer of operands to block 18 indexing.

When forming a mathematical address with writing the result onto the stack, the operands (descriptor and index) from block 113 of the input registers are transferred to adders 114 and 115. where on adder 114 it forms a mathematical address by adding the address of the beginning of the array from the descriptor and index, and on the adder 115, the index is subtracted from the size of the array. The generated mathematical address through the output register 117 addresses is transmitted from the bus 32-1 to the second information input of the data switch 15 and then via the bus 31-2 to the third information input of the device 14 of the buffer data memory.

When accessing devices 1-1 to 1-8, 19 22 to read, the generated address from the output address register 117 via bus 34 is transmitted to the first address and information input of the associative storage device 19 and the first address and information input of the mathematical translation unit 20 addresses to physical.

When accessing the devices 1-1 to 1-8, 19, 22 by recording, an additional recordable number is issued along with the address on the bus 34.

Thus, the modular principle of constructing a computing system makes it possible to increase its reliability and survivability due to redundancy of the same type of modules, while the parallel fully segmented structure of the central processor provides high-performance information processing.

The introduction of the data switch central processor ensured the transfer of the operands from the buffer data memory device and the results of previous operations to the input of parallel-running blocks of the arithmetic logic device, which increased the performance of the computing system on scalar calculations by reducing the influence of the data dependency and the presence in the arithmetic-logical device of several devices of the same type, such as addition, multiplication, logical transformations, and in the index index block Pressing the parallel formation of access to several arrays or different elements of the same array increased the performance of the computer system on vector computations.

The introduction of the communication line switch and several control computers into the central control of the switch allows one to have manual and automatic control of the computer system.

Claims (2)

SUMMARY OF THE INVENTION 1. A computing system comprising central processing units, input-output processors of a shared memory device, the control inputs and outputs of which are connected via control buses to each other, a central control unit, the exchange input / output of which is connected via exchange buses of the same name inputs and outputs of central processors, input-output processors and shared memory devices, address and numerical inputs and outputs of each central processor are connected via the same bus with the same name GOVERNMENTAL inputs-outputs of all common operational devices. memory, inputs and outputs of communication with external devices of input / output processors are inputs and outputs of a system for connecting communication channels with external devices, each central processor comprising an interface device, a buffer device for command memory, a control unit for a device for buffer command memory , a control device, a buffer data memory device, an associative storage device, a unit for translating a mathematical address into a physical one, a data call-recording unit, an indexing unit, a subroutine unit, and rhyme-logic device, controllers, the first address and numeric inputs and outputs and exchange inputs and outputs of the interface device are the inputs and outputs of the central processor of the same name, the information output of the interface device is connected to the information input of the buffer command memory device, with the first information the input of the buffer data memory device and the information input of the associative storage device, the control output of the interface device is connected to the inputs of the conditions of the device control unit ohm of the buffer memory of commands and the block of subprograms, the output of the device of the buffer memory of commands is connected to the input of the commands of the control device, the output of which is connected to the address input of the device of the buffer memory of data, with the inputs of the command of the arithmetic logic device, data call-recording blocks, indexing, subroutines and control the device of the buffer memory of commands, the output of the indexing unit is connected to the address inputs of the associative storage device and the unit of translation of the mathematical address into physical, first address and inform the communication inputs of which are connected to the first output of the data call-recording unit, the second output of which is connected to the information input of the indexing unit, the output of the associative storage device is connected to the second information input of the data buffer memory device, and c. the first information input of the subroutine block, the output of the mathematical address translation unit to the physical is connected to the first input of the interface device, the second input of which is connected to the first output of the control unit of the buffer memory command, the second output of which is connected to the address input of the buffer memory command, output of the subroutine block is connected to the address inputs of the control unit by the device for the buffer memory of commands and the control device, with the second address and information inputs of the translation unit a mathematical address in a physical and associative storage device, characterized in that. that, in order to increase productivity in scalar and vector computations and reduce the time for executing control actions, a local random access memory device, an input / output switch and a data switch are introduced into each central processor, and the central control unit contains program control blocks and a switch communication lines, the first and second information inputs / outputs of which are connected to the input-output of the exchange of the central control unit and the input-output of the exchange of program control blocks with accordingly, the command and numerical inputs and outputs of each central processor are connected via the bus of the same name with the same inputs and outputs of all input / output processors, and in each central processor, the first and second information inputs and outputs of the input / output switch are connected to the address digital input and output of the central processor and the second address and numerical inputs and outputs of the interface device, respectively, the input-output of the exchange of the device of the local random access memory is connected to the input-output of the exchange The device is connected, the output of the control device is connected to the control input of the data switch, the first information input of which is connected to the information output of the buffer data memory device, the second information input is connected to the output of the arithmetic-logic device and the third output of the data recording call block, and first entry conditions control devices, RICH.CH operands of the data switch are connected to the information input of the arithmetic logic device and the first information input of the data call-record block, the information output of the interface device is connected to the second information input of the subprogram block, the output of the results of the data switch is connected to the second Q by the information input of the data call-recording unit and the third information inputs of the buffer data memory device and the subroutine block, the status output of the buffer data memory device is connected to the second input of the conditions of the control device, the control unit of the buffer command memory device containing instruction number registers, associative memory node, command number counter, command index counter, command index registers, the outputs of which are connected to the information input of the command index counter and the second output ohm of the control unit of the buffer instruction memory device, the first output of which is connected to the output of the counter of the command number, the address input, the condition input and the command input of the control unit of the buffer memory command are connected to the first, second and third information. the inputs of all registers of the command index, the outputs of which are connected to the information inputs of the counter of the number of commands and the associative memory node, the output of which is connected to the first information inputs of all registers of the command index, the second information inputs of which are connected to the output of the counter of the command index „Registers for command decryption, control register, counter for decryption of commands, shifters for fetching commands and unpacking commands, from the first to third adders for generating fields of the unpacked command and the buffer memory block of the unpacked co5 0 5 command, the output of which is the output of the control device, the command input of which is connected to the information inputs of all registers for decrypting commands and a counter for decrypting commands and the first information input of the control register, the second information input of which | is the first input of the condition of the control device, the output of which and the outputs of all the instruction decryption registers are connected to the corresponding information inputs of the instruction sample shifter, the output of which is connected to the information input of the command decompression shifter, the output of which is connected to the first information inputs from the first to third information inputs of the first and second adders to form the fields of the unpacked command are connected to the output of the counter for decrypting commands, the second information input of the third adder to form the fields of the unpacked command is the address input of the control device, outputs from the first to the third adders forming the fields of the unpacked command, the second input of the conditions of the control device and the output of the shifter of the unpacked command are connected to inf by the formation inputs of the corresponding fields of the unpacked instruction buffer memory block, the data buffer memory device contains a significance bit memory block, stack and read buffer memory blocks, and an output buffer memory block, the output of which and the output of the significance bit memory block are an information output and the status output of the buffer data memory device, respectively, the address input and the first to third information inputs of which are connected to the inputs of the same block of memory bits of significance and blocks of the buffer the stack and read memory, the outputs of the stack and read buffer memory are connected to the first and second information inputs of the output buffer memory block, the data switch contains the result memory block, result registers, operand and result switches, the outputs of which are operand outputs and the results of the data switch, respectively, whose first information input is connected to the first information inputs of the operand and result switches, the second and third information inputs of which are combined with the outputs of the results memory block and the results register, the information input of the results memory block is the second information input of the data switch, the control input of which is connected to the control inputs of the results memory block, operand switch and results switch, the output of which is connected to the information inputs of the results registers, the indexing block contains indexing nodes, each of which contains blocks of buffer memory for commands and array descriptors, base registers and base increments, sum Ator forming the current address, the current index, the write address and the new base value, data inputs, commands, inputs and outputs of indexing nodes are connected with similar inputs and the outputs indexing, and in each indexing node, the information input is connected to the corresponding information inputs of the blocks of the buffer memory of commands and descriptors of the array and base registers and increments of the base, the input of the command of the indexing node is connected to the control input of the block of buffer memory of commands, the output of which is connected to the control the input of the buffer memory block of the array descriptors, the outputs of which are connected to the information inputs of the adders forming the current address and index and with the first information input of the adder neither the write address, the output of which and the output of the adder forming the current address form the output of the indexing node, the output of the adder forming the current index is connected to the corresponding information input of the buffer memory block of the array descriptors, the output of the base increment register is connected to the first information input of the adder forming the new base value, the output which is connected to the corresponding information input of the base register, the output of which is connected to the second information inputs of the adders for generating the record address and the new value of the base, the block for converting the mathematical address to physical contains associative storage nodes and a table page node of random access memory, each associative storage node contains an input buffer memory block te, buffer data memory block, associative memory block and adders to form the address of the next page and the physical address of the word, first and second address information and inputs, and the address input of the input buffer memory of each of the associative memory unit connected to the homonymous input unit mathematical translation into physical addresses, the outputs of which are connected to the outputs of the adders forming the physical address of the word and the blocks of the buffer data memory of all associative storage nodes, and in each associative storage node outputs the buffer memory block are connected to the corresponding information inputs of the buffer data memory block and associative memory, adders to form the address of the next page, and physical address of the word, the output of the adder forming the address of the next page is connected to the first address input of the associative memory block, the first output of which is connected to the corresponding information input the adder of forming the physical. word address, the node of the table of RAM pages contains a memory block of the table of RAM pages, the adder of forming the address of the table row and the register of the page base, the information inputs of which and the memory of the table of RAM pages are connected to the first the address and information input of the block for translating the mathematical address into physical, the output of the page base register and the second outputs of the associative memory blocks of all associative storage nodes are connected to the corresponding the information inputs of the adder to form the address of the table row, the output of which is connected to the first address input of the memory block of the RAM page table memory, the output of which is connected to the second address inputs of the memory of the RAM table page memory block and the associative memory blocks of all associative memories nodes, the block of subprograms contains a command decoder, base registers, additional base registers, control registers, a buffer memory block of binding information and an adder, the output of which also the outputs of the base registers are connected to the output of the block of subprograms, the first to third information inputs of which are connected to the same inputs of the additional base registers, the block of buffer memory of the connecting information and control registers, the input to of the instruction of the subprogram block is connected to the echo of the command decoder, the outputs of which are connected to the control inputs of the basic registers, additional base registers, the buffer memory block of the connecting information and control registers, the input of the control information of which is connected to the input of the conditions of the subprogram block, the control outputs registers and the block of buffer memory of the connecting information is connected to the corresponding information inputs of the adder, the inputs and outputs of the exchange of the block of buffer memory of the connecting information are connected to the corresponding inputs and outputs of the same basic registers, the corresponding inputs and outputs of the exchange of which are connected to the corresponding inputs and outputs of the same name base registers. 2. The computing system according to claim 1, wherein the communication line switch comprises a computing system module switch, the first and second exchange inputs of which are the inputs and outputs of the communication line switch of the same name, the control adapter, the input- the exchange output of which is connected to the second input-output of the exchange of the communication line switch, and the output is connected to the control input of the switch of the modules of the computer system, the control panel, the output of which is connected to the input of the control adapter, SUIT - the index of the next command ШК - scale of significance of fields, commands CM - bottom switch control field & SC - read addresses from the buffer, data memory P - field of the result of the operation; AZP - address of the record of the results of the operation. Const-lole constants g cop - operation code field 3 FIG. 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