RU1777142C - Device for generating address of memory block replaced - Google Patents

Abstract

The invention relates to computing and is intended to determine a block to be replaced from a group of blocks in a buffer memory column organized according to a partially-associative principle. The number of elements in the buffer memory column is variable. When changing the number of elements in the column, the exact LRU algorithm is preserved. The invention can be used in computers and computer systems, computing devices and digital automation devices. The aim of the invention is to increase the productivity of the device by eliminating additional calls to disabled memory blocks. For this, a replacement address selection block has been introduced into the device, which allows you to determine the address of the most used buffer memory block to be replaced taking into account disabled buffer memory blocks tee. 1 s.p. f-ly, 5 ill. 10 s

Description

The invention relates to computing and is intended to determine the address of a block to be replaced from a group of blocks in a buffer memory column organized by a partially associative principle. The number of elements in the buffer memory column is variable. By changing the number of elements in the column, the exact LRU algorithm is maintained. The invention can be used in computers and computer systems, computing devices and digital automation devices.

When a general-purpose buffer memory is implemented in a computer, the partially associative principle of organization is most often used.

the fact that the buffer memory is conventionally presented in the form of a table, broken into rows and columns. An element of the table is a block, which is a unit of information transferred between the main memory and the buffer memory. To determine the presence of an addressable block of information in the buffer memory, the address of the buffer memory column is taken directly from the logical address register, and an associative search is performed on the column. In the absence of information in the buffer memory, it becomes necessary to replace one of the blocks in the buffer memory column. Algorithms that perform the function of selecting a candidate for substitution in the buffer memory column are called substitution algorithms.

A device is known that uses the LRU substitution algorithm and implements a write-through algorithm when recording. In accordance with this algorithm, when accessing the memory for each column of the buffer memory, a list is provided that accurately defines the chronology of accessing the blocks of a specific column of the buffer memory. The device comprises a state memory, an input encoder, a register, and an output encoder. If there is information in the buffer memory, when writing to the memory, information is written to both the buffer and the main memory. In this device, it is possible to disable buffer memory units. Moreover, in accordance with the LRU replacement algorithm, there may be situations when the selected block for replacement is disabled. In this case, blocks are exchanged between the main memory and the buffer memory in order to update the history list, although the information of the disabled block cannot be used. This leads to additional temporary loss, which ultimately increases the effective memory access cycle. The disadvantage of this device is the large amount of equipment and loss of memory system performance when disconnecting buffer memory blocks.

A device is known that uses the LRU substitution algorithm and implements a flag rewrite algorithm when recording. A feature of this device is the implementation of writing to memory. If during recording information is found in the buffer memory, then recording is performed only in the buffer memory, and the modification flag is set to one. If during the memory operation the information is absent in the buffer memory and the check box for replacing the replaced block is equal to one, then it is necessary to rewrite the replaced block in the main memory. After that, the requested block is transferred to the buffer memory. The disadvantage of this device is the inability to disable the buffer memory blocks, although the efficiency of the rewrite algorithm is higher than that of the write-through algorithm.

The technical solution closest to the invention is a device prior to selecting a replaceable element, comprising a code converter, a memory and a register, the first output of which is connected to the information output of the device and the first input of the code converter, the third input of which is connected to the information input of the device, and the output of the code converter with an information memory input, the address and synchronization inputs of which are connected to the address input

and the synchronization input of the device, and the memory output is connected to the information input of the register, the sync input of which is connected to the sync input of the device, and the second output of the register is connected to the second input

0 code converter. The number of memory words corresponds to the number of columns into which the buffer and random access memory are divided. The address of the buffer memory block consists of the column address and the block address in

5 column, Each memory word contains a history code indicating a sequence of accesses to the blocks included in the corresponding column of the buffer memory. When loading a new block from RAM into the buffer, the history code for the addressed column of the buffer memory is read from the memory. Moreover, the high-order bits that enter the output of the device are the address of the block to be replaced. When determining the presence of data in the buffer memory, all blocks of the addressed column are checked and a comparison code is generated that identifies the block that is being accessed. The comparison code is fed to the third input of the code converter. Using the old chronology code and the comparison code, a new chronology code is generated at the output of the code converter, which is written into the addressable memory word. The modification of the chronology code is carried out according to the LRU algorithm. The disadvantage of this device is that accurate tracking of the sequence of calls to

0 blocks of a buffer memory column are only possible for a fixed number of blocks, which reduces the functionality of the device. We sat down for the buffer memory provided block shutdown, then

5, when working with one or more disabled blocks, accurate tracking of the sequence of access to the buffer memory blocks of those columns in which one or more blocks are disabled is disrupted. This results in a loss of processor performance. If the buffer memory should work according to the rewrite algorithm, then it is necessary to switch to either write-through algorithms, which is essential

5 reduces the performance of the central processor, or significantly complicate the mechanism for tracking the history of accesses to blocks of buffer memory,

The aim of the invention is to increase the productivity of the device due to

exclusion of additional calls to disabled memory units.

This goal is achieved by the fact that in the device for generating the address of the replaced memory block, comprising a memory block, a register and a code converter, the output of which is connected to the information input of the memory block, the address input of which is the address input of the device, and the write enable input is / reading is combined with the control input of the register and is the synchronization input of the device, the output of the register is connected to the first group of inputs of the code converter, the second group of inputs of which is the first information input device, the information input of the register is connected to the output of the memory unit, a replacement address selection block is introduced, the first input of which is connected to the output of the register, the second input is the second information input of the device, and the output is the information output of the device.

In the proposed device, the formation of the address of the replaced block is carried out taking into account disabled blocks. For a plurality of included blocks, accurate hit history is maintained for all columns of the buffer memory.

Thanks to the introduction of an additional unit to select the address of the replaced buffer memory unit, the device's functional capabilities are expanded, productivity is increased, or equipment volumes in the proposed device are reduced in comparison with the known ones.

The memory capacity of the proposed device. where N is the number of columns of the buffer memory; L is the bit depth of the history memory word. The word spacing is determined by solving the inequality, where m is the number of lines of the buffer memory.

For known devices, a memory capacity of (M-1) / 2. For, in the proposed device, bits, and in analogue bits. With an increase in the number of lines, the gain in equipment is much higher.

The device provides the ability to disable blocks when machine errors occur in the buffer memory. Since the disconnect lines of the blocks gate the comparison signals, it is possible that the selected replacement block is disabled. This leads to additional accesses to the RAM until the LRU algorithm indicates a healthy (non-disconnected) block for replacement. In general, this leads to an increase in the effective memory cycle and, as a result, to a decrease in processor performance.

In a device that implements a flag rewriting algorithm, it is difficult to implement a block shutdown mechanism, since information is written only to a buffer memory block, which is selected from the main memory in place of the block.

0 to be replaced. For a simple implementation of the block shutdown mechanism, it is necessary to switch to a write-through algorithm. This leads to a decrease in processor performance.

5 In the device for selecting a replaceable element, exact tracking of the sequence of calls to the buffer memory blocks is carried out for a fixed number of buffer memory blocks, which narrows its functional capabilities. This device is the most economical of hardware costs known from the point of view. The use of this device in the buffer memory with the units turned off leads to the same disadvantages that are inherent in the devices described above.

The formation of the address of the memory block being replaced is illustrated by the example of a device in which the number of rows is 0 and the number of columns is 64.

In FIG. 1 is a block diagram of an apparatus for generating an address of a replaceable memory unit; in FIG. 2 - truth table of the code converter;

5 in FIG. 3 is a functional block diagram of a substitution address selection unit; FIG. 4, 5 are truth tables of an EEPROM on which a substitution address selection block is implemented. Address Generator

0 replaceable memory block (Fig. 1) contains memory block 1, register 2, code converter 3, substitution address selection block 4. The following notation is introduced: address input 5, clock input 6, code input equal to 5 or 7, input of trip bits 8 exit 9, information link 10.

Memory unit 1 stores history codes that reflect the exact order of accesses to the buffer memory blocks for all

0 columns.

The memory unit can be implemented on 5 memory elements with 64x1 bit organization.

Register 2 stores the history code from address 5 of the buffer column read from the memory unit 1.

The code converter (Fig. 1} generates a new chronology code by the value of the old code from the outputs of register 2 and the code compared to input 7. The code converter

3 can be implemented on an EPROM with 128x5 organization. The truth table of the code converter is shown in FIG. 2, where the bits of input 1 of the code converter are indicated by AO, A1, A2, A3, A4, and input 2 by A5, A6. The outputs of the code converter are indicated by Qo, SI, Q2, Oz, CU.

Two clock signals are received at synchronization input 6: SI1 to the first input of register 1 and SI2 to the first input of the memory unit.

The replacement address selection unit, which is a read-only memory (Fig. 3), is used to determine the most used block (device output 9) from among the unconnected blocks of the addressable buffer memory column by the read history code (register output 1) and bits disconnecting blocks (input of device 8). The address selection block contains an EPROM 12, an EPROM 13, an AND-NOT element 14, connected to the address inputs of AO, A1, A2, A3, A4 EEPROM 12 and 13, the input 8 of the device, indicated by BO, B1, B2, is connected to the address inputs A5 , A6, A7 EPROMs 12 and 13, and the input 8 of the device, designated VZ, is connected to the read enable input RD EPROM 12 and to the input of the AND-NOT 14 element, the output of which is connected to the read enable input RD EPROM 13, the outputs of which are connected to the mounting AND with the outputs of the ROM 12 and are the output 9 of the device. The truth table of the EEPROM 12 and 13 are shown in FIGS. 4, 5.

A device for generating the address of a replaceable memory unit may be connected to a computer processor, which includes a buffer memory constructed in accordance with a partially-associative principle and operating by a write-through algorithm or a flag rewrite algorithm. All external signals: memory block address 5, synchronization signals 6, comparison code 7, and trip bits 0 are received from the processor. The output of device 9 is provided to the processor.

The device operates as follows. The choice of a replaceable block about an addressable column is determined by the principle of the longest used, according to which the candidate for replacement is the block that has not been accessed the longest. Such tracking of the sequence of calls is carried out for each column of BP. Since the buffer memory is a 4-associative memory, it is necessary to store 24 combinations of codes that completely track the order of accesses to the blocks (lines) of the PSU. The order of calls can be set

in the form of a decimal combination, which is a possible permutation of the elements (rows) 0, 1,2, 3. So, for example, the combination 0132 means that the sequence

The BP accesses to the lines were as follows: the earliest access to the 0th line, then to the 1st, 3rd and last access to the 2nd line. For encoding 24 such combinations, 5 bits are required. Decoding

0 combinations in binary form are presented in table 1.

The binary value of the combination is encoded in such a way that the most significant two bits represent the PSU string, which has been used for the 5 longest time.

The address of the buffer memory column is supplied to the address input of the memory unit 1, from which an old combination of history is read and, according to SI 1, is received in the register

0 2. Information from the output of the register goes to the first input of the code converter, to the second input of which a comparison code is supplied from the input 7 of the device. In accordance with the truth table presented on

5 of FIG. 3, a new chronological state is generated at the output of the code converter, which is recorded by pulse SI2 in memory unit 1. After receiving the old chronological state in register 2, the binary chronological combination is fed to the first input of the output code converter block, to the second input of which bits disabling blocks for the addressable column of the buffer memory. Single state

5 signals on the lines BO, B1, B2, BZ means that the corresponding block of the buffer memory is operational, i.e. not disconnected. The zero state of the signal on the BO, B1, B2, and OT lines means that the corresponding block is turned off. The replacement address selection unit forms the address (code) of the longest used block from a plurality of unconnected blocks. The functional block diagram of the substitution address selection block (Fig. 3) is implemented on two EPROMs, combined at the output to the installation I. EEPROM 12 generates the address of the longest used unit if the OT signal is 1, i.e. the third block is not disabled, and the ROM 13 generates the address of the most long-used block if the OT signal is O, i.e. the third block is disabled. The truth tables of the EEPROMs 12 and 13 are shown respectively in FIG. 4, 5.

Shaping device operation

5 addresses of the replaced memory block can be considered in the following example. Let the address of the zero column of the buffer memory arrive at address input 5, and the sequence of calls to the blocks of the buffer memory 1320, i.e. the last appeal was to

block in line 0, and the longest used block is in line 1 and the same block is disabled. This state corresponds to binary combination 01101, which is read from memory 1 and received by SI 1 into register 2. From the output of the register, information is fed to the first input of the substitution address selection block. The second input of the replacement address selection block receives the disable bits of the blocks:, B,, VZ5-. Since the block in line 1 is disabled, the longest used of the blocks in line 1 is disabled, the longest used of the blocks s in lines 0, 2, 3 is the block in line 3. In accordance with the truth table for ROM 12, to the address input of which the value 01101101 is received, at the output of the substitution address selection block, signals are generated and, which corresponds to the block in line 3. If the information is not in the buffer memory, then the block in line 3 is replaced by the block from the main memory. Accordingly, the information after the exchange with RAM is located in the buffer memory, which leads to the development of a comparison code at input 7, equal to 11, which goes to the second input of the code converter, the first and second input of which receives the combination 01101. In accordance with the truth table a new history value 01010 is generated, which is written to memory 1.

Unlike the prototype, in the proposed device it was possible to increase productivity by eliminating additional calls to disabled memory units. This is achieved by introducing a replacement address selection block that generates the code of the most used block from among the unconnected blocks. The advantages obtained in the proposed device in relation to the prototype are determined by the type of algorithm used for the exchange of information between the buffer and random access memory.

When implementing an end-to-end recording algorithm in the buffer memory and using the proposed device with respect to the prototype, the effective memory access cycle is reduced due to the fact that the introduced replacement address selection block generates the code of the most used block from the number of included blocks, which avoids additional accesses to random access memory. In the end

This leads to a censure of processor performance.

When implementing a buffer rewrite algorithm with flags in the buffer memory

the use of the invention allows to expand the functionality of the device, since it involves the selection of the most used block from a fixed number of blocks. The implementation of the mechanism for disabling blocks in the prototype is extremely difficult, since information is recorded only in the buffer memory.

The introduction of a replacement address selection unit slightly increases the response time of the proposed device in comparison with the prototype. This does not lead to a deterioration of the time parameters of the buffer memory, since the determination of the most

a long used block is executed on

background of access to random access memory.

Claims (2)

1. A device for generating the address of a replaceable memory unit, comprising a memory unit, a register and a code converter, the output of which is connected to the information input of the memory unit, whose address input is the address input of the device, and the write-read enable input is connected to the control input of the register and is the synchronization input of the device, the register output is connected with the first group of inputs of the code converter, the second group of inputs of which is the first the information input of the device, the information input of the register is connected to the output of the memory unit, characterized in that, in order to increase the productivity of the device by eliminating additional calls to disabled memory units, a replacement address selection block is inserted into it, the first input of which is connected to register output, the second input is the second information input of the device, and the output is the information output of the device. 2. Device pop. 1, characterized in that the replacement address selection block contains a constant memory, the first group of bits of the address input of which is the first input of the block of choice of the address of replacement, the second group of bits of the address input is combined with a control input read-only memory and is the second the input of the replacement address selection unit, the read-only memory input is the output of the replacement address selection unit. I BLOCK REPLACEMENT CONTROLLER & vufarnots memory FIG. 2. f YU it B l M. Ґr J2 00 01 02 03 well l about w 02 ha Figz Elmee / Oro & i rshvm & M lo / o zf d doOO (/ 9 ізлнэчзЫор sntfat / goduB ogj. о notfijft gish urra & lemie device of left buffer paw / pi substitutions about the dollar with e.