RU1775858C - Veterby decoder output device - Google Patents

Abstract

The invention relates to computing and communication technology. Its use in digital data transmission equipment makes it possible to increase the noise immunity of a device that contains a clock synchronization unit, a recording address generator, a path memory address generator, a path tracking address generator, switches, a path memory unit, a path tracking unit and a decision block thanks to the introduction of additional the decision block and the comparison block, continuous tracking and comparison of the primary and secondary paths, the proximity of which determines the reliability solutions. 1 s.p. f-ly, 7 ill.

Description

The invention relates to computer and communication technology and can be used in digital data transmission equipment.

It is known the output device of the convolutional code decoder according to the Viterbi algorithm, which contains a memory unit, the information inputs of which are the device inputs of the same name, a buffer register, the outputs of which are connected to the corresponding information inputs of the device, a synchronization unit, the first input of which is the device output, a synchronization unit the first output of which is connected to the synchronization inputs of the memory block and the buffer register, the second and fourth outputs of the synchronization block are connected to the control input m storage unit, a control input and an input of the output register timing multiplexer data inputs of which are connected to respective outputs of the memory unit, and the output and control inputs are connected to the multiplexer

respectively, to the information input and the first (K-1) -th outputs of the buffer register, where K is the code restriction of the convolutional code.

The disadvantage of this device is the high hardware costs due to the register organization of the memory unit and the large number of communications, which reduces the reliability of the device.

The closest in technical essence is the output device of the Viterbi convolutional code decoder, which contains a clock synchronization block, the clock input of which is connected to the input of the path memory address generator and the clock input of the decision block and is the clock input of the device, the first output of the clock synchronization block connected to the input of the address generator of the record, the clock inputs of the address generator of the path tracking, decision block, memory block, paths, path tracking and control unit the first and second inputs

(L

WITH

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switches, the outputs of the path memory address generator are connected to the first information inputs of the second switch and the installation inputs of the path tracking address generator, the first outputs of which are connected to the second information inputs of the second switch, the outputs of the write address generator are connected to the first information inputs of the first switch and the control inputs of the block clock synchronization, the second output of which is connected to the control input of the path-tracking address generator, the second output which is connected to the control input of the decision unit, the outputs of the first and second switches are connected to the first and second information inputs of the path memory unit, the outputs of which are connected to the information inputs of the path tracking unit, the first outputs of which are connected to the information inputs of the decision unit and the second information inputs of the first switchboard.

The disadvantage of this device is the lack of information about the reliability of information symbols at the output of the device, and therefore, the noise immunity of the device when used in communication systems using cascade coding with external side codes and internal convolutional codes is reduced.

The purpose of the invention is to increase the noise immunity of data transmission equipment.

To achieve this goal, the output device of the Viterbi decoder containing a clock synchronization unit, the clock input of which, combined with the clock inputs of the path memory address generator and the decision block, is the device clock signal, the first output of the clock synchronization block is connected to the clock inputs of the write address generator , a path tracking address generator, a path tracking unit and control inputs of the first and second switches and a path memory unit, the information input of which l is an input device and an output coupled to an input tracking paths unit, the second output clock unit coupled to the control input of the tracking paths addresses, an information. whose input, combined with the first input of the second switch, is connected to the output of the path memory address generator, the second output of the address generator

track tracking connected to the control output of the decisive unit, and the first output to the second input of the second switch, the output of which is connected to senior

the bits of the address input of the path memory block, the low-order bits of which connect the output of the first switch, the first input of which, combined with the second input of the clock synchronization block, is connected to the output of the path memory address generator, and the second input, combined with the input of the decision block - with the output of the track tracking unit, a second decision block and a comparison block are introduced, whereby the clock and control inputs of the second decision block are combined with the clock and control inputs of the first decision block, the input is connected to eye tracking paths output unit, and an output ust0 roystva - a second input of the comparison unit, the first input coupled to an output of the first deciding unit, a clock input to a clock input of the first casting unit, and the output is a second

5 device output. .

Comparison of the main methods for increasing the noise immunity of communication systems shows that the cascade connection of external

0 block codes and internal convolutional codes with decoding of the latter according to the Viterbi algorithm. So, with the probability of error p, the maximum coding energy gain (CEC) is 5-6

5 dB for both block and convolutional codes. The use of a cascade system with an external Reed-Solomon code and an internal convolutional code makes it possible to obtain an EEC of 6.5-7.5 dB. The maximum EEC is achieved if eraser symbols (labels reliability indicating the least reliable information symbols).

5 Such an approach makes it possible to additionally increase the CEC of the cascade system by 1 dB, and, therefore, increase its noise immunity or throughput. Thanks to the introduction of the second crucial unit and

0 of the comparison unit, tracking of two independent continuous paths is provided and reliability labels are formed that indicate inaccurate characters, thereby increasing the immunity of data reception.

In FIG. 1 shows a block diagram of a device; in FIG. 2 is a comparison unit; in FIG. 3 is a diagram of an encoder forming a code decoded by the device; in FIG. 4-7 are diagrams illustrating the operation of the device.

The device comprises a clock synchronization unit 1, a recording address generator 2, a path memory address generator 3, a path tracking address generator 4, switches 5, a path memory unit 6, a path tracking unit 7, decision units 8 and a comparison unit 9. In FIG. 1, information and clock inputs 10, 11, information and control outputs 12, 13 are indicated.

Clock synchronization unit 1, recording address generator 2, path memory address generator 3, path tracking address generator 4, switches 5, path memory unit 6, path tracking unit 7, decision block 8.1 are made in the same way as similar units of the known device .

Decision block 8.2 is made in the same way as block 8.1. The comparison unit 9 (Fig. 2) contains an EXCLUSIVE OR element 14, the input of which is the first input of the comparison unit 9, and the second through the delay element 15 is connected to the second input of the unit.

The encoder on the transmitting side, generating a convolutional code with a code restriction length K to be decoded in the proposed device, contains (Fig. 3) a K-bit shift register 16, half adders 17 and a switch 18, as well as information and clock inputs 19, 20.

The code is defined by the links between the outputs of the bits of the shift register 16 and the inputs of the half adders 17. Denoting the presence of a connection between the register bit 16 and the input of the half adders 17 by the symbol 1, and the absence of communication by the symbol O, code generators (1011, 1101) are received, and introduced code generators in octal form, get (13, 15). The code restriction length of such a code is four. Information sequence 1 (D) is input to the shift register 16 and two channel symbols are generated over the duration of one information symbol using the switch 18. Thus, the code rate in this case is equal to R 1/2. In the general case, the code rate may be equal to R k / n, where k and n are positive integers, with k n. The convolutional encoder is a discrete automaton with a finite number of states and is completely described by a state diagram.

The state of the encoder refers to the contents of the three right shift registers. The state diagram contains all possible transitions of the encoder from one state to another (Fig. 4). Lattice convolutional chart is a scan of the chart

states over time (Fig. 5). On the grid, states are shown by nodes, and transitions by branches. The number of nodes at one step of the trellis diagram is N 2k 1. After

each transition from one state to another is shifted one step to the right.

The device is designed to operate as an output device as part of a known device for decoding a convolutional code and operates as follows.

Channel processing metrics branches of a known device provides

5 information clock pulses FI with a frequency two times lower than the channel frequency of the received sequence T (D), and in the phase corresponding to the correct separation of the sequence T (D) On the sequences TI (D) and Ta (D).

Block 1 clock synchronization during one pulse F generates at its first output a packet of N clock pulses FT, and at the second output - pulse end

5 cycles that are used in conjunction with the FJ pulses to synchronize the remaining blocks of the device.

At the information input 10 of the device for solving the channel for processing metrics, branches exist in the form of logical information about transitions (O is the upper path, 1 is the lower one) according to the trellis diagram of the convolutional code. From a consideration of a fragment of the trellis diagram for binary convolutional codes with speeds of 1 / n, where n is 1,2,3, ... (Fig. 5), it can be seen that the addresses of the nodes at the previous (when moving from left to right) step along the lattice can be obtained from the host address in the next step

0 by shifting to the right the binary code of the node address and substituting the transition information (O or 1) into the freed high-order bit.

Going up the trellis chart

5 from left to right, the decoder discards half of the branches included in the node, and the trellised diagram takes the corresponding form (Fig. 6), with only one branch entering each node. Conversion Information

0 is supplied to the control input of the path memory unit 6.

The output device of the Viterbi decoder provides storage of information about transitions along the trellis diagram and tracking of a continuous path. Since tracking to a depth L (5-6) K is sufficient, it is necessary to store information about transitions through N - 2 nodes at a length of L steps. Transition information is stored in block 6

memory paths, the address space of which is organized in the form of an address ring of length Cfig. 7). With such an organization, there is no need to shift the information along the length L. Only the address of the current step is modified according to the trellis diagram.

The transition address in the trellis diagram consists of the address of the node in which the transition is made (the lower part) and the address of the trellis diagram (the older part) (Fig. 6). Meanwhile, the path memory needed to store the transition information is M L N bits. When decisions are recorded, the addresses of the nodes are sequentially scanned by the shaper 2 of the write address and the address of the steps along the trellis diagram by the shaper 3 of the path memory address. Decisions are recorded in the path memory unit 6 at the received transition address, which is transmitted through the switches 5 (high and low bits of the path memory).

Continuous track tracking is performed from right to left in a trellis diagram. The address of the node from which the transition to this node is made is formed by the path tracking unit 7, which is a shift register, the input of which receives information from the output of the path memory unit 6. The node address in the previous step, formed by the path tracking unit 7, is supplied through the switch 5.1 (the lower-order bits of the path memory address) to the first address inputs of the block

6 paths. Read from block 6 of the memory paths, the information is fed to the input of the block

7 tracing the path that forms the new node address (Fig. 6). When tracing the paths, the addresses of the steps in the trellis diagram are moved by the path tracker 4 from the current address of the record, starting from the current recording address, in the opposite direction, for which the current address is transferred from the path memory address generator 3 to the path tracker 4.

Since at the end of tracing a continuous path to a depth of L steps, information about the K-1 oldest transitions is present at the output of the shift register of the path tracing unit 7, this information is provided to decision block 8.2 as a decoder decision. The decision block 8.1, the output of which is the information output of the device, converts the decoder decision from parallel to serial during K-1 information clocks FI

With sufficient path tracking depth in the output device of the Viterbi decoder, all paths emerging from the various starting nodes of the trellis diagram

merge into one. Therefore, in the proposed device, the initial tracking node is randomly selected and one continuous path is tracked only from the selected node, however,

Too many errors in the channel at the selected path tracking length do not merge. The introduction of another crucial unit allows obtaining information about another, continuous path,

5 traceable from an arbitrary node in another step of the trellis diagram. If the decisions made by the decision blocks coincide, then this means that the main and additional paths along the selected length

0 traces merged, which, in turn, indicates a small number of errors in the channel and, therefore, the reliability of the solution at the output of the decision block. In the case of mismatch of decisions on

At the output of the decision blocks, at the output of the comparison circuit, an unreliability signal is received by the decision decision block (erasure mark).

Since the label sequence

0 reliability at the control output of the device is delayed by K-1 clock cycles relative to the sequence of characters on the information output of the device, then if necessary, equalize the delays

5, a sequence of information symbols is transmitted through a delay element to K-1 clock cycles.

Thus, the proposed device can improve noise immunity

Claims (2)

0 digital data transmission equipment using cascade coding with internal convolutional codes by obtaining and then using information about the reliability of information symbols at the output of the device. The claims 1. The output device of the Viterbi decoder containing a clock synchronization unit, the clock input of which is combined 0 with the input of the path memory address generator and the clock input of the first decision block and is the device clock input, the first output of the clock synchronization unit is connected to the input of the write address generator, the clock inputs of the path tracking address generator, the first decision block, the path memory block, path tracking unit and control inputs of the first and second switches, the outputs of the path memory address generator are connected to the first information inputs of the second switch and the installation input the path tracking address generator, the first outputs of which are connected to the second information inputs of the second switch, the outputs of the recording address generator are connected to the first information inputs of the first switch and the control inputs of the clock synchronization unit, the second output of which is connected to the control input of the path tracking address generator the second output of which is connected to the control input of the first decision block, the outputs of the first and second switches are connected to the first and second information the input inputs of the path memory unit, the outputs of which are connected to the information inputs of the path tracking unit, the first outputs of which are connected to the information inputs of the first decision unit and the second information inputs of the first switch, characterized in that, in order to increase the noise immunity of the device, the second decision block and the comparison block, the clock inputs of which are connected to the clock input of the device, the output of the first decision block is connected to the first input of the comparison block, the second outputs of the block track tracking is connected to the information inputs of the second decision block, the control input of which is connected to the second output of the path tracking address generator, the output of the second decision block is connected to the second information input of the comparison block and is the information output of the device, the output of the comparison block is the control output of the block. 2. The device according to claim 1, characterized in that the comparison unit comprises a delay element and an EXCLUSIVE OR element, the first input of which is the first information input of the block, the information and clock inputs of the delay element are the second information and clock inputs of the block, respectively. the output of the delay element is connected to the second input of the EXCLUSIVE OR element, the output of which is the output of the block. Fia. 1 Nj 3 3 } IV i S § abut. 6 about u lo address and / aha Fa & .7