RU1775717C - Speed regulator - Google Patents

Abstract

The invention relates to speed controllers, for example, transporting a film in a wire feeder used in the printing industry. The purpose of the invention is to improve the accuracy of speed control and simplify the design. To achieve this goal, the frequency inverter 4 to the voltage is made in the form of an integrator with a reset

Description

The invention relates to speed controllers, in particular when transporting a film in a wire feeder used in the printing industry.

A frequency-to-voltage converter is known, supplemented by an output digital-to-tax conversion unit. To improve accuracy, it requires reduced speed and complexity.

A known speed controller comprising a series-connected analog comparison unit, a motor control unit and a pulse speed sensor, as well as a frequency to voltage converter, the output of which is connected to the first input of the analog comparison unit, a speed controller

A disadvantage of the described device is the decrease in the accuracy of regulation for

error counting in frequency to voltage converters. The accuracy of the regulation is largely offset by the presence of a digital integrator, and this complicates the design.

The purpose of the invention is to improve the accuracy of speed control and simplify the design.

This goal is achieved by the fact that in the speed controller, which contains a series-connected analog comparison unit, an electric motor control unit and a pulse speed sensor, as well as a frequency to voltage converter, the output of which is connected to the first input of the analog comparison unit and a speed controller, a frequency converter the voltage is made in the form of an integrator with a reset, the reset input of which is connected to

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the output of the pulse speed sensor, and the information input, with the output of the speed sensor, the reference voltage input of which is connected to the second input of the analog comparison unit, made in the form of an algebraic adder with averaging, the inputs of which are the inputs of the unit. The speed controller also contains a sample-storage unit, an information input and an output connected between the output of the integrator from the comparison unit, and a control input connected to the output of the pulse speed sensor.

Figure 1 shows a block diagram of the proposed speed controller and one of their embodiments of its blocks; Fig. 2 is a diagram of an operation of a frequency converter to a voltage.

The speed controller comprises a series-connected analogue comparison unit 1, an electric motor control unit 2, a pulse speed sensor 3, a frequency to voltage converter 4, the output signal of which Va is supplied to the input of the analogue comparison unit 1, and a regulator 5.

In operation, due to the feedback, the output signal of the sensor TD and the output signal of the transmitter Ud are stabilized. When the reference signal V3 changes, the output of the sensor etc changes, but the output signal of the Odd converter is still equal to the reference signal Vn. The presence of signals Vn and Ud at the inputs of Comparison Unit 1, which are unchanged over the entire range of reference, and what is especially important, the constancy of the steady-state value of Ud signal is a significant difference in the operation algorithm, which is due to the distinguishing features of the device.

The positive effect of increasing the accuracy of regulation is associated with an increase in the accuracy of operation of the frequency inverter to the voltage. Indeed, in the prototype, the output signal of the Ud converter must be equal to the reference signal Ut, i.e., it can change dozens of times. And at small values of Ud, the relative conversion error increases. In the proposed device, Ud is a constant value (in statics) and varies slightly (in dynamics) to provide feedback control. In this case, the steady-state value Ud can be selected in accordance with the optimal operating mode of converter 4. In connection with this, converter 4 can be assembled according to a simple scheme, a variant of which

contains a resettable integrator (elements 6-15) and can be supplemented by a sample-store at the output elements (16-22).

Since blocks 1 and 4 have increased accuracy due to the constant signal Ud, the static control error can be further reduced by introducing an integrating circuit (capacitor) 23 in the composition of block 1, which consists of a summing amplifier on elements 24-27

The operation of the embodiment 4 is illustrated in FIG. On the positive edge of the sensor signal, a short pulse generated by a circuit of elements 10, 11, 12, 14 discharges an integrating capacitor 13. The diode 15 is designed to accelerate the discharge, and

0 resistor 8 - to reduce the residual voltage on the diode, and the value of the resistor 8 can be the smaller the higher the power of the amplifier 6. After the end of the discharge pulse, the capacitor 13 is charged at a speed proportional to the reference signal U3.

Thus, the amplitude of the sawtooth voltage across the capacitor 13 (signal A) is proportional to the reference signal Y3

0 and inversely proportional to the frequency td.

In the simplest case, signal A can be used instead of the signal Ud, but to suppress the variable component at frequency Td, it is necessary to increase the capacitance

5 23, i.e. reduce system performance. So, as the frequency td increases, the amplitude and constant component of signal A decrease, the output signal of amplifier 27 increases, and with the appropriate choice of the structure of block 2, the feedback tends to decrease the frequency ffl.

When using one of the options for the sampling-storage scheme, the peak voltage of signal A is stored on

5 to the capacitor 18 (dashed curve B) and during a positive pulse td, which opens the electronic key 22, is transmitted to the storage capacitor 19. At a zero signal level td, the key 22 is locked, and

0, the capacitor 18 is discharged, but no more than to the voltage level A. Obviously, when the amplitudes of the pulses A are equal, the variable component on the capacitor 19 is absent, which allows

5 improve accuracy and speed.

To further reduce the static error, digital integration of the TD signal can be used with a correction action on the input. The task is similar to that described in

prototype. The master can be made in the form of a digital-to-analog converter or. in the simplest case, a potentiometer.

The positive effect of increasing the accuracy is due to an increase in the accuracy of the frequency converter into the voltage (see above), and the simplification of the design is due to the fact that in some cases this increase in accuracy eliminates the need for correction from a digital integrator. In addition, the connections indicated in the distinguishing features sharply reduce the requirements for the stability of the reference voltage (for which the power supply Vn is used).

The use of a regulator with a pulse sensor makes it possible to control the transportation speed with a high accuracy (by a digital indicator) and, if necessary, introduces a correction along the reference circuit. With a relatively simple circuit, the controller provides greater accuracy than EPU2. When preparing the unit for operation (that is, for the time during which the temperature control system enters the mode), the operator switches on the transportation drive and sets the required transportation speed using the dial 5. In this case, the real speed is monitored by the signal of the sensor fA with high accuracy by a digital indicator (this indicator is also intended to control other parameters of the wiring installation, i.e., it is not part of the speed controller.

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Since the analog part of the proposed speed controller has improved accuracy and stability, a single control of the real speed by a digital indicator is sufficient for stable operation of the installation throughout the entire shift.

Claims (2)

1. A speed controller comprising a series-connected analog comparison unit, an electric motor control unit and a pulse speed sensor, as well as a frequency to voltage converter, the output of which is connected to the first input of the analog comparison unit, a speed sensor, characterized in that, with In order to improve the accuracy of speed control and simplify the design, the frequency to voltage converter is designed as an integrator with a reset, the reset input of which is connected to the output of a pulse speed sensor, and in ormatsionny the input to output speed set point, the reference voltage input of which is connected to a second input of the analog comparison unit configured in the form of an algebraic adder with averaging, the inputs of which are block inputs. 2. The speed controller according to claim 1, with the exception of the fact that it contains a sampling-storage unit, an information input and an output connected between the integrator output with a reset and the first input of the analog comparison unit, and the control the input connected to the output of the pulse speed sensor. J S3 A (parad. 2