RU1772808C - Function generator - Google Patents

Abstract

Functional transducer relates to measuring technique and can be used in the construction of automated control systems. SUMMARY OF THE INVENTION: A functional converter comprises an operational amplifier integrating a capacitor, two switches, two groups of storage capacitors, a sample-storage unit, and a control unit. 1 ill.

Description

The invention relates to the field of information measurement technology, in particular, to functional

transducers m, and can be used in the construction of information-measuring systems.

Functional converters used in information measurement technology are known (see, for example, USSR Authors Certificate No. 661525, G 05 F 1/44, 1979, 1191892. G 05 F 1/44, 1985; positive decision dated 04/05/89 by application No. 4609227/24.

The device described in ed. testimonial. Mg 661525, contains an integrator, keys, a nonlinear code converter in time intervals, a control unit. The input value in this device is the code, and the output value is the voltage. This is due to the fact that the input code is converted to an intermediate value - time intervals, the physical realization of which is associated with the creation of rectangular pulses having an imperfect edge and a fall. A decrease in the error from imperfectly generated pulses is associated with an increase in their duration. As a result, this device has a low speed, which is its important disadvantage. The device described in ed. testimonial. No. 1191892, contains an operational amplifier, capacitors, switches, and a control unit. The input value of this device is a digital code, and the output is an alternating voltage of complex shape formed by piecewise-step approximation. This device can be used for a scaled voltage converter proportionally to a coefficient that is nonlinear depending on the input quantity, however, it has a low speed associated with the need to intermediate convert the input code into time intervals, i.e., with the formation of rectangular pulses

Joint venture

Xi

XI GO 00

about

00

the imperfection of fronts and slopes which limits the ability to reduce their duration, and therefore, increase the speed of the device. This is its disadvantage.

The closest in technical essence is the device (pos. Resolution from 5.04.89, application No. 4609227/24;. This device contains an operational amplifier integrating a capacitor, two switches, two capacitor arrays and a control unit. This device can be used as a functional scale converter that implements the potentiation function is the inverse of the logarithm, but it does not take into account the bias voltage at the input of the amplifier. Suppose that before starting the conversion, the voltage at the output the amplifier was equal to Uo, and the voltage at the input of the operational amplifier is 11 cm. Then, after the end of the first cycle, the voltage at the output of the device becomes

(Ux + UcM) CNiv

P

, CN2 UxCNj CnCn

where Cn is the capacitance of capacitor 2,

Ux - voltage at the input of the device, С N2

+ U00

After the end of the 2nd cycle (Ux + UCM) CNi

U

Cn

(1-tQh

After the end of the nth cycle

(UX + UCM) CN; ft

un

cn

J 1

H, n.

Using the formulas for geometric progression with IQ I 1, we obtain

N1

U ,.

- Un (Ux + UCM)

I-, and

N2

Therefore, an increase in conversion accuracy is associated with a decrease in UCM assuming unknown values. This is due to the use of high-precision operational amplifiers, however, it is impossible to completely eliminate the ISM and therefore we can write that the functional values of this device

f (Ni. N2, Ux, AT, At, 1cm),

where AT is the change in time,

At - temperature change, I - bias voltage

assumes not a specific scalar value, but falls into the interval. This is a disadvantage of the device.

An object of the present invention is to improve the accuracy of a functional converter.

The functional converter (see the drawing) contains an operational amplifier 1, the non-inverting input of which is connected to the device’s common bus, an integrating capacitor 2, the first cover of which is connected to the inverting input of the operational amplifier 1, switch 3, connected to the analog input of the device by the first input, a matrix capacitors 4, connected by the first plates of their capacitors to the outputs of the switch 3, switch 5, the outputs of which are connected to the first plates of the capacitors of the matrix b matrix20, and the unit is controlled and 7, connected to the digital input of the device, the first outputs are connected to the control inputs of switch 3, and the second outputs are connected to control inputs of switch 25 of switch 5, key 8 is connected to the first lining of the integrating capacitor 2 and to the inverting input of the operational amplifier 1, as well as to the output of the operational amplifier 1, key 9, connected to

30 to the second lining of the integrating capacitor 2, as well as to the output of the operational amplifier 1, the second inputs of the switches 3 and 5 are connected to the device’s common bus, the control inputs of the keys 8 and 9 are connected

35 to the third output of the control unit 7, and the sample-storage unit 10 is connected to the output of the operational amplifier 1, to the analog output of the functional converter and to the switch 5 and to the fourth output of the control unit.

An example of the construction of the control unit 7 can serve as a set of series-connected generator 11, pulse counter 12, decoder 13 and

45 matching patterns 14, as well as a decoder 15 with associated links.

By the Start command, the counter starts counting the pulses of the generator 11, the Decoder 13, decrypts the state of the counter 50 of the counter 12, generates control pulses F1, Ф2, ФЗ, Ф4, which arrive at the matching circuit 14 and at the control inputs of the keys 9 and 10 and the control input of the block sample storage. On match patterns

55, the output code of the decoder 15, which is the result of non-linear conversion of the input code of the device, is also received. The pulses from the output of matching circuits 14 are supplied to the switches 3 and 5, which connect the matrix capacitors 4 and 6, respectively, to the analog input of the device (matrix 4) and to the output of the sample-storage unit 8, which is the analog output of the device, The conversion process of the proposed device consists of several identical cycles. The cycle starts with the fact that the decoder generates the signal F1, which is input to the decoder 15. At this signal, the decoder gives a code that closes the keys of group B. The signal F1 also closes the key 9 and opens the key 10. As a result, the operational amplifier 1 turns into a repeater open key 10 prevents the discharge of capacitor 2. Matrix capacitors 1 and 6. connected by one plate to the inverting input of the operational amplifier, and the other to the device common bus are charged to UCM - bias voltage at the input of the operation Nogo amplifier 1. On signal F2 matrix capacitors 4 selected decoder 15 and coincidence circuit 14 are coupled to one plate of an analog input device, and the other to the inverting input of the operational amplifier 1.T. k. capacitors of matrix 4 were charged to voltage 1) See then, at signal F2, they recharge to voltage UX-UCM. As a result, recharging is associated with a change in charge equal to UXC4, where CA is the total capacitance of the connected capacitors of matrix 4, and is independent of UCM. This charge is transferred to the integrating capacitor 2. Similarly, by the signal ФЗ, the charge UeuxCe is transferred to the integrating capacitor 2, where Sat is the total capacitance of the connected capacitors of the matrix 6. The signal F4 selects the output voltage of the operational amplifier 1.

The capacitances of the capacitors of each of the matrices 4 and 6 are related to each other, for example, as the weights of the bits of a binary number, i.e., they can be equal to 2 ° С, 2 С, ... 2 С, where С is the capacitance of the capacitor of the corresponding bit do minimum weight. Thus, if codes Ni and N2 are received at the input of the device, which are converted by decoder 15 into codes M {and N2, respectively, which directly control switches 3 and 5, then the total charges transferred by matrices 4 and 6 to capacitor 2 are equal in this case

 2 ai2M UxCNi. i - 1

.xC f; bi2M lWCN12,

i - 1

where ai and bi are the binary digits of the 1st digits of the codes Ni and N2, respectively.

Suppose that before starting the conversion, the voltage at the output of the operational amplifier 1 was equal to U0. Then, after the end of the first cycle, the voltage at the output of the device becomes equal

lu-n + .. With N2

U14J ° + Cn

UxCNi

where O 1Cn With N2

Cn

+ UoQ

, Cn is the capacitance of capacitor 2.

After the end of the nth cycle

Ux С NI Ј, „j-1m,

Un p 2j Q + UoO.

-n j 1

where j is the sequence number of the cycle,, n.

Using the well-known formulas for geometric progression, we write an expression to determine the output voltage of the device after the end of the transient process, in steady state

Ni

U.

 N

i-i

30 To evaluate the gain in conversion accuracy, consider an example. Suppose we took 544UD2A as an operational amplifier, having a temperature drift of TKUcM 50 μV / ° С, during operation, the temperature changed by 30 ° С,, 1 V. For the prototype, we would get a relative error

(IIH + ISM) (- IOut + ISM) Sat, C 2 ISM SA

U

 uf

Cg

y -.

Ux

In this error, we do not take into account the time drift, which would introduce an error as well. The invention provided the functional converter with a significant increase in conversion accuracy, since its output voltage is invariant to the bias voltage of the operational amplifier, which largely depends on the ambient temperature.

Claims (1)

SUMMARY OF THE INVENTION A functional converter comprising an operational amplifier, the non-inverting input of which is connected to a common bus of the converter, an integrating capacitor, the first lining of which is connected to the inverting input of the operational amplifier, the first switch connected to the information input of the converter by the first information input, the first group of storage capacitors, the first plates of the storage capacitors which are connected to the outputs of the first switch, the second switch, you the passages of which are connected to the first plates of the storage capacitors of the second group, the control inputs of the first and second switches are connected to the corresponding outputs of the control unit, the input of which is connected to the control input of the converter, characterized in that, in order to increase accuracy, into it the first and second keys are entered, an I / j junction box, the output of which, which is the output of the converter, is connected to the first input of the second switch, the output of the operational amplifier is connected to the information input of the block storage and samples with the first outputs of the first and second keys, the second output of the first key is connected to the second plate of the integrating capacitor, the inverting input of the operational amplifier is connected to the second terminal of the second key and to the second plates of the storage capacitors of the first and second groups, the second information inputs of the switches are connected to the zero potential bus, and the control inputs of the fetch-storage unit, the first and second keys are connected to the corresponding outputs of the control unit.