RU1771063C - Digital power amplifier - Google Patents

Abstract

The invention relates to amplification technology and can be used to amplify the power of amplitude and frequency modulated signals. In a digital power amplifier, by creating a corrective voltage without using an adjustable power supply, high efficiency and reliability are ensured. The correction channel is made on a serially connected pulse shaper 13, a ramp generator 14, a comparator 15, a D-flip-flop 16 and an additional amplifier 17. The feedback circuit contains a series attenuator 18, an additional amplitude detector 19, an additional subtractor 20, an additional adder 21. The correction channel and the feedback target ensure that the envelopes of the input and output signals are completely consistent without loss of power due to the absence of an adjustable pi source Ani. 1 ill.

Description

h

Ј

VI VI

About About CO

The invention relates to amplification technology and can be used to amplify the power of signals with simultaneous amplitude and frequency modulation.

The purpose of the invention is to increase efficiency and reliability.

The drawing shows a structural diagram of a digital power amplifier.

The digital power amplifier contains an amplitude detector 1, a subtractor 2, a polarity detector 3, a phase inverter 4, a digital-to-analog converter DAC 5, two pairs of key amplifiers b (6 and 6), an adder 7, a low-pass filter 8, a load 9, two pairs of controlled keys 10 (10 and 10 g), analog-to-digital converter ADC 11, decoder 12, driver 13 pulses, generator 14, switch 15, D-trigger 16, additional amplifier 17, attenuator 18, additional amplitude detector 19, additional subtractor 20, additional adder 21 optional th key amplifier 22.

Digital power amplifier operates as follows.

With a small input signal level, the analog-to-digital converter 11 through the decoder 12, through the controlled keys 10 connects the key amplifier 16 of each pair to the output of the phase inverter 4 and, thus, in this state of the analog-to-digital converter 11, the key amplifiers b / and 6 of each the pairs are excited in antiphase and their output signals are mutually compensated in the adder 7. In this case, the input signal is amplified by an additional amplifier 16 and an additional key amplifier 22, the output signals of which are supplied to ummator 7 out of phase relative to each other by an angle corresponding to the level of the input signal envelope.

When the input signal reaches the first quantization level of the analog-to-digital converter 11, the decoder 12 connects through controlled keys 10 and 10 one of the pairs of key amplifiers 6 to the output of the amplitude limiter 3. In this case, this pair of key amplifiers is excited in phase. The output voltage of the amplifier in this case is determined by the total value of the output signal of one in-phase excited pair of key amplifiers 6 and the output signals of additional amplifier 7 and additional 1 key amplifier 22 angled relative to each other, ensuring that the envelope of the output signal corresponds to the level of the input envelope. By

as the input signal increases, various combinations of key amplifier pairs 6 excited in phase are connected to the adder 7, however, the output correction

The voltage between the quantization levels of the envelope of the input signal is carried out by changing the angle of shift between the output signals of the amplifiers 17 and 22.

The input signal of the additional key amplifier 22 comes from the detector of polarity 3, and the input signal of the additional amplifier 17 comes from the clocked D-flip-flop 16 and is formed as follows. To the output of the analog-to-digital converter 11, a digital-to-analog converter 5 is connected, which generates a signal that is a stepwise approximation of the envelope of the input and similar to the total output

voltage of common-mode pairs of key amplifiers 6.

The input from the subtractor 2 receives signals from the output of the digital-to-analog converter 5 and the amplitude detector 1, and

the differential signal from the output of the subtracter 2 is fed to the input of an additional adder 21.

If the envelope of the output voltage of the digital power amplifier at load 9 differs from the envelope of the input signal, a correction voltage is applied to the second input of the additional adder 21 from the output of the additional subtractor 20, the signals to which are received from

the output of the amplitude detector 1 and the chain of sequentially connected attenuator 18 and the additional amplitude detector 19. From the output of the additional adder 21, an analog signal is fed to

the first input of the comparator 15, to the second input of which a linearly varying voltage is generated, which is generated by the edge and slice pulse generators 13 and the linearly varying voltage generator 14 connected in series to the output of the polarity detector 3.

At the output of the comparator 15, pulses are generated, which are fed to the synchronization input of the clocked D-trigger 16 to the information input of which the signal comes from the output of the polarity detector 3, which provides the necessary phase shift of the output signal of the clocked D-trigger 16, which arrives at input of additional amplifier 17.

Thus, the introduced correction circuit (13, 14, 15, 16, 17) and the feedback circuit (18, 19, 20, 21) provide

increased efficiency and reliability of the digital amplifier.

Claims (1)

SUMMARY OF THE INVENTION A digital power amplifier comprising a series-connected SMPD detector, a subtractor and a series-connected polarity detector, a phase inverter, wherein the inputs of the amplitude detector and the polarity detector are combined and are the input of a digital power amplifier, as well as a digital-to-analog converter whose output is connected to the second input of the subtractors and n pairs of key amplifiers, the outputs of which are connected to the corresponding inputs of the adder, connected through the lower filter often to the load, while the input of the first key amplifier of each pair is connected to the output of the detector 3 polarity and the inputs of n pairs of controlled keys and the first of each pair of controlled keys is connected between the output of the detector of polarity and the input of the second key amplifier of each n pairs of key amplifiers, and the second between the output of the phase inverter and the input of the second key amplifier of each of the n pairs of key amplifiers, to the output of the amplitude the detector is connected in series with an analog-to-digital converter and a decoder, the outputs of which are connected to the control inputs of the keys under control, respectively, characterized in that, in order to increase the efficiency and reliability, a pulse shaper is connected between the output of the polarity detector and the additional input of the adder, generator, comparator, D-flip-flop, additional amplifier, series-connected att are inserted between the output of the low-pass filter and the second input of the comparator an enuator, an additional amplitude detector, an additional subtractor, an additional adder, and an additional key amplifier is introduced between the output of the polarity detector and the corresponding input of the adder, while the outputs of the analog-to-digital converter are connected to the inputs of the digital-to-analog converter, respectively, the output of the amplitude detector is connected to the second input of the additional subtractor , the output of the subtractor is connected to the other input of the additional adder, and the signal input of the D-trigger is connected to the output polarity detector.