RU173336U1 - SLink scalable universal communications interface - Google Patents

Abstract

The utility model relates to the field of computer technology, and specifically to data transmission and reception interfaces. The technical result is to expand the functionality by providing intermodular communication channels with a throughput balanced with the flow parameters between the specified modules in both directions. Scalable universal SLink interface contains two logical blocks located respectively in modules A and B, two output blocks of the interface transmitter (Slink TX Client), p located respectively in modules A and B, two input blocks of the interface receiver (Slink RX Client) located respectively in modules A and B, each output block 2 and 6 of the interface transmitter (Slink TX Client) contains a register of 7 headers (Header Array), a data register 8 (Data Array) and an output unit 9 of the transmitter (TX Link), each input unit 3 and 5 of the interface receiver (Slink RX Client) contains a register 10 headers (Header Array), a data register 11 (Data Array) and an input block 12 transmitters (RX Link). 3 ill.

Description

The utility model relates to the field of computer technology, and specifically to the interfaces of the reception and transmission of data.

The well-known "universal circular user interface with many states" [RF No. 2450320 C2, G06F 3/048, 05/10/2012] containing a content processing device, a user interface connected to the specified content processing device, and a processor located in the content processing device and intended for: activating a system for selecting a menu of states, creating a control set of functions related to an available application of the device, displaying at least one function from the specified control set of fu actions on at least one data input device included in said content processing device and activation of one of said at least one function displayed on said at least one data input device and included in said control set of functions after activating said at least one data input device.

The disadvantage of this interface is that it is used only in applications of mobile communication devices.

Closest to the claimed is a universal bidirectional serial data transfer interface and data transfer method [RF No. 2345401 C2, G06F 3/00, 01/27/2009] containing a transceiver unit configured to receive and transmit data that meets the USB specification (universal serial bus) ); a detecting unit configured to determine data received by the transceiver unit in order to determine whether it is necessary to convert the received data into data that conforms to a specific specification; and a conversion unit configured to convert the received data to data that conforms to a specific specification, after determining that the received data should be converted to data that conforms to a specific specification, and to convert transmission data that conforms to a specific specification to data that conforms USB specifications, for transmission through a transceiver unit.

The disadvantage of this interface is that it does not allow to organize inter-module communication channels with a throughput balanced with the flow parameters between the specified modules in both directions.

The technical result consists in expanding the arsenal of funds, that is, in realizing the purpose of the claimed universal interface of the communication channel.

The technical result is achieved by the fact that in the scalable universal interface of the communication channel containing a transceiver unit for receiving and transmitting data, it is further introduced that the transceiver unit is divided into an interface transmitter unit and an interface receiver unit, and two logical units located respectively are added to it in modules A and B, two output blocks of the interface transmitter and two input blocks of the receiver of the interface, each located in the corresponding modules A and B, the output of the logical block the ka located in module A is connected through the system interface of the transmitter to the input of the output block of the interface transmitter located in module A, the output of which is connected via the external scalable interface of the communication channel to the input of the input block of the interface receiver located in module B, the output of which is through the system interface the receiver is connected to the input of the logic unit located in module B, the output of which through the system interface of the transmitter is connected to the input of the output unit of the transmitter of the interface, data in module B, the output of which through an external scalable interface of the communication channel is connected to the input of the input unit of the interface receiver located in module A, the output of which through the system interface of the receiver is connected to the input of the logical unit located in module A, each output unit of the interface transmitter contains register of headers, data register and output block of the transmitter, the output of the register of headers is connected to the first input of the output block of the transmitter, the second input of which is connected to the output of the register o, the input of which is connected to the second input of the output block of the interface transmitter, the first input of which is connected to the input of the header register, and the output of the output block of the interface transmitter is connected to the output of the output block of the transmitter, each input block of the interface receiver contains the header register, data register, and input block receiver, the input of the header register is connected to the first output of the input unit of the receiver, the second output of which is connected to the input of the data register, the output of which is connected to the second output interface of the receiver unit, a first output of which is connected to the outlet header register, and an output interface unit receiver input coupled to the input of the receiver unit the input.

The introduction of these additional elements and the sequence of its connection provides the opportunity to expand the arsenal of funds, that is, to implement the designated universal interface of the communication channel.

In FIG. 1 shows a general diagram of a scalable universal communication channel interface.

In FIG. 2 shows a diagram of the output unit of the interface transmitter (Slink TX Client).

In FIG. 3 shows a diagram of the input unit of the interface receiver (Slink RX Client).

The scalable universal interface of the communication channel (Fig. 1) contains two logical blocks 1 and 4 located respectively in modules A and B, two output blocks 2 and 6 of the interface transmitter (Slink TX Client) located respectively in modules A and B, two input units 3 and 5 of the interface receiver (Slink RX Client), located respectively in modules A and B.

Each output block 2 and 6 of the interface transmitter (Slink TX Client) (Fig. 2) contains a header register 7 (Header Array), a data register 8 (Data Array) and an output block 9 of the transmitter (TX Link).

Each input unit 3 and 5 of the interface receiver (Slink RX Client) (Fig. 3) contains a header register 10 (Header Array), a data register 11 (Data Array) and a receiver input block 12 (TX Link).

The interface (Fig. 1, Fig. 3) contains two logic blocks 1 and 4 located respectively in modules A and B, two output blocks 2 and 6 of the interface transmitter (Slink TX Client) located respectively in modules A and B, two input units 3 and 5 of the interface receiver (Slink RX Client), located respectively in modules A and B, the output of the logical unit 1 located in module A, through the system interface of the transmitter (system TX interface) is connected to the input of the output unit 2 of the interface transmitter (Slink TX Client) located in module A, the output of which is through the External Slink interface connected to the input of input unit 5 of the interface receiver (Slink RX Client) located in module B, the output of which through the system interface of the receiver (system RX interface) is connected to the input of logic block 4 located in module B, the output of which is through the system interface of the transmitter (system TX interface) is connected to the input of the output unit 6 of the interface transmitter (Slink TX Client) located in module B, the output of which through the External Slink interface is connected to the input of the input unit 3 of the interface receiver (Slink RX Client) located in module A, the output of which is through system The th receiver interface (system RX) interface is connected to the input of the logical unit 1 located in module A, and each output unit 2 and 6 of the interface transmitter (Slink TX Client) contains register 7 headers (Header Array), data register 8 (Data Array) and the transmitter output unit 9 (TX Link), the output of the header register 7 (Header Array) is connected to the first input of the transmitter output unit 9 (TX Link), the second input of which is connected to the output of the Data Array 8, the input of which is connected to the second block input, the first input of which is connected to the input register 7 headers (Header Array), and in the output is connected to the output of the transmitter output unit 9 (TX Link), and each input unit 3 and 5 of the interface receiver (Slink RX Client) contains a header register 10 (Header Array), a data register 11 (Data Array) and a receiver input block 12 (RX Link), the input of the header register 10 (Header Array) is connected to the first output of the input block 12 of the receiver (RX Link), the second output of which is connected to the input of the data register 11 (Data Array), the output of which is connected to the second output of the block, the first output of which is connected with the output register 10 headers (Header Array), and the input is connected to the input of the input block 12 re Occupancy (RX Link).

The operation of the interface (Fig. 1, ..., Fig. 3) is as follows.

When organizing multiple channels of exchange between modules of the same type on the same chip, as a rule, a single interface is used for all modules, which has a fixed maximum throughput. Interface bandwidth is selected to cover the needs of the most demanding of the modules. At the same time, for channels whose bandwidth requirements are lower, the same interface and the same amount of hardware resources are used.

In the case of large inter-module distances and a wide range of bandwidth requirements for the channels used, this can lead to unjustified excessive use of hardware resources and complicate the routing of conductors on a chip, especially in cases where the bandwidth requirements of the most demanding channel are large. One way to solve this problem is to use the scalable universal SLink communication channel interface.

The SLink interface is switched (the same lines are used to transmit both parameters (address, command, etc.) and packet data) by a unidirectional bus. The width of the data / parameter line is a parameter that can be set in accordance with the required bandwidth, and the exchange protocol itself and the set of control signals are fixed. The data / parameter line width parameter is specified in bytes and can be set in increments of 1 byte in the range from 1 byte and above. For the organization of bidirectional exchange, separate SLink interfaces are used for each of the directions. Thus, the use of the SLink interface allows you to organize inter-module communication channels with a throughput balanced with the flow parameters between the specified modules in both directions, for example, between module A (Module A) and module B (Module B) (Fig. 1). To connect Slink controllers to the modules, the system TX / RX interface system interfaces A (B) are used.

To organize an exchange channel in one direction between a pair of modules, the user estimates the required throughput for the corresponding direction and selects, in accordance with the specified estimate, the data line width / parameters of the external interface of the transmitter-receiver pair of the SLink controller. In addition, the user sets the parameters of the system interfaces of the receiver and transmitter controllers, such as the width of the header lines and the width of the data lines, and writes them to the configuration file. The result of the script are two files: the receiver controller and the transmitter controller. If necessary, a similar procedure is performed for the channel of the reverse direction of exchange.

The set and parameters of system interface signals are determined by the variety of types of transmitted packets: if all transmitted packets consist of headers only, then there are no signals in the system interface.

For example, the transmitter module may generate only read requests and / or responses without data.

The location of the parameter fields in the header determines the efficiency of using the header compression function on the SLink interface. The greatest efficiency is achieved when the most frequently changing parameters are located in the lower bytes of the header.

The efficiency of using the header compression function when transmitting independent streams of request arrays depends on the frequency of rotation of requests from different streams. To achieve maximum efficiency, the arbitration of streams for transmission via the SLink interface must be carried out in batches of the maximum possible size, i.e. after N, where N = 1, 2, 3, ..., requests from one stream are transmitted M, where M = 1, 2, 3, ..., requests from another stream, and the higher the values of M and N, the higher the efficiency of use compression function.

Source module A or B keeps track of available resources in the remote receiver module using resource counters. The active signal level of the strobe release credit (wl free) in the current cycle means the release of one resource in the buffer of the remote receiver module and causes the increment of the corresponding counter. In the general case, the signal of the strobe for freeing credits (wl free) is multi-bit, each of the bits corresponds to a certain type of packet. Separation of buffers by packet type is not necessary and is carried out in accordance with the specifics of a particular receiver module. In the absence of separation of resources by type, the signal of the strobe of credit release (wl free) is single-bit. The issuance of the next packet by the source module is accompanied by decrementation of the corresponding counter. The package is issued from the source module only if there is a resource in the receiver module to store the specified package.

Multiple packets can be transmitted without waiting cycles between them. The transmission of the packet begins with the start sending at the signal of the beginning of the transmission of the packet (wl start = 1) and ends with the signal of the end of the transmission of the packet (wl stop = 1). Starting and ending packages can be combined. Packet transmission is fragmented. The current packet fragment is sending a header and / or data located on the packet header lines (wl header) and data in the packet (wl data), respectively, accompanied by the significance / size parameters of the header significance pointer (wl hptr) and data significance pointer (wl dptr) respectively. The end of reception of the current packet fragment from the source module to the transmitter of the SLink interface controller is confirmed by the controller by setting the confirmation signal (wl ack) to the active state. The values of the system interface signals set by the source module when issuing the next packet fragment cannot be changed until the receipt of the exposed fragment from the transmitter of the Slink interface controller transmitter acknowledgment signal (wl ack = 1). Fragmentation of the current packet fragments can be carried out continuously, which is possible only if the level of the confirmation signal is continuous (wl ack = 1), and with waiting cycles entered by the source module. The waiting cycle is the transmission of an empty non-start sending data on the signals of the beginning of the transmission of the packet (wl start = 0) and the data significance indicator (wl dptr = 0). Waiting cycles can only be entered due to a temporary lack of data from the source module. The formation of a wait cycle in a stop package (wl_stop = 1, wl_dptr = 0) is prohibited. In the starting package, both the header + data can be transmitted, and only the header, regardless of whether the packet contains data or not. When transmitting the header, the source module indicates the size of the significant part of the header on the packet header line (wl header) using the significance / size parameter of the header significance pointer (wl hptr). The size of the significant part is counted from the 0th byte of the packet header line (wl header). If the header of the current packet differs from the header of the previous packet only in N least significant bytes, the source module can (but is not required to) indicate the size of the significant part of the header wl hptr = N, and the value N = 0 is acceptable (this means that the header of the current package is exactly the same as the header of the previous package).

In non-starting packages, the transfer of the header is prohibited, as a result, the source module must set the header significance pointer (wl hptr = 0) for all the time when the start package is not issued, including for the time when the packets are not issued at all . When transmitting data, the source module indicates the size of the significant part of the data vector on the data line in the packet (wl data) using the significance / size parameter of the data significance pointer (wl dptr). The size of the significant part is counted from the 0th byte of the data line in the packet (wl data). It is recommended to organize the data output so that the bulk of the data fragments are displayed with a size corresponding to the full width of the data line in the packet (wl data). Failure to fulfill the indicated recommendation means the non-optimal choice of the line width parameter of the system data interface in the package (wl data) by the user.

The receiver module writes the received packet to the buffer. As space becomes available in the indicated buffer for the next packet, a one-cycle pulse of resource release on the wl free line is generated. In the general case, the signal of the strobe for freeing credits (wl free) is multi-bit, each of the bits corresponds to a certain type of packet. Separation of buffers by packet type is not necessary and is carried out in accordance with the specifics of a particular receiver module. In the absence of separation of resources by type, the signal of the strobe of credit release (wl free) is single-bit.

Multiple packets can be dispatched by the receiver of the SLink controller to the system interface without waiting cycles between them. The issuance of the packet starts with the start sending (wl_start = 1) and ends with the stop (wl_stop = 1).

The signals of the beginning of the transmission of the packet and the end of the transmission of the packet can be combined, in this case they are 1 wl start = 1 and wl stop = 1. The issuance of the package is fragmentary. The current packet fragment is sending the header and / or data located on the packet header lines (wl header) and the data in the packet (wl data), respectively. Send data followed by significance / size parameter wl_dptr. Fragmentation of the current packet fragments can be carried out both continuously and with waiting cycles entered by the receiver of the SLink controller. The waiting cycle is the transmission of an empty non-start sending data on the signals of the beginning of the transmission of the packet (wl start = 0) and the data significance indicator (wl dptr = 0). Waiting cycles may appear due to the accumulation by the receiver of the SLink controller of data from the external interface to output the vector of the full width of the data line in the packet (wl data). In the starting package, both the header + data can be transmitted, and only the header, regardless of whether the packet contains data or not. When issuing a header, the size of the significant part on the packet header line (wl header) is not indicated, the actual size of the significant part is determined by the type of transaction (tType field of the header). When issuing data, the size of the significant part of the data vector on the data line in the packet (wl data) is indicated using the significance / size parameter of the data significance pointer (wl dptr). The size of the significant part is counted from the 0th byte of the data line in the packet (wl data). In all issued parcels, except the stop one, the parameter data significance indicator (wl dptr) can take the values either “0” (lack of data) or W (W is the total width of the data line in the packet (wl data) in bytes). In the stop package (wl_stop = 1), the parameter wl_dptr can take any value from "1" to W inclusive, where W = 1, 2, 3, ....

Communication between module A and module B and vice versa (Fig. 1) is carried out via an external scalable interface of the communication channel (External Slink interface). Within each module, communication is carried out through the System TX interface system interface during transmission or through the System RX interface system interface when receiving packets.

In this case, the blocks (Fig. 1, Fig. 2) in each module perform the following functions.

Logical Block 1 (Logical Block), which is usually used as an external channel for receiving and transmitting information, connects to the interface, works with information, such as storage, processing, transmission, etc.

The logical block 4 (Logical Block) is designed to store the header of the transmitted packet.

The output unit of the transmitter 2 and 6 of the Slink interface (Slink TX Client) (Fig. 1) receives packets from the system interface (System TX interface), transcodes to the external SLink interface, and transfers information from the logical block.

The input unit of the receiver 3 and 5 of the Slink interface (Slink RX Client) receives the packet from the external scalable interface of the Slink communication channel (External Slink interface), transcodes to the system interface and transfers information to the corresponding logical blocks 1 and 4.

Block header registers 8 and 11 (Header Array) (Fig. 2) is designed to store the header of the transmitted packet.

The block of data registers 9 and 12 (Data Array) is designed to store the packet that is currently being transmitted.

Blocks 10 (TX Link) and 13 (RX Link) (Fig. 2) are the output of the transmitter and the input receiver blocks and respectively carry out serialization and transmission of information and deserialization and reception of information.

Thus, the use of the Slink interface, where Slink is a symbol, allows you to expand the arsenal of tools, that is, in the implementation of the designated universal communication channel interface.

Claims (1)

Scalable universal interface of a communication channel containing a transceiver unit for receiving and transmitting data, characterized in that the transceiver unit is divided into an interface transmitter unit and an interface receiver unit, and two logical units located respectively in modules A and B, two output units are added to it the interface transmitter and two input blocks of the interface receiver, each located in the respective modules A and B, the output of the logic block located in module A, through the system interface the transmitter is connected to the input of the output unit of the interface transmitter located in module A, the output of which through an external scalable interface of the communication channel is connected to the input of the input unit of the interface receiver located in module B, the output of which is connected to the input of the logical unit located in the receiver’s system interface module B, the output of which through the system interface of the transmitter is connected to the input of the output block of the transmitter of the interface located in module B, the output of which is through an external scale iruemy link interface connected to the input interface of the receiver input unit disposed in the module A, output of which through a system interface connected to the receiver logic block input, located in the module A.

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