RU172100U1 - DEVICE FOR INCREASING EFFICIENCY AND RELIABILITY OF PROCESSING CRYPTOGRAMS - Google Patents

Abstract

The utility model relates to radio engineering and can be used in systems with decision feedback (ROS) for receiving and processing signals on communication channels of low quality. The technical task of the device is to provide the required information processing modes with less hardware costs. The technical result is achieved by the claimed device increase of efficiency and reliability of processing of KRG includes two parallel lines, each containing a decoder of the “Request” combination, a feature analyzer correspondence, drive, two switches, logical element “AND”, three logical elements “OR”, two keys, the information input of decisive feedback of the first channel being connected respectively to the inputs of the drive, analyzer of the attribute of conformity, decoder of the command “Request” of the first line, and the information input of the decisive feedback of the second channel is connected respectively to the inputs of the drive, the analyzer of the sign of compliance, the decoder of the command "Request" of the second line, the outputs of the drives of the first and second channels of the connection are connected with the corresponding inputs of key 1 and switch 1, while the outputs of key 1 are connected to the inputs of the OR-1 element, key 2 and switch 2, the outputs of the analyzer of the sign of correspondence of the first and second channels are connected to the inputs of the OR-1 element and inputs drives of the first and second channel, while the outputs of the decoder of the Request command are connected to the inputs of the OR-2 element, the outputs of which are connected to the block of reception and transmission of the Request command, while the outputs of the block of reception and transmission of the Request command connected s with the inputs of the drives of the first and second channels and the key 1, the outputs of the key 1 are connected to the inputs of the element "And", the outputs of which are connected to the inputs of the element "OR-3", the outputs of which, in turn, are connected to the inputs of the key 2.

Description

The utility model relates to radio engineering and can be used in systems with decision feedback (ROS) for receiving and processing signals on communication channels of low quality.

A device for receiving diversity signals, comprising a coherent addition unit, a demodulation and decision unit, and series-connected switch, an averaging unit, a weight coefficient calculation unit, a maximum weight coefficient selection unit, a division unit, its second input being connected to the output of the weight coefficient calculation unit , as well as N receiving paths, each of which consists of a series-connected filter, a normalizing amplifier, a time delay unit, an adjustable attenuator, and which is connected to the input of the adder, a detector connected in series, the input of which is connected to the output of the normalizing amplifier, and the time distortion measurement unit, the output of which is connected to one of the inputs of the switch, and the memory unit, the input of which is connected to the output of the division unit, and the output to the second input of an adjustable attenuator (author certificate No. 1019650).

A diversity signal addition device (patent No. 2031543) is also known, comprising receiving channels including each receiving unit, a delay element, an adjustable attenuator, a detector, a signal information parameter measuring unit, a memory unit and a multiplier, a coherent addition unit, a demodulator, a switch, functional blocks converters, averaging block, maximum weight coefficient selection block, memory registers, correction correction memory block, and a control and synchronization block containing a pulse generator a sensor and a delay unit.

The disadvantages of the analogs are low noise immunity, as well as switching to the query mode on low-quality channels by signals from the analyzer sign of compliance, which reduces the speed of information transfer.

The closest technical solution adopted for the prototype is a device for increasing the speed of information transfer (patent 2007138359), containing two parallel lines, each containing sequentially located output drive, key, drive, analyzer sign of compliance, decoder command request; a common output drive, nine logical elements "OR", a logical element "AND", and the information input of the decisive feedback of the first channel is connected to the corresponding inputs of the drive, the analyzer of the sign of compliance, the decoder of the command request the first line, and the information input of decisive feedback of the second channel is connected respectively, with the inputs of the drive, the analyzer of the sign of compliance, the command decoder request the second line, the outputs of the output drives of the first and second channels are connected to the corresponding the first OR sixth logical elements OR, the outputs of which are connected respectively to the inputs of the common output drive, the output of the analyzer of the sign of correspondence of the first line is connected to the input of the logical element AND and the input of the seventh logical element OR, the output of which is connected to the input the key of the first line, while the output of the logical element "AND" is connected to the input of the ninth logical element "OR", the output of the analyzer of the attribute of correspondence of the second line is connected to the input of the logical element "AND" and the input of the eighth ogicheskogo element "OR", which is connected to the input key of the second line, the outputs of the decoders request command are connected to inputs of the ninth logic element "OR", the output of which is coupled to inputs of said seventh and eighth logic element "OR".

The disadvantage of the prototype is the structural complexity, requiring the implementation of individual blocks for each mode of operation of the device (mode "increase efficiency" or mode "increase reliability"), as well as the lack of the possibility of the device in combined mode.

The technical task of the device is to provide the required information processing modes with less hardware costs.

The technical result is achieved by the fact that the claimed device for increasing the efficiency and reliability of processing cryptograms (hereinafter - KRG) includes two parallel lines containing each decoder of the “Request” combination, an analyzer of the sign of compliance, a drive, two switches, a logical element “I”, three logical “OR” element, two keys, the information input of the decisive feedback of the first channel being connected respectively to the inputs of the drive, the analyzer of the sign of compliance, the decoder of the command “ inquiry ”of the first line, and the information input of the decisive feedback of the second channel is connected respectively to the inputs of the drive, the analyzer of the attribute of compliance, the decoder of the command“ Request ”of the second line, the outputs of the drives of the first and second channels are connected to the corresponding inputs of the key 1 and switch 1, while the outputs key 1 are connected to the inputs of the element "OR-1", key 2 and switch 2, the outputs of the analyzer sign of compliance of the first and second channels are connected to the inputs of the element "OR-1" and the inputs of the drives of the first and second channel, while the outputs of the decoder of the Request command are connected to the inputs of the OR-2 element, the outputs of which are connected to the blocking element for receiving and transmitting the Request command, while the outputs of the blocking element for receiving and transmitting the Request command are connected to the inputs drives of the first and second channels and the key 1, the outputs of the key 1 are connected to the inputs of the element "And", the outputs of which are connected to the inputs of the element "OR-3", the outputs of which in turn are connected to the inputs of the key 2.

The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features that are identical to all the features of the claimed technical solution are absent, which indicates the compliance of the claimed device with the patentability condition of "novelty".

Search results for known solutions in this and related fields of technology in order to identify features that match the distinctive features of the claimed object from the prototype showed that they do not follow explicitly from the prior art. The prior art also did not reveal the popularity of the influence provided by the essential features of the claimed utility model of transformations on the achievement of the specified technical result. Therefore, the claimed utility model meets the condition of patentability "inventive step".

The claimed method is illustrated by figure 1. Used in the figure of the designation:

Bl.Prm. "Inquiry" - receiver lock and transmission of the “request” combination; DshKZ - Request combination decoder APS - Conformity Analyzer N - Storage device P1, P2 - switch one, switch two Cl1, Cl2 - One key, two key About € - efficiency mode D - reliability mode TO - a comprehensive mode of increasing efficiency and reliability OR - logical element "OR" AND - logical element "AND"

Declared as a utility model, the technical solution provides the ability to work in the modes: "increase efficiency", "increase reliability", "combined" mode.

The positive effect of the claimed technical model as a utility model is ensured by the implementation of the claimed functions due to lower (in relation to the prototype) hardware costs.

The device operates as follows.

Switching the parallel operation device to the "increase efficiency" mode of transmission ("O" mode) is carried out by switch P1. When the correct combinations are received on both channels, they are transmitted through the channel accumulators H, the contacts of the P1 switch in the “O” mode, the OR-3 circuit, and the Kl2 key are supplied to the information recipient.

When receiving a combination with a detected error in one of the channels, the equipment of this channel blocks the drive of this channel by a signal from the channel APS, preventing the recipient from outputting the distorted combination. Information in this case passes from another channel, including with an undetected error, through drive N, contacts of switch P1 in the “O” mode, OR-3 circuit, Kl2 key to the information recipient.

All possible decisions that the system makes in the “O” mode, depending on the combinations taken, are given in table 1.

In case of receiving an undistorted combination through one of the channels and a combination with an undetected error in another, a double outcome is possible:

in case of distortions of the type “1” → “0”, the recipient is given the correct combination;

in case of distortions like "0" → "1", the receiver is given a combination with an undetected error.

In the mode of increasing the reliability of "D", in addition to the nodes operating in the previous mode, a device for bitwise comparing the elements of the received code combinations is connected using the switches P1 and P2. In this mode, the blocking of the ROS equipment receivers and the installation of the system in the request mode are carried out:

in cases of receiving a signal "request" on one of the channels. Then, from the output of the “request” combination decoder of this channel, the unit blocks the receiving device through the OR-2 circuit and issues a command to transmit the “request” signal to the transmitting device;

if an error is detected in one of the channels, when the unit from the output of the APS of this channel blocks the drive H and blocks the receiving device through the OR-1 and OR-2 circuits and issues a command for transmitting the “request” signal to the transmitting device;

in the event of a discrepancy in at least one of the digits during the element-by-element comparison of the code combinations received on both channels, in the logical element “I” through the channel accumulators H, the contacts of switch P1 in mode D. Then the unit from output Cl1 is sent to the lock Cl2, prohibiting the issuance of Cl2 information to the recipient and simultaneously through the logic elements OR-1 and OR-2 blocks the receiving device and issues a command to transmit the signal "request".

The system solutions developed depending on the combinations taken are shown in table 2.

Upon receipt of undistorted combinations through both channels, they are issued to the recipient, as in the “O” mode. If, on one of the channels, “request” combinations come up or with an error detected, then a signal is given through the OR-2 and OR-1 circuits, respectively, to block the receivers of the POC equipment and put the system in query mode. In this case, combinations to the recipient and to the bitwise comparison device are not issued.

When one of the channels receives an undistorted combination, and in another combination with undetected errors, they are transmitted through the channel accumulators H, the contacts of the switching device P1 are sent to the bitwise comparison device, made on the element "I". The bitwise comparison device registers the mismatch of the elements, blocks the output of these combinations to the recipient by sending a signal from the output of the And element, contacts of the P2 switch in D mode, the output of the Cl1 key to lock Cl2, and simultaneously through the logic elements OR-1 and OR-2, the signal is transmitted to block the receiving devices and commands for transmitting the signal "request".

Only in one case, in this mode, the recipient is given false information. This occurs when combinations with undetected errors are received on both channels, and provided that the errors in both combinations are identical. The probability of such an event is determined by an infinitesimal quantity.

Thus, we can conclude that the “D” mode of the system provides a very high reliability of the received information.

The “K” mode is complex, that is, it simultaneously uses the algorithms described for the two previous modes “O” and “D”. Switching the device to the "K" mode is carried out by the switches P1 and P2.

When an error is detected in one of the receiving devices, the signal from the APS of this channel is blocked by Cl1 and thereby the bit-by-bit comparison device is turned off, the drive H of this channel is blocked, prohibiting the delivery of information to the recipient, and at the same time a signal is transmitted through the logical elements OR-1 and OR-2 blocking the receiving device and issuing a command to transmit a “request” signal.

The recipient receives information not only when the correct combinations are received on both channels, as in the “D” mode, but also when the correct information is received on one of the channels, and an error is detected on the other channel.

In this case, the signal from the output of the APS channel, through which the distorted combination is received, blocks the drive H of this channel and the key Kl1. That is, the delivery of distorted information to the recipient is blocked and the bitwise comparison device is turned off. The correct combination is through a different channel through the drive H, the contacts of switch P1 in the "K" mode, through the element OR-3, the key Kl2 is issued to the recipient.

That is, this program of work provides for a decrease in the number of requests sent, due to a slight increase in the probability 5 of receiving distorted signals.

The decisions that the system makes, depending on the combinations taken, are summarized in table 3.

Claims (1)

The device for increasing the efficiency and reliability of cryptogram processing includes two parallel lines, each containing a request request decoder, a correspondence attribute analyzer, a drive, characterized in that the device includes two switches, an AND logical element, three OR logical elements , two keys, and the information input of the decisive feedback of the first channel is connected respectively to the inputs of the drive, the analyzer of the sign of compliance, the decoder of the command "Request" of the first line ii, and the information input of the decisive feedback of the second channel is connected respectively to the inputs of the drive, the analyzer of the attribute of compliance, the decoder of the command "Request" of the second line, the outputs of the drives of the first and second channels are connected to the corresponding inputs of the key 1 and switch 1, while the outputs of the key 1 are connected with the inputs of the element "OR-1", key 2 and switch 2, the outputs of the analyzer sign of compliance of the first and second channels are connected to the inputs of the element "OR-1" and the inputs of the drives of the first and second channel, at the outputs of the decoder of the Request command are connected to the inputs of the OR-2 element, the outputs of which are connected to the block of reception and transmission of the Request command, while the outputs of the block of reception and transmission of the Request command are connected to the inputs of the drives of the first and second channels and key 1, the outputs of key 1 are connected to the inputs of the “AND” element, the outputs of which are connected to the inputs of the “OR-3” element, the outputs of which, in turn, are connected to the inputs of the key 2.

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