RU169671U1 - Variable Division Frequency Divider - Google Patents

Abstract

The proposed utility model relates to automation and computer engineering and can find application in measuring and computing devices. A frequency divider with a variable division coefficient contains a counter, a register, a code comparator, the first logic circuitry NOT and the second logic circuitry NOT, the counter input is an input of the device clock frequency and is connected to the input of the first logic circuitry NOT. The output of the first logic circuitry is NOT connected to the enable input En of the code comparator and the reset input R of the RS trigger, the output of the RS trigger is the output of the divider with a variable division coefficient. The register output is connected to the first input of the code comparator, and the counter output is connected to the second input of the code comparator, the output of the code comparator is connected to the input of the second logic circuit NOT, the output of which is connected to the installation input S of the RS-flip-flop. The register data input is a device data input, the register recording input is connected to the input of the device recording signal. To ensure the possibility of issuing a predetermined frequency immediately after writing a new conversion factor into a frequency divider with a variable division ratio, an OR logic circuit is introduced, while the RS-trigger output is connected to its first input, the second input of the OR logic circuit is connected to the register recording input, and the output logic circuit OR connected to the reset input R of the counter.

Description

The proposed utility model relates to automation and computer engineering and can find application in measuring and computing devices.

Frequency dividers with a variable division coefficient are known (see Studfiles.ru> preview / 1718467, lecture 7, Counters with an arbitrary conversion factor, Fig. 2), containing an n-bit counter whose outputs are connected to a decoder whose output is connected to the reset input counter.

The disadvantage of this device is the unreliability of resetting the counter and the inability to automatically control the conversion factor of the frequency divider.

The closest technical solution to the proposed one is a frequency divider with a variable division coefficient (see Patent No. 163222 dated 06/20/2016, "Frequency divider with a variable division coefficient" authors Slepova Yu.V., Makeeva A.V., Tsishuk A.A. ., Cherkasova V.A.) containing a counter whose input is the device’s clock frequency input and is connected to the input of the first logic circuit NOT, the output of the first logic circuit is NOT connected to the reset input R of the RS-flip-flop, the output of the RS-flip-flop is the output of a divider with a variable division factor and by is connected to the R input of the counter, while the output of the register is connected to the first input of the code comparator, and the output of the counter is connected to the second input of the code comparator, the output of the code comparator is connected to the input of the second logic circuit NOT, the output of which is connected to the setup input S RS-flip-flop, input register data is a device data input, a register write input is connected to the device write signal input, while the output of the first logic circuit is NOT connected to the enable input En of the code comparator.

The disadvantage of this device is its low speed due to the long tuning time for frequency output after recording a new value for the conversion factor of the frequency divider.

The objective of the proposed utility model is to increase the speed of the divider with a variable division ratio.

The technical result of the proposed utility model is the ability to issue a given frequency immediately after recording a new value for the conversion factor of the frequency divider.

The essence of the utility model is that a frequency divider with a variable division coefficient contains a counter, a register, a code comparator, the first logic circuitry NOT and the second logic circuitry NOT, the counter input is the input of the device clock frequency and connected to the input of the first logic circuitry NOT. The output of the first logic circuitry is NOT connected to the enable input En of the code comparator and the reset input R of the RS trigger, the output of the RS trigger is the output of the divider with a variable division coefficient. The register output is connected to the first input of the code comparator, and the counter output is connected to the second input of the code comparator, the output of the code comparator is connected to the input of the second logic circuit NOT, the output of which is connected to the installation input S of the RS-flip-flop. The register data input is a device data input, the register recording input is connected to the input of the device recording signal.

What is new in the proposed utility model is that an OR logic circuit is introduced, while the output of the RS-flip-flop is connected to its first input, the second input of the OR logic circuit is connected to the register entry input, and the output of the OR logic circuit is connected to the reset input R of the counter.

The introduction of new nodes and connections made it possible to issue a given frequency immediately after recording a new value for the conversion factor of the frequency divider.

In FIG. 1 shows a diagram of a frequency divider with a variable division ratio,

In FIG. 2 is a diagram of the operation of the device.

A frequency divider with a variable division coefficient contains a counter 1, a first logic circuit NOT 2, RS trigger 3, register 4, a code comparator 5, a second logic circuit NOT 6, a logic circuit OR 7.

The input of counter 1 is the input of the device’s clock frequency and is connected to the input of the first logic circuit NOT 2, the output of the first logic circuit NOT 2 is connected to the reset input R of the RS trigger 3, the RS output of trigger 3 is the output of the divider with a variable division coefficient.

The output of register 4 is connected to the first input of the code comparator 5, and the output of counter 1 is connected to the second input of the code comparator 5, the output of code comparator 5 is connected to the input of the second logic circuit NOT 6, the output of which is connected to the setup input S of RS-flip-flop 3, RS output trigger 3 is connected to the first input of the OR logic 7, the output of the OR logic 7 is connected to the reset input R of counter 1, the input of register 4 is the data input of the device, the write input of register 4 is connected to the input of the write signal of the device and to the second input of the logic oh OR gate 7, the output of the first NAND gate 2 is connected to the input of the permission code comparator 5.

A frequency divider with a variable division coefficient operates as follows.

At time T0 (Fig. 2), a write pulse records the value of the input data in register 4, which are stored in it until the next record. The data is the conversion factor of the frequency divider, and specifically, the period of the output frequency of the device T in the periods of the clock frequency Ftact:

T = M⋅ (1 / Ftact),

where M is a number written in register 4.

At the same time, the write signal through the OR logic 7 resets the counter 1, the content of which begins to increase with each negative edge of the clock frequency (moments T1 through T2 in Fig. 2). As soon as the contents of counter 1 reaches the value of the contents of register 4 (in our example - 8), the code comparator 5 will work and an impulse will appear at the output “=” of the code comparator 5 from the output of the logic circuit NOT 2 (moment T2), which through the logic RS-flip-flop 3 will cock the circuit NOT 6, which will be reset via the logic circuit NOT 2 of the positive half-wave clock frequency. At the output of the device, an output signal (from T2 to T3) will appear, equal in duration to half the period of the clock frequency. The same signal will reliably reset counter 1 through the OR logic 7. Frequency formation with a period of 8 clock cycles will continue (T4 in Fig. 2) until the contents of register 4 change.

At time T5, a new data value will be written to register 4 (in our example, 3). Counter 1 counted up to 4 (i.e., more than 3) by this time, and if it had not been reset by the write impulse through the OR 7 logic, then the value “3” would appear in it only after the counter 1 overflows and before the count reaches 3 x, which would significantly delay the formation of impulses with a new period. In the proposed device, the formation of pulses with a new period occurs immediately after writing a new data value to register 4 (moments T6, T7, T8 in Fig. 2).

Thus, the introduction of a new node and connections made it possible to ensure the delivery of a given frequency immediately after recording a new value for the conversion factor of the frequency divider.

Claims (1)

A frequency divider with a variable division coefficient, comprising a counter, a register, a code comparator, the first logic circuitry NOT and the second logic circuitry NOT, the counter input is an input to the device clock frequency and connected to the input of the first logic circuitry NOT, the output of the first logic circuitry is NOT connected to the enable input En of the code comparator and reset input R of the RS-flip-flop, the output of the RS-flip-flop is the output of a divider with a variable division coefficient, the register output is connected to the first input of the code comparator, and the counter output is connected to the second input of the code comparator, the output of the code comparator is connected to the input of the second logic circuit NOT, the output of which is connected to the input of the S RS-flip-flop setup, the register data input is the device data input, the register write input is connected to the device recording signal input, characterized in that an OR logic circuit is introduced, while the RS-trigger output is connected to its first input, the second input of the OR logic circuit is connected to the register entry input, and the output of the OR logic circuit is connected to the reset input R of the counter.

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