RU168443U1 - High voltage key device - Google Patents

Abstract

High-voltage key device relates to the field of designing high-voltage power semiconductor switches and modules and can be used in circuits and devices of power electronics of medium and high voltage levels. The device contains a first power terminal [1], a second power terminal [2], a third control terminal [3], (N-1) additional power terminals [4], [5] and [6], a rack [7] of N in series connected keys with field control [8], [9], [10] and [11], a rack [12] of (N-1) fixing diodes [13], [14] and [15], the control n-channel MOS transistor [16]. The drain of the first field switch [8] is connected to the first power terminal [1], the source of the Nth field switch [11] is connected to the drain of the control MOS transistor [16], while the source of the control MOS transistor [16] is connected to the second power output [2], and the gate of the control MOS transistor [16] is connected to the third control terminal [3]. To the gate of each of the (N-1) field keys [8], [9] and [10] in the rack of series-connected keys with field control [7], the anode of the corresponding diode [13], [14] and [15] of the rack [ 12] from (N-1) fixing diodes, while the cathode of the corresponding diode [13], [14] and [15] from the rack (N-1) of fixing diodes [12] is connected to the corresponding additional power terminal [4], [ 5] and [6]. The device is equipped with a stand [17] of (N-1) forcing capacitors connected in series, the first lining of each of (N-1) forcing capacitors [18], [19] and [20] is connected to the gate of the corresponding field key [8], [ 9] and [10] from the rack [7] of serially connected field-controlled keys, the second lining of the (N-1) th forcing capacitor [20] and the gate of the N-th field key [11] connected to the source of the control n- channel MOS transistor [16]. 4 ill.

Description

The utility model relates to the field of designing high-voltage power semiconductor switches and modules and can be used in circuits and devices of power electronics of medium and high voltage levels.

A key device is known in which a field-controlled high-voltage switch is switched by a low-voltage MOS transistor connected in series with it (US Pat. No. 6,633,195 B2, 10/14/2003, IPC H03K 17/687).

The disadvantage of this device is that its output voltage is limited to the maximum voltage of a single high-voltage switch, and these devices cannot be directly used in converters of medium and high voltage levels.

The closest in technical essence to the claimed utility model is a high-voltage key device having a first power terminal, a second power terminal, a third control terminal and (N-1) additional power terminals and containing a rack of N series-connected keys with field control, a rack of ( N-1) of fixing diodes, the control n-channel MOS transistor, interconnected in such a way that the drain of the first field key is connected to the first power output, the source of the N-th field key is connected to the drain of the control MOS transistor, while the source of the MOS transistor is connected to the second power terminal, and the gate of the MOS transistor is connected to the third control terminal, to the gate of each of the (N-1) field keys in the rack of series-connected keys with field control the anode of the corresponding diode from the rack (N-1) of the fixing diodes, while the cathode of the corresponding diode from the rack (N-1) of the fixing diodes is connected to the corresponding additional power output (RF patent 152692 U1, 11.25.2014, IPC - H03K 17/73) .

The disadvantage of this solution is that to discharge the input capacitances of N series-connected keys with field control, an additional rack of (N-1) series-connected diodes is used, which significantly increases the number of semiconductor elements of the device. The second disadvantage of this solution is the incomplete discharge of the input capacitances of N series-connected keys with field control due to the finite forward voltage on the discharge diodes, which impairs the dynamics of the transient switching on of the device and increases the power of switching losses. The third disadvantage of this solution is the lack of the possibility of its use in devices as a key element of the upper level, since in the prototype circuit it is fundamentally impossible to change the direction of connection of the fixing diodes.

The technical task of the proposed device is the expansion of its functionality for use as a key element of both the lower and upper levels.

The technical result of the proposed device is to increase operating efficiency by increasing the switching speed and reducing dynamic and static power losses.

The technical result is achieved by the fact that the known high-voltage key device contains a first power terminal, a second power terminal, a third control terminal and (N-1) additional power terminals and a rack of N field-connected keys with field control, a rack of (N-1) locking diodes, the control n-channel MOS transistor, interconnected so that the drain of the first field key is connected to the first power output, the source of the N-th field key is connected to the drain of the control MOS transistor the current of the MOS transistor is connected to the second power terminal, and the gate of the MOS transistor is connected to the third control terminal, an anode of the corresponding diode from the rack is connected to the gate of each of the (N-1) field keys in the rack of field-connected keys (N -1) fixing diodes, while the cathode of the corresponding diode from the rack (N-1) of the fixing diodes is connected to the corresponding additional power terminal, equipped with a rack of (N-1) series-connected boost condensers Ators, the first plate of each of the (N-1) boost capacitors is connected to the gate of the corresponding field key from the rack of series-connected keys with field control, while the second plate of the (N-1) th boost capacitor and the gate of the N-th field key are connected to source control n-channel MOS transistor.

The essence of the utility model is illustrated by drawings, where in FIG. 1. presents a high-voltage key device, FIG. 2. A diagram is presented with a lower level of connecting a high-voltage key device to the power supply and load circuits.

In FIG. 3. shows a diagram with the upper level connecting the high-voltage key device to the power supply and load circuits.

In FIG. 4. The scheme of a half-bridge with lower and upper levels of connecting a high-voltage key device to the power supply and load circuits is presented.

The high-voltage key device contains a first power terminal 1, a second power terminal 2, a third control terminal 3, (N-1) additional power terminals 4, 5 and 6, a rack 7 of N series-connected keys with field control 8, 9, 10 and 11 , a rack 12 of (N-1) fixing diodes 13, 14 and 15, a control n-channel MOS transistor 16. The drain of the first field key 8 is connected to the first power terminal 1, the source of the Nth field key 11 is connected to the drain of the control MOS transistor 16, while the source of the control MOS transistor 16 is connected to the second power terminal 2, and the gate of the control MOS transistor 16 is connected to the third control terminal 3. To the gate of each of the (N-1) field keys 8, 9 and 10 in the rack of series-connected keys with field control 7, an anode of the corresponding diode 13, 14 is connected and 15 racks 12 of (N-1) fixing diodes, while the cathode of the corresponding diode 13, 14 and 15 of the rack (N-1) of fixing diodes 12 is connected to the corresponding additional power output 4, 5 and 6. The device is equipped with a rack 17 of ( N-1) series-connected boost capacitors, the first about the laying of each of the (N-1) boost capacitors 18, 19 and 20 is connected to the gate of the corresponding field key 8, 9 and 10 from the rack 7 of series-connected keys with field control, while the second lining of the (N-1) th boost capacitor 20 and the gate of the N-th field key 11 is connected to the source of the control n-channel MOS transistor 16.

In FIG. 2, the first power terminal 1 of the device is connected to the load H, and the second power terminal 2 of the device is connected to a common bus. The fixing diodes 13, 14 and 15 in the rack 12 in this circuit are connected to additional power terminals 4, 5 and 6 of the device by cathodes.

Parallel to the power supply E, a rack of N series-connected filter capacitors C1, C2, C3, C _{N is} connected.

The connection points of the filter capacitors C1, C2, C3, C _{N are} connected to (N-1) additional power terminals 4, 5 and 6 of the device.

In FIG. 3, the first power terminal 1 of the device is directly connected to the positive pole of the power source E, and the second power terminal 2 of the device is connected to a grounded load N. The fixing diodes 13, 14 and 15 in the rack 12 are connected to the additional power terminals 4, 5 and 6 of the device by anodes.

Parallel to the power supply E, a rack of N series-connected filter capacitors C1, C2, C3, C _{N is} connected.

The connection points of the filter capacitors C1, C2, C3, C _{N are} connected to (N-1) additional power terminals 4, 5 and 6 of the device.

In the half-bridge circuit, the high-voltage key device of the upper level with the first power output is connected to the positive bus of the power supply E, and the high-voltage key device of the lower level with the second power output 2 is connected to the negative bus of the power supply E. In parallel to the power supply E, a rack of N series connected filter capacitors C1 is connected , C2, C3, C _N.

The connection points of the filter capacitors C1, C2, C3, C _{N are} connected to (N-1) additional power terminals 4, 5 and 6 of the device with both the upper and the lower connection level.

The load N is connected between the connection point of the upper (second power output 2), and the lower (first power output 1) power device and the midpoint of the filter capacitors C1, C2, C3, C _N , which is a common point.

Consider the operation of the inventive device on the example of a circuit with the upper level of connecting a high-voltage key device to the power supply and load circuits (Fig. 3).

The device is an asymmetric key and provides current transmission and power regulation in the load N with a positive potential at the first power terminal 1 (device drain) relative to the second power terminal 2 (device source), i.e. provided

,

,

where U _SI is the output voltage of the drain-source device between the power terminals of the device 1 and 2.

The locked state of the device is realized when the control signal is zero at the third control terminal 3 connected to the gate of the control MOS transistor 16.

Denote the external voltage applied to the inventive device and connected in series with the load H, the symbol E. When the device is closed:

,

,

where U _DS8 , U _DS9 , U _DS10 , U _DS11 is the drain-source voltage at the corresponding field switches 8, 9, 10, 11 in rack 7;

U _DS16 - drain-source voltage at the control MOS transistor 16.

The voltage values of U _DS8 , U _DS9 , U _DS10 , U _DS11 , U _DS16 on the key elements of a closed device will be determined below.

The device is turned on by applying a positive voltage pulse to the third control terminal 3. In this case, the input capacitance of the control MOS transistor 16 is charged, which ensures its inclusion.

Through the channel of the open control MOS transistor 16, the input capacitance of the field key 11 is discharged. When the voltage at the input capacitance of the field key 11 decreases to the cut-off voltage V ₀ , it is unlocked.

Further, through the channel of the open control MOS transistor 16, the channel of the open field key 11 and the boost capacitor 20, the input capacitance of the field key 10 is discharged. When the voltage at the input capacitance of the field key 10 decreases to the cutoff voltage V ₀ , it is unlocked. And so on for all other field keys 9 and 8 in rack 7.

Since the boost capacitors 18, 19 and 20 in the rack 17 are pre-charged to the initial voltage E / N, they provide forced recharging of the input capacitance of the corresponding transistors 8, 9 and 10. In turn, this increases the switching speed of the device and reduces the power of dynamic losses. After the input capacitors of the transistors 8, 9, and 10 are discharged, the residual charge from the boost capacitors 18, 19, and 20 also enters the drift region of the transistors 8, 9, and 10, which provides additional modulation of the resistance of the drift region and a decrease in static power losses.

At the end of the transient switching process, a direct voltage will be established on the device:

,

,

where U _{(on) 8} , U _{(on) 9} , U _{(on) 10} , U _{(on) 11} is the voltage drop across the open field switches 8, 9, 10, 11;

R _{DS (on) 16} - resistance of the open channel drain-source control MOS transistor 16;

I _C - drain current of the power device in the open state, equal to the load current.

The device is turned off by switching the voltage at the control terminal 3 to zero. When this occurs, the input capacitance of the control MOS transistor 16 is discharged, after which this transistor 16 is locked.

The drain potentials of field keys 10 and 9 at the same time begin to grow, with the exception of the drain potential of key 8, which is fixed at the level of power source E. Since the initial voltages at the boost capacitors 18, 19, 20 are zero before turning off the device, the gate-source field keys in the rack 7 negative voltages are formed. The negative voltage of the uppermost switch 8 in the rack 7 increases most rapidly. When this voltage is increased to the cut-off voltage V ₀ , the field switch 8 is locked, and a powerful reverse current pulse is generated in its gate circuit, the magnitude of which is proportional to the load current.

In practice, most often the device operates on an active-inductive load in continuous current mode. Since the field switch 8 is locked, the load current begins to flow through the boost capacitor 18, ensuring its charge is almost linear in law. The load current is always larger in magnitude than the amplitude of the reverse current pulse arising in the gate circuit of the field key 8. At the same time, the diode 13 will be in the open state for the charging time of the boost capacitor 18, ensuring that the gate potential of the field key 8 is fixed at (N-1 ) E / N, thereby fixing the output voltage of key 8 at the level of:

.

.

According to a similar mechanism, all other field-controlled keys 9, 10 and 11 are sequentially locked in a rack 7. After locking the last field key 11, the device goes into a locked state. In this case, the total voltage of the external source E, evenly distributed between N field keys 8, 9, 10, 11 in rack 7 at the E / N level, is applied to the output source-source circuit of the device.

The drain potential of the closed MOS transistor 16 when the device is locked is maximized to the cut-off voltage level V _{0 of the} field switch 11, while the output voltage on the closed MOS transistor 16 is set equal to:

.

.

A condition for the operability of the device is the requirement that the charging time of the boosting capacitors 18, 19 and 20 in the rack 17 by the load current In to voltage E / N be longer than the time Δt of the reverse current pulse flowing in the gate circuit of the corresponding field switches 8, 9 and 10 in the rack 7. This condition is ensured by the selection of the corresponding capacitance value C ₀ forcing capacitors 18, 19 and 20 in the rack 17:

Examples of specific performance of the proposed device.

In FIG. 2 shows a circuit with a lower level of connecting a high-voltage key device to the power supply circuit E and load N. In this scheme, the power output 1 of the device is connected to the load H, and the second power output 2 of the device is connected to a common bus. The fixing diodes 13, 14 and 15 in the rack 12 in the lower key circuit are connected to additional power terminals 4, 5 and 6 of the device by cathodes. When the source of the device is grounded (power terminal 2), this connection of the fixing diodes ensures the fixation of the positive potentials of the field-controlled key gates in the rack 7, relative to the negative bus of the power supply E.

In FIG. Figure 3 shows the circuit with the upper level connecting the high-voltage key device to the power supply circuit E and load N. In this circuit, the first power output 1 of the device is directly connected to the positive bus of the power supply E, and the second power output 2 of the device is connected to the grounded load N. With a fixed the potential of the first power output of the device, the fixing diodes are connected to additional power terminals 4, 5 and 6 of the device by the anodes, since such a connection ensures the fixation of negative potential catching gate closures with field control in rack 7, relative to the positive bus of power source E.

In FIG. 4. A half-bridge is presented, containing two high-voltage key devices: one at the bottom and the other at the top level of connection to the power supply and load circuits. This connection ensures the operation of the circuit with alternating current in load N.

The use of the invention provides enhanced functionality for the use of a high-voltage device as a key element of the lower and upper connection level, and also increases the efficiency of the device by increasing the switching speed and reducing dynamic and static power losses of its key elements.

Claims (1)

A high-voltage key device containing a first power terminal, a second power terminal, a third control terminal and (N-1) additional power terminals, a rack of N field-connected keys in series, a rack of (N-1) fixing diodes, an n-channel control MOS transistors interconnected in such a way that the drain of the first field key is connected to the first power terminal, the source of the Nth field key is connected to the drain of the control MOS transistor, while the source of the control MOS transistor is connected to the second power output, and the gate of the control MOS transistor is connected to the third control terminal, the anode of the corresponding diode from the rack (N-1) of the fixing diodes is attached to the gate of each of the (N-1) field keys in the rack of series-connected keys with field control, when this cathode of the corresponding diode from the rack (N-1) of the fixing diodes is connected to the corresponding additional power output, characterized in that it is equipped with a rack of (N-1) series-connected boost capacitors, the first lining of each about from (N-1) forcing capacitors is connected to the gate of the corresponding field key from the rack of series-connected keys with field control, while the second cover of the (N-1) -th forcing capacitor and the gate of the N-th field key are connected to the source of the control n- channel MOS transistor.

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