RU165467U1 - SILICON STRUCTURE WITH DIELECTRIC INSULATION - Google Patents

Abstract

A silicon structure with dielectric insulation, consisting of silicon "pockets" surrounded by a layer of silicon oxide and polysilicon, a plane-parallel polished silicon substrate attached to polysilicon with a glass frit layer, characterized in that the outer side of the silicon substrate is processed to a roughness of not more than R = 0, 12 microns.

Description

The scope of the utility model is the production of semiconductor devices and integrated circuits, namely the production of silicon structures with dielectric insulation (KSDI).

Known silicon structure with dielectric insulation, consisting of silicon "pockets" surrounded by a layer of silicon oxide and a polysilicon substrate (see, for example, RF patent No. 1116919, class H01L 21/76, 04/15/1994, Bryukhno N.A. ., Zharkovsky EM et al., Silicon structures with dielectric insulation for microelectronics products. Review of electronic technology. Ser. 3. Microelectronics, 1987)

The main disadvantage of this structure is that during high-temperature (more than 1000 ° C) heat treatments when building a polysilicon substrate (300-600 μm), as well as high-temperature heat treatments associated with the formation of microcircuit elements, the polysilicon grains recrystallize and due to the decrease in the volume of the polysilicon substrate leads to a curvature of the entire silicon structure, which complicates further processing and reduces the yield of products, especially when using structures of large diameter (100 mm or more).

This drawback is eliminated in the closest to the claimed silicon structure with dielectric insulation, consisting of silicon "pockets" surrounded by a layer of silicon oxide and polysilicon, a plane-parallel polished silicon substrate attached to polysilicon with a glass frit layer described in RF patent No. 2018194, class H01L 21 / 76, dated August 15, 1994

In such a silicon structure with dielectric insulation, to prevent deformation, a thin layer of polysilicon is used, usually 40-100 μm, depending on the depth of the insulating grooves, and a plane-parallel silicon single crystal orientation plate (111) with two-sided mechanical grinding and subsequent etching of the broken layer. Bilateral mechanical grinding of the wafer is necessary in order to guarantee high adhesion strength of the glass frit to the substrate and the parallelism of the sides of the entire silicon structure with dielectric insulation.

However, the presence on the reverse side of a silicon structure with dielectric insulation on the polished side of the substrate often leads to the accumulation of heavy metal impurities on the open surface of the substrate, in particular, iron and copper. Using such plates in high-temperature processes, impurities from the open surface of the substrate can fall into the working direction, namely, into silicon insulated “pockets”. Because the thickness of the isolated "pockets" is usually small (10-50 microns), the concentration of heavy metal impurities in the isolated "pockets" can be significant, which leads to a deterioration in the characteristics of the formed semiconductor structures, in particular transistors.

The technical result of this utility model is the improvement of reproducibility and hanging the yield of suitable products when using silicon structures with dielectric insulation by reducing the level of "pollution" by impurities of heavy metals.

The specified technical result is achieved in that, in contrast to the known silicon structures with dielectric insulation, consisting of silicon "pockets" surrounded by a layer of silicon oxide and polysilicon, a plane-parallel polished support plate attached to polysilicon by a glass frit layer, in the proposed outer side of the substrate is processed to roughness of not more than R _z = 0.12 μm.

New in the proposed utility model is that the outer side of the silicon substrate is processed to a roughness of not more than R _z = 0.12 μm. At such roughness values, the level of contamination with heavy metal impurities is significantly reduced due to a decrease in the total surface area that absorbs heavy metal impurities.

The roughness value is selected from the following considerations: an increase in roughness leads to an increase in the accumulation of contaminants by impurities of heavy metals, and a decrease in roughness complicates the processing of plates and does not significantly improve the effect of absorption of impurities of heavy metals.

The essence of the proposed utility model is illustrated by figures. In FIG. Figure 1 shows the blank of the CDI for the operation "Polishing the outer side of the silicon substrate", in FIG. 2 shows the finished CSID; FIG. Figure 3 shows a comparative diagram of the concentrations of heavy metal impurities - iron and copper in ready-made KSDI.

The positions in figures 1-2 are indicated:

1 - source plate;

2 - base plate;

3 - V-shaped grooves;

4 - n ⁺ layer;

5 - a layer of silicon oxide;

6 - layer of polycrystalline silicon;

7 - junction area;

8 - polished outer side of the silicon substrate;

9 - silicon "pockets" insulated by a dielectric, in which elements of microcircuits are formed.

The following describes the main stages of the manufacture of the proposed silicon structure with dielectric insulation.

For the fabrication of DDS, we used the initial plates of 1 single-crystal n-type silicon with a resistivity of 4 Ohm · cm, diameter 100 mm, orientation (100), and a thickness of 500 μm; as the supporting plate 2, plates of single-crystal silicon EKES-0.01 orientation (111) with a diameter of 100 mm and a thickness of 500 microns.

The initial plates were subjected to double-sided chemical-mechanical polishing, and the support plates were subjected to plane-parallel double-sided grinding with free abrasive and alkaline etching. On the initial plate 1 (by anisotropic etching through a mask of SiO ₂ , V-grooves 3 were etched with a depth of 37 ± 2 μm. Arsenic was diffused into the relief surface at a temperature of 1200 ° C to obtain an n ⁺ layer 4 with a depth of 6.0 ± 0 , 5 microns, thermal and pyrolytic oxidation to a thickness of a silicon oxide 5 layer of 2.5-4.5 microns, and deposition of a polycrystalline silicon 6 layer with a thickness of 70 ± 10 microns at a temperature of 1200 ° C using a UNES-101M installation using chemical reduction method SiCl ₄ in hydrogen The resulting structure was subjected grinding with a bonded abrasive to a depth of 20 μm and etching in KOH. Then, a layer of glass frit powder matched by thermal expansion coefficient with silicon was applied to the resulting structure and the hot support plate by suspension, after which the support plate and the relief structure were connected to each other so so that the precipitated glass was between them, clamped in a clamp with a spring dynamometer and subjected to heat treatment in a diffusion furnace in a stream of nitrogen at constant pressure. At a sintering temperature of 1200 ° C and a time of 60 min. the junction area 7 is formed. After bonding, the outer side of the silicon substrate 8 is polished to a roughness of not more than R _z = 0.12 μm with AFM-0.5 diamond paste. Next, the brazed plates were subjected to standard technological operations to obtain silicon structures with dielectric insulation with insulated silicon "pockets" 9 (Fig. 2).

In FIG. 3 shows the survey data by the mass spectroscopic method of concentrations of heavy metal impurities - iron and copper in silicon structures with dielectric insulation, made according to the prototype and the claimed. Impurities of heavy metals - iron and copper - reduce the lifetime of charge carriers and increase leakage currents. The proposed silicon structure with dielectric insulation helps to reduce the level of contamination with heavy metal impurities by treating the surface of the outer side of the silicon substrate to a roughness of not more than R _z = 0.12 μm, therefore, the total surface area that absorbs heavy metal impurities is reduced.

Analysis of figure 3 shows that the use of the inventive silicon structure with dielectric insulation can reduce the level of contamination with impurities of heavy metals and increase the yield of products when using silicon structures with dielectric insulation.

Claims (1)

A silicon structure with dielectric insulation, consisting of silicon "pockets" surrounded by a layer of silicon oxide and polysilicon, a plane-parallel polished silicon substrate attached to polysilicon with a glass frit layer, characterized in that the outer side of the silicon substrate is processed to a roughness of not more than R _z = 0 , 12 microns.

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