RU151822U1 - SYNCHRONOUS MULTI-CHANNEL SYNCHRONIC DATA COLLECTION DEVICE - Google Patents

Abstract

A synchronous switch of a device for multi-channel synchronous data collection, obtained over a standard Ethernet network through data units (BDS) with analog-to-digital ADC converters, characterized by the presence of a standard Ethernet switch, a multi-channel device for generating a set of sequences of clock signals with width-coded pulses (SCI), to which it is connected a power supply device, wherein said multi-channel device for generating a set of sequences of clock signals includes a clock a herator that sets the main frequency of clock pulses to ensure the operation of all ADCs in each BSD, a divider counter designed to generate ADC sampling pulses, a divider counter designed to generate pulses corresponding to the moment of the formation of the next packet of a given number of ADC readings, a counter of the current packet number data and a generating circuit designed to generate a combined synchronization sequence of pulse-width encoded pulses (SQI), the mentioned clock the converter, counters-dividers, and the counter of the current number of the data packet are connected to the input of the shaping circuit, the output of the shaping circuit is connected to the inputs of the SCI converters into differential signals, ensuring the transmission of the SCI through matching transformers to the corresponding BSD.

Description

The utility model relates to information-measuring equipment and can be used in distributed multichannel systems for synchronous data collection from receiving elements of multichannel hydroacoustic antenna arrays, long multi-element seismic exploration antennas, distributed vibration and tension sensors in complex structures, test equipment, etc. p., providing the ability to build a distributed system for synchronous data collection using standard Ethernet network protocols, in which the nodes of the system are spaced up to 160 meters away and connected to the proposed synchronous switch with only a standard network cable (for example, “UTP Category 5” consisting of four twisted pairs of wires).

In addition, the proposed utility model allows the construction of a multi-channel acquisition system, which implements the possibility of arbitrary switching and the sequence of data packets transmission over the Ethernet network, ensuring further restoration of the synchronism (coherence) of data from different receiving elements at any stage of their further processing.

State of the art

A device is known having two synchronization lines (US patent 7792139, IPC H04L 12/66), containing several analog-to-digital conversion modules connected in series with each other by a twisted-pair cable. Each analog-to-digital conversion module consists of an analog-to-digital conversion unit, a digital signal processing unit, an interface controller, an Ethernet bus controller, a PLL synchronization recovery unit from clock signals coming from a separate twisted pair cable and a measurement (sampling) signal decoding unit, also arriving at the device via a separate twisted pair cable, however, even in this case the task of synchronizing data packets transmitted over the Ethernet network is not solved, but with an arbitrary order of inclusion I BDS also occurs a complete loss of mutual synchronization of data transmitted over the Ethernet network between individual BDS.

The closest in technical essence and technical result achieved with respect to the described utility model is a device (RF patent No. 2485582) containing data acquisition units (BSD), a concentrator, a storage device and a PC connected by a star topology with information interface lines .

The data acquisition units consist of an analog-to-digital conversion unit based on analog filters and ADC chips, a digital signal processing unit, a control unit based on microcontrollers and / or programmable logic chips (FPGAs), a bus occupancy monitoring unit, a bus controller, made on the basis of a microcontroller and / or programmable logic chip (FPGA), a synchronization unit, which can be performed on the basis of counters and microchips of generators with a programmable output frequency, task memory made on the basis of flash memory chips.

This device is the closest in technical essence to the proposed utility model and is taken as a prototype.

The disadvantage of this device is the presence of a separate line for transmitting only a simple clock signal, which only starts the internal clocks of the BSD, without providing the presence of other clocks, in particular, signals ensuring the synchronization of the sampling times (sampling) of the ADCs located in different BSDs of the clock signal corresponding to the simultaneous the moment of the beginning of the formation of data packets for transmission over the Ethernet network, and synchronous information about a single current number of data packets generated in different BSDs, providing The possibility of guaranteed further mutual binding of data packets received from different BSDs in the process of their communication and joint, including coherent processing. In the case of a non-simultaneous moment of switching on different BSDs or in the case when individual BSDs during operation can turn off or turn on at arbitrary points in time, and with a large number of BSDs this is very likely, a complete loss of mutual synchronization occurs in the prototype. In addition, to ensure synchronization, in addition to the Ethernet cable, the introduction of an additional synchronization line (cable) is required, which greatly complicates the installation and operation of the system.

The objective of the utility model is to create a device for multichannel synchronous data collection that implements strict synchronization of the work and moments of data sampling for a set of analog-to-digital converters (ADCs) located in different BDSs, synchronously generates time-ordered packets of ADC samples with a single synchronous numbering of data packets transmitted over the Ethernet network, formed in the diversity of the BSD.

The developed device provides the organization of tight time synchronization of samples of signals transmitted over the Ethernet network from terminal devices; a multi-channel device for generating a set of sequences of pulse-width encoded clock signals transmitted over one twisted pair of conductors of a standard Ethernet cable is introduced into the Ethernet switch. The set of clock sequences includes:

the main clock frequency (OTF) of the ADC, including for the sigma-delta

ADCs operating in resampling modes;

signal of the sampling moment (sampling period) of the ADC;

a signal of the moment of formation of the next data packet;

signals of synchronous code information, including a single simultaneous sequential numbering of generated data packets and other code information, which is simultaneously included in all generated Ethernet data packets in different BSDs.

A sequence of clock signals with pulse-width coding is transmitted to terminal devices (nodes, BSD) via one free pair of wires of a standard cable used to connect these devices via FastEthernet (100BASE-TX). The second free pair of standard cable transfers power to terminal devices (BSD), including standard Power over Ethernet (PoE), a technology that allows electric power to be transmitted to a remote device with data through a standard twisted pair cable over Ethernet (IEEE 882.3 standard af).

The technical result of using the utility model is to increase the reliability of the device by providing tight synchronization of arbitrarily connected devices and data streams over the network.

An important advantage of the utility model is also the ability to connect (disconnect) the DSS in random order directly during operation while maintaining end-to-end synchronization, which also ensures the reliability of the device.

The developed device also provides a simplification and a significant reduction in cable communications, lower manufacturing costs, as well as the possibility of further communication of data packets, including their arbitrary processing and storage time, without additional transformations and binding to a single point in time.

The problem is solved, and the technical result is achieved due to the fact that the device, characterized by the presence of data acquisition units (BSD), additionally includes a synchronous switch interconnected by standard Ethernet cables, a synchronous switch connected via a standard Ethernet network to the necessary computing means for processing and storing data. The synchronous switch includes a standard Ethernet switch, with the required number of ports, and a multi-channel device for generating a set of clock sequences with pulse-width coding, as well as a power supply device that provides power to all BSDs.

The multi-channel device for generating a set of pulse width coding clock sequences includes a clock connected to a generating circuit. The clock generator sets the main frequency of the OTF clock pulses to ensure the operation of all ADCs in each BSD. The device includes a counter-divider designed to generate ADC sampling pulses, a counter-divider designed to generate pulses corresponding to the moment of the beginning of the formation of the next packet of a given number of ADC samples combined in one packet for transmission over the Ethernet network, a counter of the current data packet number and circuit formation, intended for the formation of the integrated synchronization sequence of pulse-width encoded pulses (SQI). The mentioned counter-dividers and the counter of the current number of the data packet are connected to the input of the formation circuit, the output of the formation circuit is connected to the inputs of the SCI converters into differential signals for transmission of the SCI through matching transformers via a free twisted pair of wires of each Ethernet cable of the synchronous switch to the corresponding BSD.

Each BSD data acquisition unit consists of ADCs made on the basis of analog filters and ADC microchips, a power converter, as well as a digital processing unit and Ethernet data packets and a decoding unit for pulse-width synchronized synchronization signals based on microcontrollers and / or programmable microcircuits logic (FPGA).

Synchronous data acquisition device, as shown in fig. 1, consists of many data acquisition blocks (BSS) 1, to which analog signals (data) are received from the receiving elements, and a synchronous switch 2, interconnected only by standard Ethernet connectors and cables (for example, “UTP category 5” consisting of four twisted pairs of wires). For further data processing, the synchronous switch 2 is connected via a standard Ethernet network to the necessary computing means for processing and storing data.

In addition to the standard Ethernet switch 3, the structure of synchronous switch 2, with the required number of ports (not less than the number of connected BSDs and ports for data output to computing means for further processing and registration), introduces a multi-channel device for generating a set of sequences of clock signals with width-coded pulses 4, as well as a power supply device 5, providing power to all BSD (1) connected to the system.

The multi-channel device for generating a set of sequences of clock signals with pulse-width encoding 4, in turn, as shown in Fig. 2, consists of a clock generator 7 connected to the formation circuit 11 and setting the main frequency of the clock pulses to ensure the operation of all analog-to-digital converters ( ADC) 6, counter-divider 8, designed to generate ADC sampling pulses corresponding to the necessary moment of the beginning of the next measurement cycle (receiving the next ADC readout), Chick-divider 9, designed to generate pulses corresponding to the moment of the beginning of the formation of the next packet of a given number of ADC samples, combined in one packet for Ethernet transmission, the counter of the current data packet number 10. Generation circuit 11 is designed to generate a combined synchronizing sequence of width-coded pulses (SCI).

The counter-divider 8, the counter-divider 9 and the counter of the current number of the data packet 10 are connected to the inputs of the forming circuit 11, the output of the forming circuit 11 is connected to the inputs of the SCI converters into differential signals 12 for transmitting the SCI through matching transformers 13 via a free twisted pair of wires of each cable Ethernet synchronous switch 2 to the corresponding BSD 1.

Each BSD 1 data acquisition unit (Fig. 1) consists of ADC 6 based on analog filters and ADC microchips, a power converter 14, and a digital processing unit and Ethernet data packets 15 and a decoding device for pulse-width synchronized pulse signals 16 made on the basis of microcontrollers and / or chip programmable logic (FPGA).

The decoder for the width-coded pulse (SHKI) synchronization signals 16 extracts from the SHKI the ADC clock synchronization signal supplied to all ADCs 6, and also selects from the SHKI information about the moment of the formation of the next data packet and the code of its current number, and transmits them to the digital device processing and forming Ethernet data packets 15, the input of which also receives data from the ADC 6. The power converter 14 is connected to all devices included in the BSD (1) and provides conversion of the pit voltage Ia supplied from the power unit 5 constituting the synchronous switch 2 in the range of voltages required for operation of the devices.

A synchronous data acquisition device operates as follows.

After external power is supplied to the power supply device 5 of the synchronous switch 2, it generates the necessary set of supply voltages for the operation of its devices 3 and 5, and also through the Ethernet cable supplies power to the power sources 14 of each of the BSD 1 which, in turn, form the necessary set of voltages power supply for operation of all devices included in the BSD (6, 15, 16). The clock generator 7 of the device for generating a set of sequences of clock signals with pulse-width encoding 4 generates the main frequency of the clock pulses with a duty cycle of 4, which are supplied to the shaper 11 and connected in series: a counter-divider 8, which generates pulses corresponding to the required moment of the start of the next ADC measurement cycle, counter-divider 9 which generates pulses corresponding to the moment of the beginning of the formation of the next packet of a given number of ADC samples, combining mn in one packet for transmission over the Ethernet network, and a counter of the current number of the data packet 10, forming the code of the packet number. Pulses of double duration, in comparison with the pulses of the clock generator 7, formed by the counter-dividers 8 and 9 are supplied to the former 11, where they are combined with the clock pulses of the generator 7. The pulses of the beginning of the formation of the next data packet, formed by the counter-divider 9, are used as the starting pulses during the formation the next data packet number. The code of the current number from counter 10 is sent to the And generator, where it is converted into a code sequence of pulses with unit bit durations (signal "1") of equal double duration, compared to clock pulses 7 and zero bit designations (signal "0") corresponding to the pulse width of the clock 7.

The timing diagrams generated by the signal conditioning apparatus 4 are shown in Fig. 3.

Diagram I (Fig. 3) shows the enlarged general synchro sequence of the ShKI. The synchronization sequence uses two types of pulses: with a duty cycle equal to four and with a duty cycle equal to two. Pulses with a duty cycle of 4 are used as pulses with an operating frequency of the ADC and as a designation of zero bits when reading an information package. Pulses with duty cycle 2 are used as markers for the start of measurements (shown in Diagram 2), the beginning of a data packet and information sequence (shown in Diagram 3), and as designations of single bits (signal “1” is shown in Diagram 3) when reading code information about the current number data packet.

The information sequence begins with an impulse with a duty cycle of 2 and can be of two types. If a pulse with duty cycle 2 is followed by pulses with duty cycle 4 (diagram II), then this sequence should be perceived only as a command to start the next measurement cycle (signal to start sampling or sampling of the ADC). If an impulse with duty cycle 2 is followed by two more pulses with duty cycle 2 (diagram III), then such a sequence of pulses should also be perceived as the beginning of the next packet of samples generated for the Ethernet network. Following three pulses with a duty cycle of 2 are followed by a sequence of pulses “1” and “0”, corresponding, for example, to a 16-bit code of the current packet number for the Ethernet network.

The generated signal through the converters 12 and transformers 13 is supplied to all connected BSDs 1. The decoding device for the pulse-width pulse-encoded (SHKI) synchronization signals 16 extracts the ADC clock synchronization signal from the SHKI, which is supplied to all ADCs 6, and also extracts information about the start moment from the SHKI the formation of the next data packet and the code of its current number, and transmits them to the digital processing device and the formation of Ethernet data packets 15, the input of which also receives data from the ADC 6.

The main clock signal is used as a clock signal for the operation of the sigma-delta (serial) ADC installed in the BSD 1. Conversion triggering pulses are used to start generating the next sample in the sigma-delta ADC and as a clock signal for parallel ADCs. Data generated in the ADC 6 Pulses of the packet number are used as the start when forming the next data packet for transmission over the Ethernet network. The data generated in the ADC 6 and the current packet number code is included in the UDP / IP packets in the digital processing and Ethernet data packet generation device 15. The Ethernet data packets are formed and all the DSSs are sent to switch 3 of synchronous switch 2, from where they are transferred to external computing means for further processing and registration.

The proposed architecture of the data acquisition device allows connecting, disconnecting and replacing terminal modules without additional reconfiguration of the system as a whole. If one or more terminal devices fails, serviceable devices continue to transmit digital signals. The introduction of a synchronization device with a ShKI allows for rigid group phase and packet synchronization in a multichannel distributed data acquisition system using only standard cables designed for data transmission via Ethernet. The use of standard cables, the principles of generating differential ShKI differential signals identical to signals intended for data transmission over an Ethernet network, makes it possible to separate individual BSDs 1 over a distance of more than 100 meters from synchronous switch 2.

Claims (1)

A synchronous switch of a device for multi-channel synchronous data collection, obtained over a standard Ethernet network through data units (BDS) with analog-to-digital ADC converters, characterized by the presence of a standard Ethernet switch, a multi-channel device for generating a set of sequences of clock signals with width-coded pulses (SCI), to which it is connected a power supply device, wherein said multi-channel device for generating a set of sequences of clock signals includes a clock a herator that sets the main frequency of clock pulses to ensure the operation of all ADCs in each BSD, a divider counter designed to generate ADC sampling pulses, a divider counter designed to generate pulses corresponding to the moment of the formation of the next packet of a given number of ADC readings, a counter of the current packet number data and a generating circuit designed to generate a combined synchronization sequence of pulse-width encoded pulses (SQI), the mentioned clock the converter, counters-dividers, and the counter of the current number of the data packet are connected to the input of the shaping circuit, the output of the shaping circuit is connected to the inputs of the SCI converters into differential signals, ensuring the transmission of the SCI through matching transformers to the corresponding BSD.

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