RU127957U1 - CONTROL DEVICE FOR INTERFERENCE-PROTECTED RADIO TECHNICAL SYSTEM - Google Patents

Abstract

A control device for an anti-interference radio engineering system comprising a central processing unit (CPU), a first read-only memory (ROM), a first random access memory (RAM), an input port (PV), an output port (PV), a first control bus (SHU), a first a data bus (SH), a first address bus (SH), the first group of inputs and outputs of the CPU through the first SH being connected to the group of outputs of the first ROM, with the group of inputs and outputs of the first RAM, with the group of outputs of the PV, with the first group of inputs of the PV; the group of information outputs of the CPU through the first address bus (SHA) is connected to the group of inputs of the first ROM, with the group of inputs of the first RAM, with the first group of inputs of the PV, with the second group of inputs of the PV; the second group of PV inputs is connected to the group of outputs of the UO, the group of outputs of the PVs is connected to the second group of inputs of the managed object (UO), characterized in that the first input-output address decoder (SAI), serial asynchronous input-output module (MPAVV), module are introduced formation of a unipolar control code (MF UKU), a control module for the control signal driver (MU FKS); the group of control inputs of the first DAVA through the first control unit is connected to the group of control outputs of the CPU, the group of information inputs of the first DAVA through the first ШA is connected to the group of information outputs of the CPU, and the outputs of the first DAVA are connected to the control inputs of the first ROM, first RAM, PV, PV , MF UKU and MU FKS, with the first group of inputs and outputs MPAVVY connected to the second group of inputs and outputs of the CPU, the second group of inputs and outputs MPAVVy connected to the first group of inputs and outputs of the UO,

Description

The inventive utility model relates to the field of automated control of radio engineering objects and can find application in radio engineering devices operating in difficult interference conditions.

Currently, the problem of ensuring the reliable functioning of radio systems (PC) in the aspect of the implementation of control functions is of great importance. This is due to the fact that modern complexes have turned into complex systems, in the vast majority of cases, with the chaotic dynamics of the implementation of their target functions. At the same time, functioning in the general environment of reception and transmission, the presence of significantly affecting the effectiveness of potentially dangerous code or analog sequences and the unpredictable change in the volume and nature of the information received leads to regular transitions to the conflict mode of operation of both individual elements and the entire system. In this case, the information management system (SU), based on the processing of digital streams, is of particular importance. According to modern concepts [1-5], the head of the entire radio system should traditionally have one central link (or device) that will make final decisions on major issues. This leads to the need to develop new control devices that can effectively implement their target functions.

Before describing the claimed utility model and its prototypes, it is necessary to give the following explanations.

A computing complex refers to several computing systems that are informationally interconnected (usually via a serial channel) [5, p. 18]. A system bus is a group of trunk lines that includes groups called an address bus, a data bus, and a control bus [5, p.26]. The term "common address space" is used to denote the set of addresses used in processor instructions for organizing intra-machine information exchanges [5, p.26]. The term "interface" (Interface - conjugation) is used to denote the combination of hardware, software and design tools used to implement the informational interaction of functional blocks in computers. The term “interface” is used for all devices of computers: processor, system bus, RAM, peripheral devices [5, p. 28].

Digital automation and control systems are known, described in [1], where the general provisions on the choice of the control system structure and the general rules for constructing real-time systems are defined, according to which the control system is a complex structure that provides control of individual components by organizing interaction between them through transmission data based on common interfaces and control information exchange protocols. According to [1], in most systems, several hierarchical or administrative levels can be distinguished that correspond to decisions that must be made in the management process, which as a result leads to the modular principle of constructing control systems for complex objects.

SUs are known, described in [2], where the process of controlling dynamic objects under initial uncertainty and changing working conditions when interacting with the external environment is considered. Systems operating in such conditions are called adaptive control systems. The principle of operation of adaptive control systems is to change the parameters and structure of the system based on processing a priori and current information, which as a result leads to an improvement in the dynamics of functioning processes.

The disadvantage of the systems [1] and [2] is the insufficient study of the practical details necessary for the operation of the device in a complex jamming environment and the random change in the volume and nature of the information received, as well as low quality control indicators for non-linear and complex systems (systems consisting of a large number of blocks (over 100)).

The closest in technical essence to the claimed utility model is the device described in [4, p. 108], taken as a prototype.

The structural and functional diagram of the prototype device is presented in figure 1, where the following notation.

2 - central processing unit (CPU);

4 - read-only memory (ROM);

5 - random access memory (RAM);

6 - input port (PV);

7 - output port (PVy);

8 - control bus (ШУ);

9 - data bus (BD);

10 - address bus (ША);

11 - system bus (SS);

30 - managed object (UO).

The prototype device comprises a central processor 2, read-only memory 4, random access memory 5, input port 6, output port 7. Moreover, the group of control outputs of the central processor 2 is connected via control bus 8 to the control input of read-only memory 4, with a control input random access memory 5, with the control input of the input port 6 and with the control input of the output port 7. The group of inputs and outputs of the central processor 2 via the data bus 9 is connected to Uppa of the outputs of read-only memory 4, with a group of inputs / outputs of random access memory 5, with a group of outputs of an input port 6 and with a first group of inputs of an output port 7. A group of information outputs of a central processor 2 is connected via an address bus 10 to a group of inputs of a read-only memory 4 , with a group of inputs of random access memory 5, with a first group of inputs of an input port 6, with a second group of inputs of an output port 7. A control bus 8, a data bus 9, and an address bus 10 form a system tire 11.

In addition, the second group of inputs of input port 6 is connected to the group of outputs of the managed object 30, and the group of outputs of output port 7 is connected to the group of inputs of the managed object 30.

The structural and functional diagram of the input port 6, described in [4, p.125], is presented in figure 2, where the following notation:

6.1 - input address decoder (DAV);

6.2 - bus driver (BF).

Input port 6 contains a sequentially connected decoder of input address 6.1, the control input of which is the control input of the input port 6 unit, and the input group is the first group of inputs of the input port 6 unit, and the bus driver 6.2, the output group of which is the output group of the input port 6, and the group of inputs is the second group of inputs of input port 6. The output of the decoder of the input address 6.1 is connected to the input of the bus driver 6.2.

The structural and functional diagram of output port 7, described in [4, p.124], is presented in figure 3, where the following notation:

7.1 - output address decoder (DAO);

7.2 - output register (RV).

Output port 7 contains sequentially connected output address decoder 7.1, the control input of which is the control input of output port block 7, and the input group is the second group of inputs of output port block 7, and output register 7.2, the input group of which is the first group of inputs of output port 7, and the group of outputs is the group of outputs of output port 7. The output of the decoder of output address 7.1 is connected to the input of output register 7.2.

The central processor 2 is designed to control any objects. Permanent storage device 4 is designed to store permanent data, which may be constant coefficients and / or program memory. Random access memory 5 is designed to store data transmitted and / or received from the central processor 2, which change during program execution. The system bus 11 is intended for the exchange of information between the Central processor 2 and the remaining units located in the system. Parallel input ports 6 and output 7 are designed for data exchange between the managed object 30 and the central processor 2. Also, the input port 6 and the output port 7 perform the function of matching the speed of the managed object 30 with the speed of the system bus 11.

The enlarged algorithm of the prototype is as follows. When turned on, the central processor 2 initializes all the units that make up the system, setting them to the initial states necessary for the given operating conditions. Next, the algorithm of work embodied in the software of the central processor 2 is executed. If it is necessary to receive data from the managed object 30, the central processor 2 sets the signals for reading data to the control bus 8 and the address bus 10, and then executes a data read command. The input address decoder 6.1 receives data from the control bus 8 and the address bus 10 and transmits a data read enable signal to the bus driver 6.2. Data from the managed object 30 through the bus driver 6.2 is fed to the data bus 9, and then to the central processor 2. If it is necessary to send data to the managed object 30, the central processor 2 sets the signals for writing data to the control bus 8 and address bus 10 , and then executes a data write command. Output address decoder 7.1 receives data from control bus 8 and address bus 10 and transmits a data write enable signal to output register 7.2. Data from the central processor 2 through the data bus 9 is fed to the output register 7.2, and then to the managed object 30.

The disadvantage of the prototype device is the limited functionality, which consists in the absence of additional units for working with peripheral devices, which does not allow for the implementation of noise-immune PC control.

In addition, a common drawback of all the aforementioned devices is their lack of adaptability to non-linear processes occurring in noise-protected PCs, due to the functioning of the PC in a common receive-transmit environment where there are unstable and potentially dangerous digital or analog data streams, and the control system regularly switches to an unstable mode as a result of a random change in the volume and nature of the information received.

The problem to which the claimed utility model is directed is to develop a device capable of functioning under conditions of work with a significant level of a priori uncertainty of parameters in order to ensure the reliability of the noise-protected PC in the conditions of special influences and deliberate interference. In addition, all the modules included in the device must be in the common address space for organizing centralized management and monitoring the health of individual modules.

Achievable technical result - expansion of functionality, which consists in the following:

- providing analysis of external influences on the controlled object and the corresponding reaction to the impact of the external environment;

- providing exchange of control information between the managed object and the functional modules of the control device;

- ensuring the exchange of control information between the functional modules of the PC;

- ensuring information compatibility of various modules by converting management information into a form that is understandable to the subordinate modules;

- ensuring the monitoring of the health of individual modules and managing localization and troubleshooting;

- providing configuration management needed to identify and control the functioning of the PC;

- the availability of universality with respect to the structure and parameters of the noise-proof PC;

- ensuring the simultaneous (at the same time system time) and independent operation of the required number of PC elements;

- ensuring the implementation of the control device in the form of a block structure, which makes it easy to modify the control program of the claimed device for the next generations of managed objects.

To solve this problem, a control device for an interference-protected radio engineering system containing a central processor (CPU), a first read-only memory (ROM), a first random access memory (RAM), an input port (PV), an output port (PV), the first control bus (ШУ), the first data bus (ШД), the first address bus (ША), while the first group of inputs and outputs of the CPU is connected to the group of outputs of the first ROM via the first HDD, with the group of inputs and outputs of the first RAM, with the group of outputs of the PV, s the first group of PV inputs; the group of information outputs of the CPU through the first address bus (SHA) is connected to the group of inputs of the first ROM, with the group of inputs of the first RAM, with the first group of inputs of the PV, with the second group of inputs of the PV; the second group of PV inputs is connected to the group of outputs of the UO, the group of outputs of the PVs is connected to the second group of inputs of the managed object (UO), according to the utility model, the first input / output address decoder (SAI), serial asynchronous input-output module (MPAVV), module of formation are introduced unipolar control code (MF UKU), control module for the control signal driver (MU FKS); the group of control inputs of the first DAVA through the first ШУ is connected to the group of control outputs of the CPU, the group of information inputs of the first ДАВ through the first ША is connected to the group of information outputs of the CPU, and the outputs of the first ДАВВ are connected to the control inputs of the first ROM, first RAM, PV, PV , MF UKU and MU FKS; wherein the first group of inputs and outputs of the MPAVVY is connected to the second group of inputs and outputs of the CPU, the second group of inputs and outputs of the MPAVVY is connected to the first group of inputs and outputs of the UO; wherein the first group of inputs and outputs of the MF UKU is connected to the group of inputs and outputs of the CPU by the first SD, and the second group of inputs and outputs of the MF UKU is connected to the third group of inputs and outputs of the UO; wherein the group of inputs of the MF FCC is connected to the group of inputs and outputs of the CPU through the first SD, and the group of outputs of the MF FCC is connected to the third group of inputs of the UO; in addition, a slave processor (VP), a serial asynchronous output module (MPAV), a module for streaming data exchange interface (MPI OD), an output module (MVy), a second SAW, a second control unit, a second main circuit, a second main circuit, and a second ROM are introduced into the device second RAM; wherein the first group of inputs / outputs of the VP is connected to the third group of inputs and outputs of the CPU; while the group of control outputs of the VI through the second control unit is connected to the second group of inputs of the SAW, the second group of I / O of the VI through the second stage connection is connected to the group of outputs of the second ROM, with the group of inputs and outputs of the second RAM, with the group of inputs MVA; the first group of information outputs of the VP through the second ША is connected to the group of inputs of the second ROM, with the group of inputs of the second RAM and with the group of inputs of the second SAW; the second group of information outputs of the VP is connected to the group of inputs of the MPAV, the third group of inputs and outputs of the VP is connected to the first group of inputs and outputs of the MPI OD; the outputs of the second SAW are connected respectively to the control inputs of the second ROM, second RAM and MVy; the group of MVA outputs is connected to the first group of inputs of the MA, the group of outputs of the MPAA is connected to the group of inputs of the control device (MC), the second group of inputs and outputs of the MPI OD is connected to the second group of inputs and outputs of the MA.

Functional diagram of the inventive device is shown in figure 4, where the following notation:

1 - central module (CM);

2 - central processing unit (CPU);

3 - the first module of access and storage of data (CDM);

4 - the first read-only memory (ROM);

5 - the first random access memory (RAM);

6 - input port (PV);

7 - output port (PVy);

8 - the first control bus (SHU);

9 - the first data bus (BD);

10 - the first address bus (SHA);

11 - the first system bus (SS);

12 - the first decoder of input-output addresses (SAI);

13 - module serial asynchronous input-output (MPAVVy);

14 - module for the formation of a unipolar control code (MF UKU);

15 - control module shaper control signal (MU FCC);

16 - slave module (VM);

17 - slave processor (VP);

18 - module serial asynchronous output (MPAV);

19 - module streaming data exchange interface (MPI OD);

20 - the second module of access and storage of data (CDM);

21 - output module (MVy);

22 - second system bus (SS);

23 - the second decoder of the input-output addresses (SAI);

24 - the second control bus (SHU);

25 - the second data bus (BH);

26 - the second address bus (SHA);

27 - second read-only memory (ROM);

28 - second random access memory (RAM);

29 - control device (CC);

30 - managed object (UO);

31 - control device (UE).

The inventive device contains a managed object 30, a control device 29 and a control device 31. The control device 31 is a single system consisting of a central 1 and a slave 16 modules connected by interconnects.

The central module 1 includes:

central processor 2, first read-only memory 4, first random access memory 5, input port 6, output port 7, first control bus 8, first data bus 9, first address bus 10, first I / O address decoder 12, serial asynchronous module input-output 13, a module for generating a unipolar control code 14, a control module for the driver of the control signal 15; moreover, the first control bus 8, the first data bus 9 and the first address bus 10 form the first system bus 11, and the first read-only memory 4 and the first random access memory 5 form the first data access and storage module 3. The group of control outputs of the central processor 2 by means of the first control bus 8 is connected to the group of control inputs of the first decoder I / O addresses 12. The group of information outputs of the central processor 1 through the first bus address 10 is connected to the group of inputs the first read-only memory 4, with the group of inputs of the first random access memory 5, with the first group of inputs of the input port 6, with the second group of inputs of the output port 7, with the group of information inputs of the first decoder of the I / O addresses 12. The first group of inputs and outputs of the central processor 2 through the first data bus 9 is connected to the group of outputs of the first read-only memory 4, with the group of inputs and outputs of the first random access memory 5, with the group of outputs of the input port 6, with p the first group of inputs of the output port 7, with the first group of inputs and outputs of the module for generating the unipolar control code 14, with the group of inputs of the control module for the driver of the control signal 15. The second group of inputs and outputs of the central processor 2 is connected to the first group of inputs and outputs of the serial asynchronous input module output 13. The second group of inputs of input port 6 is connected to the group of outputs of the managed object 30, and the group of outputs of output port 7 is connected to the second group of inputs of the managed object 30. From the first to the sixth the outputs of the first I / O address decoder 12 are connected respectively to the control inputs of the first read-only memory 4, the first random access memory 5, the input port 6, the output port 7, the unipolar control code generation module 14 and the control signal driver control module 15. The second group of inputs the outputs of the serial asynchronous I / O module 13 is connected to the first group of inputs and outputs of the managed object 30, the second group of inputs and outputs of the unipo formation module the control code 14 is connected to a third group of inputs / outputs of the managed object 30; and the group of outputs of the control module by the driver of the control signal 15 is connected to the third group of inputs of the managed object 30.

The slave module 16 includes:

slave processor 17, serial asynchronous output module 18, stream communication interface module 19, output module 21, second I / O address decoder 23, second control bus 24, second data bus 25, second address bus 26, second read-only memory 27, a second random access memory 28, the second control bus 24, the second data bus 25 and the second address bus 26 form the second system bus 22, and the second read-only memory 27 and the second random access memory 28 form the second th access and storage module 20.

The first group of inputs / outputs of the slave processor 17 is connected to the third group of inputs and outputs of the central processor 1, the group of control outputs of the slave processor 17 is connected via the second control bus 24 to the group of control inputs of the second input / output address decoder 23; the second group of inputs / outputs of the slave processor 17 is connected via a second data bus 25 to the group of outputs of the second read-only memory 27, to the group of inputs / outputs of the second random access memory 28, to the group of inputs of the output module 21; the first group of information outputs of the slave processor 17 is connected via a second address bus 26 to the group of inputs of the second read-only memory 27, to the group of inputs of the second random access memory 28, to the group of inputs of the second input / output address decoder 23; the second group of information outputs of the slave processor 17 is connected to the group of inputs of the serial asynchronous output module 18; the third group of inputs and outputs of the slave processor 17 is connected to the first group of inputs and outputs of the module for the streaming data exchange interface 19. The first, second, and third outputs of the second input / output address decoder 23 are connected respectively to the control inputs of the second read-only memory 27, the second random access memory 28 and the output module 21, the group of outputs of which is connected to the first group of inputs of the managed object 30; the group of outputs of the serial asynchronous output module 18 is connected to the group of inputs of the control device 29, the second group of inputs and outputs of the module for the streaming data exchange interface 19 is connected to the second group of inputs and outputs of the managed object 30.

The functional purpose of the modules included in the UU 31 is described below. CPU 2 is designed to implement the basic logic of operation and is configured to receive multiple signals, and each signal corresponds to an assessment of the state of at least one element.

The first CDMA 3 is intended for storing transmitted and / or received data, identifiers of control commands associated with a particular device protocols and / or algorithms, assigned parameters related to periodic control commands. The first CDMA 3 includes the first ROM 4 and the first RAM 5.

The first ROM 4 is used to store information that does not change. Here you can store program memory data and tables of constant values necessary for the operation of the control device for an anti-interference PC. The first RAM 5 is used to store temporary information.

PV 6 and PV 7 are used to buffer information when accessing external devices in order to exchange information and control signals. PV 6 is designed to supply control actions to UO 30, and PV 7 is intended to read the state of UO 30 elements with the aim of making decisions about the need for exposure. Typically, for PV 6 and PV 7, the same address is allocated in the address space of CPU 2.

According to the first ШУ 8, information is generated, which is generated from the write and read signals generated by the CPU 2, which determines the logic of accessing devices connected to the CPU 2. According to the first ШД 9, information is transmitted depending on the operation that the CPU 2 is currently performing (write operation or reading). The first ША 10 transmits information intended for the identification of devices connected to the first ША 10, and each device is assigned an individual address.

The first DAVV 12 is designed to generate access permission signals to the corresponding devices.

MPAVVy 13 is designed to organize the interface with the elements that are part of the UO 30, and is a channel of bidirectional asynchronous data exchange.

MF UKU 14 is designed to generate and issue on U O 30 command words, data words or response words in the form of a parallel unipolar 16-bit code, or, conversely, for encoding 16-bit codes of command words, response words or words received from UO 30 data in the information package for transmission on the first SD 9 in accordance with the protocol used.

MU FKS 15 is designed to interact with elements that are part of UO 30 and form a functional module with an appropriate purpose.

VP 17 is designed to execute commands coming from the CPU 2 via the serial interface, and transmit sequential control actions on the elements that are part of the UO 30, but not directly related to the CM 1.

MPAV 18 is intended for the issuance of control information on the UK 29 to monitor the status of the UO 30, and is a serial asynchronous data transmission channel.

MPI OD 19 is designed to interface the information flows of the elements that make up the UO 30, and is a device that performs bidirectional synchronous data exchange with the UO 30 according to a specialized protocol.

Modules 20, 21, 23, 24, 25, 26, which are part of VM 16, are similar in purpose and execution to the corresponding CPU modules 2.

In addition, the connection of the modules 4, 5, 6, 7, 12, 14, 15 through the first SS 11 with the CPU 2 forms a common address space of the CM 1, which indicates the organization of centralized access to the CM 1 and provides standard access to the subordinate modules of the CPU 2 for management purposes.

In addition, the connection of modules 21, 23, 27, 28 through the second school bus 22 with VP 17 forms a common address space of VM 16, which indicates the organization of centralized access to VM 16 and provides standard access to subordinate modules of VP 17 for control purposes.

The operation of the claimed device is illustrated using the algorithms presented in figure 5 and 6.

The basis of the operation algorithm under conditions of an unpredictable change in the volume and nature of the processed information is the protocol for the interaction of CPU 2 with peripheral devices that are part of UU 31, allowing or prohibiting the transmission of signals between them depending on the task being implemented, taking into account the rules for the exchange of control actions required for the functioning of UO thirty.

Figure 5 presents the enlarged algorithm of the CPU 2. The work is as follows.

When turned on in block 2.1, the initial settings are set to modules 7, 12, 13, 14, 15, 17, and the control parameter values are initialized.

Next, in block 2.2, a detailed survey of slave modules 5, 6, 13, 14, 17 is performed in order to determine correctly (without errors) the functioning modules.

In block 2.3, the expected and obtained values of the functioning parameters are compared. If a mismatch between the expected and the obtained value of the operating parameters is detected in block 2.3, a transition to block 2.4 occurs; otherwise, a transition to block 2.7 occurs.

In block 2.4, the criticality of deviations of inconsistencies between the expected and the obtained parameter values is checked. If an unacceptable deviation is detected in block 2.4, the program stops working with the corresponding error message in block 17. If a valid deviation is detected in block 2.4, the program rewrites the parameters in the corresponding blocks in block 2.5, then the counter of the number of rewrites is checked in block 2.6 . If the number of overwrites does not exceed the control value, the program returns to block 2.3. If the number of attempts exceeds the control value, the program displays an error message in block 17 and exits.

Further, in block 2.7, the program initializes several independent routines for the functioning of the main program, which can be classified as follows:

- hardware interrupts (start in block 2.8);

- software interrupts (start in block 2.12);

- background tasks (beginning in block 2.14).

The execution of the hardware interrupt routine begins in block 2.8. If a message is received from slave module 13 or 14, the program interrupts the execution of background tasks and checks whether the action related to the interrupt is necessary. If the action is not required in block 2.8, it returns to the main program. If an action is required in block 2.8, then in block 2.9, the required action is performed and transition to block 2.10 occurs.

In block 2.10, the current state of CPU 2 is checked. If the next change in the state of CPU 2 is required as a result of receiving a message from modules 13 or 14, then transition to block 2.11 occurs. If a change of the current state is not required, it returns to the main program.

In block 2.11, information about the state change is fixed and the number of the next state is determined. Next is the return to the main program.

The execution of the program interrupt routine begins in block 2.12. A check is made whether it is necessary to evaluate a certain queue of events to be performed, or whether the next command should be sent to UO 30. If action is not required in block 2.12, it returns to the main program.

If the need to perform an action is detected in block 2.12, the transition to block 2.13 is performed, where the required action is performed. Then there is a transition to block 2.10.

In block 2.10, the current state of CPU 2 is checked. If in block 2.10 the next change in the state of CPU 2 is required as a result of performing the action in block 2.13, then transition to block 2.11 occurs. If a change of the current state is not required, it returns to the main program.

The execution of the background tasks subroutine begins in block 2.14. CPU 2 polls all monitored connections. According to the data obtained, a conclusion is made about the presence or absence of errors in the functioning of controlled units. If in block 2.15 there was a discrepancy between the expected and received value, in block 2.16 a code sequence with an error message is issued to the control object according to the control protocol.

Next, the polling cycle is repeated with a periodicity Δt determined by the objective function of the system.

Figure 6 presents the enlarged algorithm of the work of VP 17. The work is as follows.

When you turn on in block 17.1, the initialization and setting of the initial values of the operating parameters of the VP 17 in accordance with a priori settings.

Next, in block 17.2, a command is received from the CPU 2, which determines the mode of further operation of the VP 17.

In block 17.3, the modules 18, 19, 21, 23, 28, subordinate VP 17 are initialized in accordance with the instructions received from the CPU 2.

In block 17.4, control signals are issued to the MPI OD 19 in order to obtain the necessary data from UO 30 for transmission to CPU 2.

In block 17.5, control signals are issued to the airspace of the VP 21 to transfer the necessary data to UO 30, where, in accordance with these data, the signals of the corresponding functional modules of UO 30 are installed.

In block 17.6, data is sent to MPAV 18 in order to bring information about operations to UK 29.

Next, the VP 17 goes into standby mode commands from the CPU 2.

The interconnect structure in UU 31 provides the implementation of management and maintenance tasks for heterogeneous functional modules, operational control and coordinated interaction between different types of modules. At the same time, management is organized according to uniform principles using modern information technologies.

In addition, all the modules included in the device are located in a common address space, which allows for centralized management and control of the health of individual modules with the issuance of information to the control device. Periodic receipt of information about the health of individual components provides operational control over the managed object and allows for various control actions on faulty modules. UU 31 also provides the implementation of functions for identifying a PC and provides the ability to programmatically change the configuration of a managed PC by commands from an external device due to the presence of access and storage devices.

Thus, UU 31 collectively provides the control functions necessary to determine the technical condition of individual elements and the effectiveness of the functioning of the noise-protected PC as a whole, and provides localization and troubleshooting in the operation of individual elements and the system as a whole.

When implementing the utility model, it was taken into account that the functionality compared with the steps of the operation algorithm can be achieved only with a combination of software and hardware. Using the direct digital control mode, it was possible to apply more effective principles of regulation and control and choose their optimal option, as well as implement optimizing functions and adapt to the variable parameters of the control object.

The proposed device with a central 1 and slave 16 control modules can be implemented on the following elements:

- CPU 2 and VP 17 processors can be implemented on the basis of a specialized digital element, including a high-performance core and Flash-memory [8, 9];

- access and data storage modules 3, 20 can be implemented on the basis of volatile and / or non-volatile memory devices [7, 8];

- the module for generating a unipolar control code 14 can be implemented on the basis of specialized digital elements - terminal device controllers for multiplex communication lines [11] or on FPGA elements [10] (programmable logic integrated circuits);

- modules of serial asynchronous input-output 13 and serial asynchronous output 18 can be implemented as one of the standard RS 232/422/485 joints on the basis of specialized digital elements [6, 8, 10] or on the basis of foreign and domestic digital elements of standard logic;

- control module for control signal driver 15, address decoders 12, 23, input-output ports 6, 7 can be implemented on the basis of foreign and domestic digital elements of standard logic.

Improving the functionality of the PC control device is achieved due to the fact that the introduction of new modules provides the conversion of control information into a form that is understandable to the managed object in order to ensure information compatibility of communication protocols between the functional modules included in the PC and unconnected interconnects. In addition, the interaction of the central and slave processors configured on the basis of a multifunctional highly integrated data processing system, including a high-performance core and Flash memory, allows data processing at different time scales in accordance with the target function of the control object.

The algorithm of the PC control device is supported by the architecture of the claimed device and fits into the reasonable cost of resources to implement the necessary logic. Moreover, the work of the claimed device provides for testing errors associated with logical violations when setting the source data of the exchange rules.

Thus, the claimed device provides improved functionality of the control systems of the noise-proof PC and will be especially effective for controlling systems with a significant level of a priori uncertainty of parameters in order to provide additional protection for the system under special conditions and deliberate interference.

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6. - electronic components of the company "MAXIM".

7. - electronic components of the company "Texas Instruments".

8. - electronic components of the company "ATMEL".

9. - electronic components of the company "Silicon Labs".

10. - electronic components of the company "ALTERA".

11. Radioelectronic Components of the company Plant Transistor Unitary Enterprise, Minsk.

Claims (1)

A control device for an anti-interference radio engineering system comprising a central processing unit (CPU), a first read-only memory (ROM), a first random access memory (RAM), an input port (PV), an output port (PV), a first control bus (SHU), a first a data bus (SH), a first address bus (SH), the first group of inputs and outputs of the CPU through the first SH being connected to the group of outputs of the first ROM, with the group of inputs and outputs of the first RAM, with the group of outputs of the PV, with the first group of inputs of the PV; the group of information outputs of the CPU through the first address bus (SHA) is connected to the group of inputs of the first ROM, with the group of inputs of the first RAM, with the first group of inputs of the PV, with the second group of inputs of the PV; the second group of PV inputs is connected to the group of outputs of the UO, the group of outputs of the PVs is connected to the second group of inputs of the managed object (UO), characterized in that the first input-output address decoder (SAI), serial asynchronous input-output module (MPAVV), module are introduced formation of a unipolar control code (MF UKU), a control module for the control signal driver (MU FKS); the group of control inputs of the first DAVA through the first control unit is connected to the group of control outputs of the CPU, the group of information inputs of the first DAVA through the first ШA is connected to the group of information outputs of the CPU, and the outputs of the first DAVA are connected to the control inputs of the first ROM, first RAM, PV, PV , MF UKU and MU FKS, while the first group of inputs and outputs MPAVVY connected to the second group of inputs and outputs of the CPU, the second group of inputs and outputs MPAVVY connected to the first group of inputs and outputs of the UO, while the first group in the odes-outputs of the MF UKU through the first SD is connected to the group of inputs and outputs of the CPU, and the second group of inputs and outputs of the MF UKU is connected to the third group of inputs and outputs of the UO, while the group of inputs of the MU FKS through the first ST is connected to the group of inputs and outputs of the CPU, and the group of outputs of the MU FCC is connected to the third group of inputs of the UO; in addition, a slave processor (VP), a serial asynchronous output module (MPAV), a module for streaming data exchange interface (MPI OD), an output module (MVy), a second SAW, a second control panel, a second main circuit, a second main circuit, and a second ROM are introduced into the device the second RAM, while the first group of inputs / outputs of the VP is connected to the third group of inputs / outputs of the CPU; the group of control outputs of the VI through the second control unit is connected to the second group of inputs of the SAW, the second group of I / O of the VI through the second stage is connected to the group of outputs of the second ROM, with the group of inputs and outputs of the second RAM, with the group of inputs MVs, the first group of information outputs of the VI through the second ShA is connected to the group of inputs of the second ROM, to the group of inputs of the second RAM and to the group of inputs of the second SAW, the second group of information outputs of the VI is connected to the group of inputs of the MPA, the third group of inputs and outputs of the VI is connected to the first group the inputs and outputs of the MPI OD, the outputs of the second SAW are connected respectively to the control inputs of the second ROM, second RAM and MVA, the group of MVA outputs is connected to the first group of UO inputs, the group of MPAV outputs is connected to the group of inputs of the control device (CC), the second group of inputs and outputs MPI OD is connected to the second group of inputs and outputs of the UO.

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