RU103635U1 - DIGITAL SWITCHING SYSTEM USING THE TIME STAMP - Google Patents

Abstract

 A digital switching system (CSK) using a time stamp containing input and output code converters, time counters, address memory blocks and group path blocks, characterized in that it additionally contains blocks for fixing the time moments of signal arrival to the CSK, a control unit with A computer, the control unit with a computer designed to replace the addresses of incoming communication lines, an address memory unit, a primary memory unit, as well as primary and secondary memory units, blocks for recording recording of switched signals, b comparison codes of time codes and subscriber units, as well as a distribution block of switched signals, while the input converters have (1 ... m) inputs and are connected in series with the fixation blocks, the latter being connected to each other and to the time counter, then the fixation blocks are connected (1 ... n) inputs with a group path unit, which is connected to the control unit, the control unit of the first input connected to the computer, the second input to the address memory unit and the third input to the switching signal distributor, the splitter (1 ... n) with inputs is connected in parallel to the primary memory blocks, which are connected to the secondary memory blocks, the secondary memory blocks being connected with the input code converters as the first output, and the switching blocks for recording recorded signals with the second output (1 ... m) outputs, and the third inputs - with blocks comparing time codes that are interconnected, as well as with a time counter and input converters having (1 ... m) outputs to subscriber units.

Description

The utility model relates to the field of electrical engineering, namely to the technique of wire communication and can be used in the construction of asynchronous DSCs using a timestamp (code).

Known digital switching systems are completely dependent on the stringent requirement of signal switching over a period of time not exceeding the allowable level of edge distortion of the signals δ = 2%. Such a dependence sharply reduces the possibility of switching discrete signals in the form of isochronous sequences with increasing carrier frequency. For example, the digital switching system EDS, developed by Siemens, Germany. The essence of this system is that at the entrance and exit of the CSK, time counters and registers of incoming and outgoing communication lines are installed. Counters and registers of incoming lines fix the code (label) of time the moments of receipt of the switched signals at the inputs of the CSK. Those. Using the time code coming from the counters, significant modulation moments (ZMM) of the switched signals are recorded. In this case, the time code from the time counters and the code (0,1) of the switched signal are recorded in the registers of the corresponding incoming communication lines. This information can be stored in their registers until subsequent ZMMs are received, which makes it possible to transmit through the group path the signals of all incoming communication lines for a period of time equal to the total duration of the switched signals.

Such a system allows the processing and switching of isochronous and non-isochronous discrete signals for a constant period of time equal to the duration T of the switched signals.

Therefore, such a system is a CSK with a constant delay of switching signals.

The presented DSC provides the service of incoming communication lines more than the known DSC when using the synchronous combination of digital signals, but this is not enough, since with each year the flows of information signals increase several times.

The purpose of the utility model is to increase the capacity of the DSC for telegraph communication.

This goal is achieved by the fact that the system contains input and output code converters, time counters, address memory blocks and group path blocks, additionally blocks of fixation by the time code of signal arrival times to the CSK, a control unit with a computer, and a control unit with a computer are designed replacement of addresses of incoming communication lines, an address memory block, a primary memory block, as well as primary and secondary memory blocks, blocks for recording recording of switched signals, blocks for comparing time codes and subscriber b locks, as well as a distribution block of switched signals, while the input converters have (1 ... m) inputs and are connected in series with the fixation blocks, the latter being connected to each other and to the time counter, then the fixation blocks are connected (1 ... n) by the inputs to the group block the path, which is connected to the control unit, and the control unit of the first input is connected to a computer, the second input with an address memory unit and a third input with a switching signal distributor, while the distributor (1 ... n) is connected in parallel with primary memory blocks that are connected to the secondary memory blocks, the secondary memory blocks being connected to the inputs of the code converters by the first output, the second output with the switched Sigalov recording blocking blocks, the latter having (1 ... m) outputs, and the third inputs with time code comparison blocks, which are interconnected as well as with a time counter and input converters having (1 ... m) outputs to subscriber units.

In FIG. presents a block diagram of an asynchronous DSC using a time code.

The circuit contains input 1 and output 2 code converters, latching blocks 3 with a time code of the moments of arrival of signals to the DSC, time counters 4, generating a binary time code, using the base frequency of the station generator, a group path block 5 that provides dial-up information in a group path (GT), the control unit 6 and the address memory unit 7, switching the incoming and outgoing communication lines and the transformation of the addresses of the incoming communication lines to the addresses of the outgoing lines during information transfer through GT, switchboard of switched signals 8 in outgoing directions, blocks of primary 9 and secondary 10 memory that provide storage of switched signals, blocking blocks 11 for recording switched signals in blocks of secondary memory 10 and, comparison blocks 12 time codes, subscriber units (AB) 13, Computer 14.

AB input subscriber units are connected to input 1 and output 2 code converters, each of which provides service for ℓ subscriber sets. The total capacity of the asynchronous DSC shown in FIG. is N-nm ℓ incoming and outgoing communication lines, where m is the number of subscriber sides provided by one water code 1 converter (2); n is the number of input 1 and (output 2) code converters, serviced respectively by the group path unit 5 and the switching signal distributor 8.

CSK works as follows.

The control unit receives from the computer the numbers (addresses) of the incoming and outgoing communication lines, which must be switched between each other, and writes them to memory cell 7. Moreover, each incoming line has its own memory cell in 7, into which the address of the outgoing line connected to it is recorded communication. Subscriber units 13 receive switched signals from the incoming communication lines and give them to the incoming code 1 converters, which in turn encode the leading edge of the positive signals with code 1, and the trailing edge - 0. This code is sent from the input code 1 converter further accompanied by addresses of incoming lines communication, which received the switched signals, in the block 3, which is a storage device (memory), write in their memory cells the signal codes and time code. In this case, each incoming communication line has its own memory cell in the fixation blocks 3. The numbers of the cells and communication lines are the same, but the time recorded in the memory cells 3 captures the moments of arrival of the codes of the switched signals in the fixation blocks 3.

When servicing using the fixation unit 3 groups of incoming communication lines L = lm, there may be cases of simultaneous receipt of several switched signals at the input of the corresponding input code converter 1. In this case, a service queue k arises, which leads to edge distortions of the switched signals.

δ ¹ = (kτ _per / T) 100%, k = 2 ÷ lm,

τ _zap - clock recording of switched signals in blocks of fixation 3; T is the duration of the switched signal.

Edge distortions arise due to the fact that latching unit 3 is not constructed in the form of separate registers capable of receiving switched signal codes independently, but in the form of memory using integrated memory circuits, which greatly simplifies the DSC, but leads to the need to alternately maintain switched signals through the common input of the fixing block 3. However, given the high speed of the semiconductor memory, the value of δ ^{1 is} negligible.

The group path unit 5 reads the information from the memory cells of the latching unit 3 and provides it to the control unit 6. In this case, either synchronous or asynchronous temporal combination of signals in the GT can be used. In the first case, the reading of the memory cells of the fixing block 3 is carried out cyclically, in the second - in accordance with the priorities of the served communication lines according to their requirements. Memory cells are read in latching unit 3 at certain intervals of the GT operating time, in which signal codes, time codes, and addresses of incoming communication lines are also transferred from group path unit 5 to latching unit 3. At the same intervals, readings are made from memory cells address memory block 7 addresses of outgoing communication lines to which it is necessary to issue codes of switched signals.

The control unit 3 and the address memory unit 7 provide replacement of the addresses of the incoming communication lines coming from the group path unit 5 with the addresses of the outgoing communication lines, which, together with the codes of the switched signals and their time codes, enter the distributor of the switched signals 8 and then to the primary memory unit 9. The distribution of information in blocks 9 is carried out using a switchboard of switched signals 8, using the addresses of outgoing communication lines accompanying the information.

The primary memory unit 9 has a number of memory cells corresponding to the number of outgoing communication lines. The numbers of memory cells and outgoing lines are the same. The blocks of the secondary memory 10 have memory cells similar to the memory cells 9.

Information from the memory cells of the block of primary memory 9 is read out cyclically and issued to the inputs of the corresponding blocks 10. At the same time, from block 11, the inputs of block 10 also receive the status codes of outgoing communication lines, for which information from block 9 is currently being issued. comparison of the line status code and the edge code of the switched signal. If these codes are the same, then the recording of the received information from block 9 is blocked, and instead of the write operation, information is read from the same cell 10 into which the recording was to be made. If the codes are different from each other, then a write operation is performed.

The need to use blocks 9, 10 and 11 is explained by the fact that the edge distortion of the switched signals can reach a significant value. In this case, there may be cases when the subsequent code of the switched signal is transmitted through the GT, while the previous code is still in block 10. In this case, the new code of the switched signal will be recorded in block 9 and its further transmission in block 10 will be blocked by block encodings 11 until the previous code of the switched signal is issued from block 10 to the outgoing communication line.

Information is recorded in the memory cell of blocks 10 with the simultaneous delivery of this information, as well as the address of the cell into which the information is written, to the inputs of block 2. In this case, a time code is issued to one of the inputs of block 12, and a time code from the output is received to the other input block 4. In the block comparing time codes 12, a comparison of these time codes. If the codes are the same, then the signal α = 1 is generated, and if different, then α = 0. The signal α = 1 provides the distribution using blocks of 2 codes of signals and addresses of outgoing communication lines coming from block 10, to subscriber units in accordance with the address of subscriber sets.

Thus, the use of a timestamp (code) as an additional switching factor can significantly increase the throughput of the group path of the switching system. In particular, with δ = 2% and using the synchronous principle of digital signal switching, the throughput of the group path of the switching system can be increased by 50 times.

Claims (1)

A digital switching system (CSK) using a time stamp containing input and output code converters, time counters, address memory blocks and group path blocks, characterized in that it additionally contains blocks for fixing the time moments of signal arrival to the CSK, a control unit with A computer, the control unit with a computer designed to replace the addresses of incoming communication lines, an address memory unit, a primary memory unit, as well as primary and secondary memory units, blocks for recording recording of switched signals, b comparison codes of time codes and subscriber units, as well as a distribution block of switched signals, while the input converters have (1 ... m) inputs and are connected in series with the fixation blocks, the latter being connected to each other and to the time counter, then the fixation blocks are connected (1 ... n) inputs with a group path unit, which is connected to the control unit, the control unit of the first input connected to the computer, the second input to the address memory unit and the third input to the switching signal distributor, the splitter (1 ... n) with inputs is connected in parallel to the primary memory blocks, which are connected to the secondary memory blocks, the secondary memory blocks being connected with the input code converters as the first output, and the switching blocks for recording recorded signals with the second output (1 ... m) outputs, and the third inputs - with blocks comparing time codes that are interconnected, as well as with a time counter and input converters having (1 ... m) outputs to subscriber units.