RU1010U1 - Cardiac analyzer - Google Patents

Abstract

1. Cardiac analyzer containing a multichannel converter amplifier, the outputs of which are connected to the first group of inputs of a multichannel analog switch, serially connected by an analog-to-digital converter, an interface and an electronic computer with a display and a recording unit, characterized in that between the output of the multichannel analog switch and the input An analog-to-digital converter includes an amplifier with controlled gain and bias voltage, and multi-channel outputs of transducing amplifier further inputs connected selectively multichannel amplifier, each amplifier channel which includes a controllable passband and sample and storage device, outputs of which are connected to additional inputs of multichannel analog kommutatora.2. A card analyzer according to claim 1, characterized in that the interface comprises a microprocessor connected through an information exchange unit to an electronic computer and through an interface unit to a bandwidth input of a multi-channel selective amplifier, channel switching of a multi-channel analog switch, an analog-to-digital converter output and inputs control amplifier with controlled gain and bias voltage. 3. A card analyzer according to claim 2, characterized in that the interface unit comprises a decoder of recording signals, the digital inputs of which are connected to the address bus of the microprocessor, and the input of resolution is a circuit of the write signal of the control bus of the microprocessor, a decoder of read signals, the digital inputs of which are connected

Description

CARDIO ANALYZER

The utility model relates to medical equipment, in particular to medical devices for studying the functional state of the cardiovascular system.

A device for recording electrocardiograms (see USSR author's certificate N 1155245, M Cl. 4 A61B 5/04, publ. 1985, BI N 18), containing five electrodes, ten resistors and a four-channel recorder, which allows to increase the information content of electrocardiographic curves due to additional leads, reflecting the potentials of the anterior apical region.

The disadvantage of this device is the lack of automation of processing and the absence of polygraphic removal of electrocardiograms, i.e. simultaneous removal and measurement of an electrocardiogram from each assignment.

A known cardiac analyzer (see USSR author's certificate N 1047464, M Cl. 3 A61 B 5/02, publ. 1983, BI N 38), containing a serrated R wave detector, RR interval measurement unit, time ratio analysis unit, arrhythmia analysis unit and display unit. This cardiac analyzer provides current analysis of the electrocardiogram with the formation of a diagnosis of bradycardia, tachycardia, arrhythmias and extrasystoles.

The disadvantage is the lack of the ability to print electrocardiograms.

The closest in technical essence to the claimed cardiac analyzer is a 12-channel electrocardiograph

BIOSET 8000 from MeBgeratewerk Zwonitr GtabH Germany. This comM Cl. 5 A 61 V 5/02

The computerized cardiac analyzer has wide functionality and contains a series-connected electrode block, a twelve-channel pre-amplifier, a programmable lead switch, a three-channel terminal amplifier, an analog-digital converter, an interface, an electronic computer with a display and a thermal printing device. The BIOSET 8000 electrocardiograph is not accurate enough for taking polygraphic electrocardiograms.

The purpose of creating the claimed utility model is to increase the accuracy of the removal of printing electrocardiograms.

This goal is achieved by the fact that in a cardiac analyzer containing a multi-channel preamplifier, the outputs of which are connected to the first group of inputs of a multi-channel analog switch, the analog-digital converter, an interface and an electronic computer with a display and a recording unit are connected in series between the output of the multi-channel analog switch and the input of the analog-to-digital converter includes an amplifier with controlled gain and bias voltage, and to the outputs inputs of the multi-channel selective amplifier, each channel of which includes an amplifier with a controlled bandwidth and a sampling and storage device, and the outputs of which are connected to additional inputs of a multi-channel analog switch, while the bandwidth control inputs of a multi-channel selective amplifier, switching control inputs channels of a multi-channel analog switch, control inputs of the amplifier with controlled coefficients entom gain and bias voltage are connected to the additional output interface. The interface contains a microprocessor connected through an information exchange unit with an electronic computer and through an interface unit with inputs for controlling the passband of a selective amplifier, switching channels of a multichannel analog switch, the output of an analog-to-digital converter, and the control input of an amplifier with a controlled gain and bias voltage. The interface unit contains a decoder of the recording signals, the digital inputs of which are connected to the address bus of the microprocessor, and the input resolution with the signal circuit of the write signal of the control bus, signal decoder

Wx / w

from/

- - readings, the digital inputs of which are connected to the address bus, and the permission input to the read signal circuit of the control bus, four storage registers, the digital inputs of which are connected to the microprocessor data bus, and the recording inputs with the outputs of the decoder of the write signals, D-trigger, bit input which is connected to the low-order circuit of the data bus, and a clock input with the first output of the read signal decoder, and an output with the input CONVERSION of an analog-to-digital converter, a matching circuit, the first input of which is connected from the second the output of the decoder of the read signals, the second input with the READINESS ADC output of the analog-to-digital converter, and the output with the read input of the fifth storage register, the digital inputs of which are connected to the code output of the analog-digital converter, and the outputs with the data bus of the microprocessor, while the outputs of the first storage register are connected to the bandwidth control inputs of a multi-channel selective amplifier, the second to the channel switching control inputs of a multi-channel analog switch, the third and fourth Grated with inputs for controlling the gain and bias voltage of the amplifier with controlled gain and bias voltage.

The authors are not aware of cardiac analyzers that match technical specifications and design features, so the authors believe that the claimed technical solution is novel.

The structural implementation of the claimed utility model is illustrated by drawings.

Figure 1 shows the structural diagram of the claimed cardiac analyzer;

figure 2 shows the functional diagram of a multi-channel pre-amplifier;

Fig. 3 shows a functional diagram of a multi-channel selective amplifier;

figure 4 shows an embodiment of an amplifier with controlled gain and bias voltage;

figure 5 shows an embodiment of a device for sampling and storage on a chip type MAX 292;

figure 6 shows the structural diagram of the interface;

H-Qb№ $ 4

figure 7 shows the structural diagram of the pairing unit.

The claimed cardiac analyzer (figure 1) contains a block of electrodes 1, a multi-channel pre-amplifier 2, a multi-channel selective amplifier 3, a multi-channel analog switch 4, an amplifier 5 with controlled gain and bias voltage, an analog-to-digital converter 6, an interface 7 and an electronic computer 8 with a display 9 and a recording unit 10. The electrode block contains a reference electrode R, control electrodes E, N and lead electrodes L, F, С ... С „for the implementation of standard leads. The outputs of the multi-channel pre-amplifier 2 are additionally connected to the inputs of the multi-channel analog switch 4, the outputs of the interface 7 are connected to the control inputs of the multi-channel selective amplifier 3, multi-channel switch 4 and amplifier 5.

The multi-channel pre-amplifier 2 (Fig. 2) contains in each channel a differential amplifier 12 with negative feedback, a non-invertible input connected to the corresponding output electrode of unit 2, and invertible in addition to the output of an amplifier 11 with negative feedback, a non-inverted input connected to a reference block 2 electrode. Amplifiers 11 and 12 can be implemented on type 140UD14 microcircuits. The multi-channel selective amplifier 3 (FIG. 3) comprises in each channel a controlled bandwidth amplifier 3 and a sampling and storage device 14. The amplifier 13 contains an analogue US switch, the outputs of which are connected by a resistive divider R7 ... R10, a limiter on diodes Dl, D2 and an amplifier U4 with negative feedback (resistors Rll, R12, capacitor C2). The passband of the amplifier 13 is changed by switching the capacitor C1 to the shoulders of the resistive divider R7 ... R10. Amplifier 5 with controlled gain and bias voltage (Fig. 4) can be implemented using two microchips 15 and 16 of type K572PA1 and two operational amplifiers U5, U6 of type KP574UD1. A gain code is supplied to the digital inputs of the microcircuit 15, and a bias voltage code to the digital inputs of the microcircuit 16. The outputs 1.2 of the microcircuit 15 are connected to the inputs of the operational amplifier U5, the output of which is connected to the input 15 of the reference voltage of the microcircuit 15. The input signal is fed to the input 16 of the resistor

feedback of the microcircuit 15. Output 1 of the microcircuit 16 is connected to the output 1 of the microcircuit 15. The operational amplifier U6 is designed to set the initial bias. The reference voltage + Uon is applied to pin 15 of the microcircuit 16, and pin-16 receives voltage -Uon / 2 from the output of the operational amplifier U6.

The device 14 sampling and storage (figure 5) can be implemented using a filter on switched capacitors of a chip type MAX 292. In this case, contacts 3,4 are interconnected, contact 8 receives a signal from the output of amplifier 15, and contact 1 is gated the signal from the timer of the microprocessor 18, the output signal is removed from pin 5. The interface 7 (Fig.6) contains a microprocessor 18 connected through an information exchange device 17 of the RS 232 type to an electronic computer 8 and through a multi-channel selective amplification interface unit 19 An amplifier 3, a multi-channel analog switch 4, an amplifier 5, and an analog-to-digital converter 6. An additional memory unit 20 can be connected to the microprocessor 18.

The interface unit 19 (Fig. 7) contains a decoder 21 of the write signals, a decoder 22 of the read signals, storage registers 23 ... 27, a D-flip-flop 28 and a matching circuit 29. The digital inputs of the decoders 21 and 22 are connected to the address bus of the microprocessor 18, input permissions of the decoder 21 is connected to the control bus circuit WR, the enable input of the decoder 22 is connected to the control bus circuit RD, the digital inputs of the registers 23 ... 26 are connected to the data bus of the microprocessor 18, the recording inputs of these registers are connected to the outputs WR1 ... WR4 of the decoder 22 , the digital inputs of register 27 are connected to the code output of the analog-to-digital converter 6, the input D of the D-trigger is connected to the low-order circuit of the microprocessor 18 data bus, the input C of the D-trigger is connected to the output RD1 of the decoder 22, the first input of the matching circuit 29 is connected to the output RD2 of the decoder 22, the second input to the READINESS ADC of the analog-to-digital converter 6, the outputs of the register 23 are connected to the control inputs of the amplifier 13, the outputs of the register 24 are connected to the control inputs of the unit 4, the outputs of the registers 25, 26 are connected to the control inputs of the amplifier 5, the output of the D-trigger 28 is connected to TRANSFORMATION ode D converter 6.

The claimed cardiac analyzer allows the complex3} No. iW

-JT research method of the cardiovascular system. For one examination session, cardiac signals can be recorded and analyzed during simultaneous removal from 12 standard leads or leads according to Frank, while the lead method, correction of measurement errors, and diagnostics are performed automatically in accordance with a given program. To remove the electrocardiogram, electrodes are used that meet the requirements of GOST 26995-85. The electrodes are fixed on the patient’s body using special devices that are part of unit 1 (cuffs, corsets, suction cups). Before connecting the electrode to reduce the electrode-skin resistance, a special electrically conductive paste is applied to the skin.

After installing the electrodes, all equipment is turned on, from the computer 8 through the exchange device 17 to the microprocessor 20 codes of operations are submitted, which should be performed by the microprocessor according to the research program. The microprocessor 18 provides the generation of control commands for executing operations and transmits them to the interface unit 19 via data buses (SH), address (SH) and control (SH), in which control signals are supplied to the remaining blocks. The operation algorithm may be as follows. After the microprocessor is initialized, the nominal exchange rate with the computer 8 is established, the readiness for operation of the memory unit 20, RAM and the microprocessor 18 is interrogated, and the computer 8 sends a readiness signal for the microprocessor 18 to receive commands. The readiness of the memory unit 20 to work will be confirmed after balancing the gain channels of the amplifier 3, which is carried out as follows. In block 19, from the microprocessor 18, the code number 1 is supplied via the address bus, the write signal WR and the data bus are zero code, as a result, zero is recorded in register 23 and in the multichannel selective amplifier 3 in all analog keys of the ultrasound input X will be connected to zero output, i.e. non-invertible inputs of amplifiers U4 will be connected to zero potential through the divider R7 ... R10. Then, from the microprocessor 18, the code number 2 is supplied to the block 19 via the address bus, the write signal WR and the code of the first channel number on the data bus. As a result, the number code is written in register 24

the first channel, and in the analog switch 4, the output of the first channel of the amplifier 3 is connected to the input of the amplifier 5. Further from the microprocessor 18, the code of the number 3 is supplied via the address bus and the signal WR is sent via the control bus, the code is 3 by the data bus, as a result, it is written in register 25 the code number 3 and the gain of the amplifier 5 is set to maximum. Similarly, a code of 128 is written to register 26 and the bias voltage is set to 1/2 Uon. After that, the unit code is supplied via the address bus, the RD signal is sent through the control bus, and the unit bus is through the least significant data bus Do, as a result, the CONVERTER signal from the output of D-flip-flop 28 will be sent to the analog-to-digital converter 6 and the analog-to-digital converter will begin to convert the signal from the output of amplifier 5 to the code. Meanwhile, on the address bus, the code changes to two and the RD2 signal is fed to the input of coincidence circuit 29, to the second input of which the ADC READY signal is received. After the conversion is completed, the code from the analog-to-digital converter 6 is written to register 27. This code is transmitted to the data bus microprocessor 18 and is compared with zero. If the code is greater than zero, then the bias voltage code stored in register 26 decreases by half, if less than zero, it increases by half, and if it is zero, then the code from register 26 is written to memory unit 20 at the address corresponding to the channel number, and in register 23, the next channel number code is recorded. After the bias voltage codes are determined for all channels of the amplifier 3, the optimal value of the gain of the amplifier 5 is established for each channel.

Before describing this procedure, we consider the operation of individual nodes of the claimed cardiac analyzer. The multi-channel pre-amplifier 2 (Fig. 2) is made according to the scheme described in the book by S.G. Danko, Yu.L. Kaminsky System of technical means of neurophysiological studies of a person L., Nauka, 1982, p. 46, Fig. 7. A characteristic feature of such an amplifier is that at the output of any of the amplifiers 12, the voltage will be proportional to the difference between the signal voltages at the corresponding outlet electrode (L, F, C1 ... C6) and at the reference electrode R, i.e. the signals will correspond to a monopolar lead, and the interference voltage at the outputs of the amplifiers will be absent when the amplification factors of the amplifiers 11 and 12 are equal, i.e. with equality and.

- // - $ # / # (#

- Non-invertible inputs of amplifiers 11 and 12 are connected through resistors R5 and R6 to the reference voltage source Uon. Therefore, with poor contact of the electrode with the skin, the voltage at the output of the amplifiers 12 will exceed the control, which is a signal for re-fixing the electrodes.

The multi-channel selective amplifier 3 (FIG. 3) consists of the same amplifier channels, each of which contains a series-connected amplifier 13 and a sampling and storage device 14. The amplifier 13 contains a high-pass filter (C1, UZ, a divider R7 ... R10), a two-way limiter (diodes D1, D2) and a broadband amplifier U 4. The high-pass filter is an analog UZ switch to the input of which a signal is transmitted through capacitor C1, the filter strip code (RC chain time constant) to the control inputs, and the zero bus of the power supply is connected to the outputs, the non-invertible input of the U4 broadband amplifier is connected to the first, and the points of the resistive divider R7 ... R10 connecting the non-inverter to the rest my input of amplifier U4 zero bus. When changing the code at the inputs of AO ... A2, capacitor C1 is connected to a non-invertible input either directly or through a resistor R7 ... R9, thereby changing the constant RC chain and the high-pass filter band.

The sampling and storage device is made on a MAX 292 chip - a filter on switched capacitors and additionally performs the functions of a low-pass filter.

Amplifier 5 (figure 4) with adjustable bias voltage and gain is made on two DAC chips 15 and 16 of type K572PA1 and operational amplifiers U5, U6 of type KP574UD1.

The voltage at the output 1 of the chip 16 is equal to:

Yiom - Uon -8Ц - | ,

where NCM is the voltage code value,

Uon is the reference voltage. The voltage at the output of the operational amplifier U5 is equal to:

Ivyh - Shvh + UCM,

1 ",. / L-I

1 + k256

where k is the gain of the operational amplifier U5, Ny is the value of the gain code, UBX is the input voltage of the amplifier 5.

With 1 live Ts- UBX +

- J56. g u „JCM L fl Ny - UBX + UOTK 128 2 Thus, the gain of amplifier 5 with sufficient accuracy of approximation is equal to:

Ku-yy, where Ny ranges from 1 to 256.

The removal of electrocardiograms is as follows. In the register 23 is written the code of the passband, in the register 24 is the code number of the 1st channel. From the memory unit 20, a gain code of the amplifier 5 Ny and a bias voltage code NCM are selected. These codes are recorded in registers 25 and 26. Then, the CONVERSION signal is sent to the analog-to-digital converter 6, and after it is ready to be read, the signal level code in the first channel is read into register 27, the outputs of which are connected to the data bus. Further, an error code for the 1st channel is extracted from the memory unit 20 and the reading is corrected, i.e. code 128 is subtracted from the code written in register 27 and the error code is added, the result is checked for minimum and maximum (if the result is less than zero, then zero is fixed, if the result is more than 255, then 255 is fixed). After the correction, the signal level code and the gain code of the amplifier 5 are transmitted to the computer. In the computer 8, the channel number code, the gain of the amplifier 5, the signal level, and the pick-up time are written to the memory. Further, data from the remaining channels are read in a similar manner. After the last channel is polled, the polling cycle is repeated. The recorded electrocardiograms can be viewed on the display screen 9 in any quantity.

Editing of the taken electrocardiograms can be carried out both during the examination and after. When editing, the image of one or several electrocardiosignals is displayed on the display screen, the viewing speed can be accelerated or slowed down. I exclude sections of the electrocardiogram distorted by artifacts at 2 1 / С and - / I / t

are chatting.

Improving the accuracy of the removal of electrocardiograms in the inventive cardiac analyzer in comparison with the prototype is achieved due to the fact that during the measurement the signal level in each channel is fixed using a storage and sampling circuit, and the gain of each channel is equalized by changing the gain of amplifier 5. The measurement accuracy is further increased by due to the regular balancing of the amplifier channels - compensation of the zero drift of the amplifiers by changing the bias voltage of the amplifier 5.

The cardiocycle analysis program in computer 8 allows you to calculate the following indicators:

- heart rate beats / min;

Duration of R-R intervals in ms;

- duration of QRS - complex in ms; . - duration of the QT - interval in ms;

- the long duration of the QT - interval in ms, determined by the Bazetta formula;

- duration of the PQ - interval in ms;

Duration P - waves in ms;

-Macroose coefficient (Macrouse index);

- the position of the electrical axis of the heart (angle alpha, calculated by the position of the QRS wave) and the electrical axis for the waves T and R.

Based on these indicators, a diagnosis is established and the functional state of the cardiovascular system is determined.

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-№ FORMULA

Claims (3)

1. Cardiac analyzer containing a multichannel converter amplifier, the outputs of which are connected to the first group of inputs of a multichannel analog switch, serially connected by an analog-to-digital converter, an interface and an electronic computer with a display and a recording unit, characterized in that between the output of the multichannel analog switch and the input An analog-to-digital converter includes an amplifier with controlled gain and bias voltage, and multi-channel outputs of transducing amplifier further inputs connected selectively multichannel amplifier, each amplifier channel which includes a controllable passband and sample and storage device, outputs of which are connected to additional inputs of multichannel analog switch. 2. The cardiac analyzer according to claim 1, characterized in that the interface comprises a microprocessor connected through an information exchange unit to an electronic computer and through an interface unit to the passband control inputs of a multi-channel selective amplifier, channel switching of a multi-channel analog switch, and the output of an analog-to-digital converter and amplifier control inputs with controlled gain and bias voltage. 3. The cardiac analyzer according to claim 2, characterized in that the interface unit comprises a decoder of recording signals, the digital inputs of which are connected to the microprocessor address bus, and a resolution input is connected to the write circuit of the microprocessor control bus, a decoder of read signals, the digital inputs of which are connected to the bus the microprocessor address, and the permission input with the control bus read signal circuit, four storage registers, the digital inputs of which are connected to the microprocessor data bus, and the recording input of each one with the corresponding output ohm of the write signal decoder, a D-trigger, whose input D is connected to the low-order bit of the data bus, input C - to the first output of the read signal decoder, and the output - to the "Conversion" input of the analog-to-digital converter, a match circuit, the first input of which is connected with the second output of the read signal decoder, the second input with the ADC Ready output of the analog-to-digital converter, and the output with the read input of the fifth storage register, the digital inputs of which are connected to the code output of the analog-to-digital converter while the outputs are with the microprocessor data bus, the outputs of the first storage register are connected to the bandwidth control inputs of a multi-channel selective amplifier, the outputs of the second register are connected to the channel switching control inputs of a multi-channel analog switch, the outputs of the third register are connected to the amplifier gain control inputs with controlled gain and bias voltage, the outputs of the fourth register to the inputs of the control bias voltage of the amplifier with controlled coefficient gain volume and bias voltage.