RO59566A - - Google Patents
Info
- Publication number
- RO59566A RO59566A RO58603A RO5860368A RO59566A RO 59566 A RO59566 A RO 59566A RO 58603 A RO58603 A RO 58603A RO 5860368 A RO5860368 A RO 5860368A RO 59566 A RO59566 A RO 59566A
- Authority
- RO
- Romania
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4818—Priority circuits therefor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Bus Control (AREA)
- Communication Control (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US71161868A | 1968-03-08 | 1968-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| RO59566A true RO59566A (ro) | 1976-03-15 |
Family
ID=24858816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| RO58603A RO59566A (ro) | 1968-03-08 | 1968-12-21 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US3576542A (ro) |
| DE (1) | DE1806172C3 (ro) |
| FR (1) | FR1600134A (ro) |
| GB (1) | GB1255993A (ro) |
| RO (1) | RO59566A (ro) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL158626B (nl) * | 1972-03-31 | 1978-11-15 | Philips Nv | Prioriteitsteller. |
| US3866181A (en) * | 1972-12-26 | 1975-02-11 | Honeywell Inf Systems | Interrupt sequencing control apparatus |
| IT988956B (it) * | 1973-06-12 | 1975-04-30 | Olivetti & Co Spa | Governo multiplo |
| US4000485A (en) * | 1975-06-30 | 1976-12-28 | Honeywell Information Systems, Inc. | Data processing system providing locked operation of shared resources |
| US4105978A (en) * | 1976-08-02 | 1978-08-08 | Honeywell Information Systems Inc. | Stretch and stall clock |
| US4443848A (en) * | 1979-09-10 | 1984-04-17 | Nixdorf Computer Corporation | Two-level priority circuit |
| US4310880A (en) * | 1979-09-10 | 1982-01-12 | Nixdorf Computer Corporation | High-speed synchronous computer using pipelined registers and a two-level fixed priority circuit |
| GB2215874A (en) * | 1988-03-23 | 1989-09-27 | Benchmark Technologies | Arbitration system |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3239819A (en) * | 1960-11-07 | 1966-03-08 | Gen Electric | Data processing system including priority feature for plural peripheral devices |
| US3289168A (en) * | 1962-07-31 | 1966-11-29 | Ibm | Interrupt control system |
| US3331055A (en) * | 1964-06-01 | 1967-07-11 | Sperry Rand Corp | Data communication system with matrix selection of line terminals |
| GB1077339A (en) * | 1965-04-05 | 1967-07-26 | Ibm | Control device for a data processor |
| US3395394A (en) * | 1965-10-20 | 1968-07-30 | Gen Electric | Priority selector |
-
1968
- 1968-03-08 US US711618A patent/US3576542A/en not_active Expired - Lifetime
- 1968-10-30 DE DE1806172A patent/DE1806172C3/de not_active Expired
- 1968-12-21 RO RO58603A patent/RO59566A/ro unknown
- 1968-12-31 FR FR1600134D patent/FR1600134A/fr not_active Expired
-
1969
- 1969-02-25 GB GB9946/69A patent/GB1255993A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE1806172A1 (de) | 1969-12-04 |
| DE1806172C3 (de) | 1974-05-16 |
| DE1806172B2 (de) | 1973-10-18 |
| FR1600134A (ro) | 1970-07-20 |
| GB1255993A (en) | 1971-12-08 |
| US3576542A (en) | 1971-04-27 |