RO128328A2 - Identification of the parts of the sum for np-complete problems of subset-sum type by using a digital device - Google Patents

Abstract

The invention relates to an electronic device which allows the identification of the parts of the sum for NP complete problems of subset-sum type within the computational complexity theory field, with applications in the cryptography and optimization. According to the invention, the device comprises a cascade module (), a module () for computing the partial sum, a module () for checking the status of the circuit, a module () for generating and synchronizing the clock signal and a module () for storing the status.

Description

The invention relates to an electronic device that allows the identification of parts of the sum for complete NP problems of the "subset-sum" type. The proposed device identifies a solution represented as a subset of values.

In computer science, the "subset-sum" problem is an important classical problem in the field of computational complexity theory with applications in cryptography and optimization. This problem is defined as: giving a lot of positive integers and a sum number. it is required to check if there is an unseen subset of this set such that the sum of its elements equals the sum number.

The "subset-sum" problem is NP-complete (unresolvable in deterministic polynomial time). Many NP-complete combinatorial optimization problems can be reduced to this problem. The existence of a quick problem-solving process can be used, for example, in decrypting messages using cryptographic schemes of this type. The proposed process can be generalized and used in solving some difficult (NP-complete) problems of combinatorial optimization and cryptography. Practical optimization problems to which the invention can be applied are also those of the bin packing type. Thus, the proposed device has applicability in solving the problems of efficient allocation of resources such as: cutting of materials with minimum losses, optimal packaging of objects in a container, optimal allocation of execution times of processes, optimal use of transport spaces or storage and other similar issues.

For the purpose of solving the "subset-sum" problem, no dedicated physical device is known. For this purpose, only software implementable models and algorithms are known on a computer.

The technical problem solved by the invention is the creation of an electronic device that offers an efficient solution for the NP-complete "subset-sum" problem, which means having both a reduced computation time and a complexity and also implementation costs. reduced.

The electronic device that solves the complete NP problem "subset-sum" is based on an original model, called a cascade system. This model is described in the patent application with the title: "Process for solving the NP complete subset-sum problem". The cascade system has a linear structure and is formed by the chain of several nodes that process binary signals. The hardware implementation of this device is described in the patent application entitled "Electronic device for solving the NP-complete" subset-sum problem.

In addition to the previous patent proposal with the title "Electronic device for solving the NP-complete problem" subset-sum ", in this patent application it is proposed how to identify parts of the sum in the problem" subset-sum ".

The following is an example of embodiment of the invention, in connection with Figure 1, which represents the electronic device that allows the identification of parts of the sum for complete NP problems of the "subset-sum" type. The electronic device (fig. 1) is described by its electrical scheme and is composed of the following elements that have been grouped on modules for easier understanding:

The module for calculating the partial sum, (1), receives as input signals:

The values, in binary format, of the elements of the set, in the form of numerical constants. in the exemolified case these are: 2.3.5.7 and-ϋ-.

a

^ -2 0 1 1 - 0 0 9 8 7 - ³ ο -09- 2011

o Binary signals representing the selection of the sum elements, a binary value 0/1 for each element of the set. These signals come from the state memory module (22), more precisely from the outputs of the D-type bistable (24) and are visually signaled by the LEDs (26).

The output of the calculation of the partial amount (1) corresponds to the output of the difference component (3) and is equal to the difference between the sum value and the value of the partial amount at a given time. The value of the partial sum is calculated using the cascading assembly components (2) that receive at the inputs the value of the element of the set if the element is selected or the value 0 otherwise. The decision is made using the components of the ordered buffer type (4).

The module for checking the state of the circuit (7) has the role of checking whether a solution has been found and / or if the calculation has been completed. This module receives at its input the output of the calculation of the partial sum (1) calculated as explained above as well as the output of the binary counter (6). At the output, the circuit status check module (7) provides two binary signals that are displayed using two LEDs: finished calculation (13) indicating the completion of the calculation and the non-calculable sum (12) which, if in logic state 1, indicates the fact that no solution was found. For this, the circuit status check module (7) uses the comparator blocks (8), the D-type bistable (9), two SI logic gates (11) and an inverting gate (10). The module also receives the reset signal from the reset master button (26), a signal that is applied to the reset input of the D-type bistable (9).

The module for generating and synchronizing the tact (14) receives at the input a binary signal that is given by the result of the logical OR operation between the completed calculation signals (13) respectively the non-calculable amount (12) as well. The same mode also receives the reset signal from the reset master button (26), a signal that is applied to the rest input of the D-type bistable (16). The module for generating and synchronizing the tact (14) also contains a logic gate SI with three inputs (18) respectively an inverter (17).

The cascade module (21) implements the specific components of the cascade system described in the patent application with the title "Procedure for solving the NP complete subset-sum problem". Explanations regarding its implementation for the problem of "sub-set sum" verification can be found in the patent application entitled "Electronic device for solving the NP-complete" subset-sum problem ". This module receives as inputs:

o The tactile signal, which comes from the output of the generation and synchronization of the tact (14), o The signal from the output of the binary counter (6), o A reset signal that is obtained at the output of the logic portion OR (20), carries which performs a logical OR operation between the remaining master signal (27) and a second signal that comes from the circuit status check module (7). This reset signal applies to both the binary counter (6) and the shift registers (19).

o For each displacement register, an input with validation role of signal propagation is provided, which comes from the state memory module (22), more precisely from the SI logic gate outputs (23).

The cascade module outputs represent the outputs of the shift registers (19) that are used by the state memory module (22). displacement (22) corresponds to the elements of the given set, having exactly $ â £ ^ Bf £ WTememory of the value of each element of the essential set in ^ -2 0 1 1 - 0 0 987-3 3 0-05-20- the circuit operation is like the elements the amount to be ordered in ascending order, from left to right.

The state memory module (22) has the role of storing the correct solution if it is found. The module consists of D-type bistables (24), (25) respectively SI and OR logic gates with two inputs, according to the diagram in figure 1. The module receives the reset master signal (27) which is applied to the bistable reset inputs. D (24) and (25). It also receives the signal called "READY" from the circuit status module (7). The outputs of the state memory mode (22) represent the binary signals displayed with the help of the LEDs (26), which is precisely the solution of the "subset-sum" problem in the form of the selection of the elements of the assembly that give the sum value, if at least one solution exists.

Pressing the reset master button (27) restores the calculation that results in the LED display (26) displaying the solution of the problem if at least one solution exists. If no solution is found then the execution ends with the LED ignition for the non-calculable amount (12).

By using the proposed electronic device to find a solution to the complete NP problem "subset-sum" the following advantages are obtained:

easy and relatively low cost hardware implementation, unlike most of the existing algorithms, which have been designed for software implementations, high working speed due to complexity while being linear with respect to sum value, reduced realization costs due to space complexityJ ^^ LOAD the sum of the elements of the given set. 'W

Claims (1)

An electronic device for identifying parts of the sum for complete NP problems of the "subset-sum" type, characterized in that it implements an original model proposed by the authors of the invention, called a "cascade system", implemented in the form of the cascade module (21), having in addition a series of additions that also allow the parts of the verified amount to be identified. These additions are: the module for calculating the partial amount (1), the module for checking the state of the circuit (7) and the module for storing the state (22). An electronic device according to claim 1, characterized in that the modules of the cascade system are implemented by means of displacement registers (19) of logical OR-type gates and SI-type gates (23), the latter allowing the system modules to be switched off. cascade and identifying parts of the sum. An electronic device according to claims 1 and 2, characterized in that the module for calculating the partial sum (1), the circuit state control module ^ j ^^ x | j respectively the state memory module (22) are implemented according to the diagram elq ^^^? from figure 1.