RO108617B1 - 4 mb memorizing modulus - Google Patents

Abstract

The invention relates to a 4MB memory, characterized in that it has composing some buffer memories, signals data (BUFD), address (BUFA) and control (BUFC), Buffer Buffer (BUFC) transmitting signals to a control block (BC), address buffer by transmitting signals a Selection and Switching Block (BSCA), also receiving signals from a local counter (CNTR) commanded by the control unit (BC), a memory array (MEM), with the capacity of 4MB memory receiving the addresses from the block Selection and Switching Addresses (BSCA), Signals control from the control unit (BC) and signals from the control unit data from Buffer Data Buffer (BUFD) through via a data latch (LD) circuit and transmitting data signals directly Buffer Data Buffer (BUFD). By applying the invention extends memory capacity from 256 KB and 1MB to 4MB.

Description

The present invention relates to a 4MBytes memory module, with built-in controller, for equipping a minicomputer.

Known memory modules, 256 KB and 1 MB.

In principle, such a memory block with its own built-in controller consists of:

- a two-way, data buffer;

- an address buffer;

- a control module consisting of a buffer for control signals and a control block;

- an address selection and switching block;

- a memory array having separate input / output ports.

The signals on the computer bus are received by the three buffers, and the control block takes the signals received by them and synthesizes the commands for the operation of the memory array.

The disadvantage of these memory modules is the limited capacity of up to 1 MB, determined by the size of the card.

There is also known a large-capacity, organized, three-dimensional memory module with n matrix elements arranged matrix, addressed both by two counters common to all the elements, as well as by n counters corresponding to each element and which have on the input path of data a serial recirculation register, for writing, which is loaded in parallel through a buffer register, and on the output path a similar register for reading, which is loaded through another buffer register and transmits the display data. /1/

The object of the invention is to provide the maximum memory capacity of the computer on a single board.

The problem solved by the invention is to achieve a memory capacity of 4 MB on a platter ^- the same size as the 256 platter.

KB, respectively 1 MB.

The 4 MB memory module, according to the invention, removes the disadvantages mentioned above by using a memory matrix with 256 K x 4 chips for data, respectively 256 K x 1 for parity, the matrix receiving control signals from a block. command signals, address signals from an address selection and switching block and an internal address counter, respectively, transmitting data directly to a data buffer and receiving data via a data lock circuit (latch), command of control signals provided by the control block.

According to the invention, the memory module has the following advantages:

- increased memory capacity (4 MB) at reduced size;

- increased reliability;

- cost price per reduced memory unit;

- elimination of errors in data entry by intermediate storage in a data latch;

- increased computing speed.

The following is an example of embodiment of the invention in connection with FIG. 1 ... 28, which represents:

FIG. 1 is a block diagram of the memory module according to the invention;

FIG. 2, control block diagram;

FIG. 3 ... 11, control and address signal buffer schemes;

FIG. 12 ... 18, schematics of the data lock block and the data buffer;

FIG. 19 ... 24, diagrams of the address selection and switching block;

FIG. 25 ... 28, schematics of the memory array.

According to FIG. 1, from the MCC computer bus, three categories of signals are extracted: MBC commands, MBA addresses, MBD data.

Each of the three categories of signals is applied to a buffer or buffer, respectively: BUFC control signals, BUFA addresses, BUFD data. The control signal buffer also transmits signals to a control block, BC.

The control signal buffer together with the control block forms the control module, MC.

The control block controls the data buffer on the one hand, determining the data transfer direction (to or from the computer bus), and on the other hand it controls an address selection and switching block, BSCA This block, BSCA receives the addresses of to the BUFA address buffer and from a local counter, CNTR, for memory regeneration addresses. These addresses are transmitted to a memory array, MEM, together with the control signals from the control block, BC, and the data signals. The memory matrix, MEM, is equipped with memories of type 256 K x4, for data, these being characterized by the fact that the data inputs and outputs are made on the same pins. These pins connect on one side to the data buffer (to transmit signals from memory to the buffer) and on the other to a data blocking circuit, LD, to receive signals from the data buffer to memory array, MEM.

In turn, LD is commanded by an MCI signal that gives the command to store the data in the blocking circuit, signal provided by the buffer of the control signals, BUFC.

The operation of the module described is the following:

- In the read cycle from memory, the BUFA address buffer provides through the address selection and switching block the address of the memory location from which the data is to be extracted. The control block BC operates the BUFD data buffer that transfers the data provided by the matrix to the MCC computer bus.

- at the write cycle, the addresses are transmitted to the MEM memory matrix, and the buffer memory of the BUFC control signals activates through the MCI signal the data lock circuit, LD, which stores the data received from the BUFD data buffer on the bus. MCC computer. In the following sequence, the control block BC, provides the control signals necessary for the MEM memory arrays to retrieve data from the data block, LD. This, LD, is so constructed that it is reset before any new MCC bus access. The data transfer is done in the two sequences in 16-bit words.

The memory regeneration cycle is not described, it is identical to the one of the known 256 KB and 1 MB modules.

Fig. 2 contains the control block diagram. With memory inputs the control signals on the bus, he synthesizes the signals:

- REFEN - for a regeneration cycle that ensures the information is stored in the memory chips. The original resolution solution is presented, a conflict between an external request for access and the internal access for information regeneration;

- CYEN - for external access at work;

- MPX - for address switching;

- RASEN, CASEN - strobes for addresses provided to memory arrays;

- NDATAEN, MCI - for establishing the data transfer direction through BUFD data buffer.

Fig. 3 ... 11 contain:

- BUFD address buffer represented by integrated circuits 16A 16B, 15B (fig. 3 ... 5).

- Buffer memory of control signals, with integrated circuit 13A (fig. 6).

- The BSCA address switching block represented by the integrated circuits 15E, 16E, 16F, 16D controlled by the MPX and RFEN signals generated by the control block (fig. 7 ... 10).

Fig. 12 ... 18, contain:

- BUFD data buffer represented by integrated circuits 14F, 14D, 14B, 14A controlled by the NDATAEN signal provided by the control block BC (fig. 12);

- The LD data blocking circuit represented on integrated circuits 12F, 12B, controlled by the MCI signal generated by the control block BC (fig. 13);

- Circuits 11F, 11B, 13F, 13B ensure the generation and verification of memory parity, control necessary for its correct functioning (Figs. 14 ... 17).

Fig. 19 ... 24 contain the synthesis part of the address synthesis and switching block by:

- Circuits 15D, 09E, 09B, which ensure the logical multiplication of the addresses (fig. 19 ... 21);

- The circuits UD, IOD '- IOD, IOC' IOC, 09D '- 09D, 09C - 09C that ensure the selection of the line in the memory matrix (figs. 22, 23).

Fig. 25 ... 28 contain the logic schema of the memory matrix. This is accomplished with dynamic MOS, MiLL, MiLH, MiHL, MiHH, MjLL, MjHL, MjHH integrated circuits where i = 0, 1, 2, 3 and j = 4, 5, 6, 7 with a capacity of 256 x 4

Kbiți for data and MiLP, MiHP, and

MjHP in which i = 0, 1, 2, 3 and j = 4, 5,

6.7 with a capacity of 256 x 1 Kbit for storing parity.

Claims (1)

Claim The 4 MB memory module, characterized in that it has some data buffer (BUFD), address (BUFA) and control (BUFC) buffers, the control buffer (BUFC) transmitting signals to a control block (BC), the address buffer transmitting signals to an address selection and switching block (BSCA), receiving signals from a local counter (CNTR) commanded by the control block (BC), a memory array (MEM) with 4MB memory capacity receiving addresses from the address selection and switching block (BSCA), control signals from the control block (BC) and data signals from the data buffer (BUFD) via a blocking circuit of data (LD) and transmitting data signals directly to the data buffer (BUFD).